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Title:
CIRCUIT AND METHOD FOR SENSING BIT-LINE MULTI-LEVEL VOLTAGE
Document Type and Number:
WIPO Patent Application WO/2023/022299
Kind Code:
A1
Abstract:
The present invention relates to a circuit for sensing a bit-line multi-level voltage for a multi-bit operation of a DRAM including a memory cell for storing data by the operation of a word line and a bit line, the circuit comprising: a comparator including a first input terminal coupled to a first ranked bit voltage source and a second input terminal coupled to a bit line corresponding to a memory cell; an (n-1)th ranked bit switch module including an (n-1)th capacitor, an (n-1)th common switch, and an (n-1)th positive/negative switch, each of which is coupled to the bit line in parallel with the memory cell; and a bit voltage selection unit for turning on one of switches in response to a read signal for reading data recorded in the memory cell.

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Inventors:
CHO SEONG HWAN (KR)
LEE GI WOO (KR)
Application Number:
PCT/KR2021/016745
Publication Date:
February 23, 2023
Filing Date:
November 16, 2021
Export Citation:
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Assignee:
KOREA ADVANCED INST SCI & TECH (KR)
International Classes:
G11C11/4091; G11C7/12; G11C11/408; G11C11/4094
Foreign References:
KR20140134835A2014-11-25
KR20130045803A2013-05-06
KR20090109823A2009-10-21
JP2014519793A2014-08-14
US20110221520A12011-09-15
Attorney, Agent or Firm:
SU INTELLECTUAL PROPERTY (KR)
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