Title:
COLUMNAR SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
Document Type and Number:
WIPO Patent Application WO/2016/084205
Kind Code:
A1
Abstract:
Apertures are formed in a gate insulation layer and a gate conductive layer at the outer circumferential part of the middle position of a Si column (6), and at the outer circumferential part of these apertures a stacked layer, wherein a Ni film and two each of a poly-Si layer and a SiO2 layer (17a, 17b) containing donor or acceptor impurity atoms are stacked, is formed. Thermal processing is performed, thereby silicidizing the poly-Si layer, and an N+ region (2a) and a P+ region (3a) forming the source and drain of a surrounding gate MOS transistor (SGT) are formed by diffusion of the donor or acceptor impurity atoms into the Si column (6) from NiSi layers (20a, 20b) that project toward and make contact with the side surface of the Si column (6) as a result of the silicidation.
Inventors:
MASUOKA FUJIO (JP)
HARADA NOZOMU (JP)
HARADA NOZOMU (JP)
Application Number:
PCT/JP2014/081455
Publication Date:
June 02, 2016
Filing Date:
November 27, 2014
Export Citation:
Assignee:
UNISANTIS ELECT SINGAPORE PTE (SG)
MASUOKA FUJIO (JP)
HARADA NOZOMU (JP)
MASUOKA FUJIO (JP)
HARADA NOZOMU (JP)
International Classes:
H01L21/336; H01L21/8238; H01L27/092; H01L29/78
Domestic Patent References:
| WO2014184933A1 | 2014-11-20 |
Foreign References:
| JP2012004473A | 2012-01-05 | |||
| JPH0613623A | 1994-01-21 | |||
| EP1804286A1 | 2007-07-04 | |||
| JP2010258345A | 2010-11-11 | |||
| JP2014013792A | 2014-01-23 |
Attorney, Agent or Firm:
KIMURA MITSURU (JP)
Mitsuru Kimura (JP)
Mitsuru Kimura (JP)
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