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Title:
COMPUTE-IN-MEMORY CHIP, AND MEMORY UNIT ARRAY STRUCTURE
Document Type and Number:
WIPO Patent Application WO/2020/258360
Kind Code:
A1
Abstract:
Provided are a compute-in-memory chip and a memory unit array structure. The memory unit array comprises: multiple memory unit sub-arrays arranged in an array. The memory unit sub-arrays comprise: multiple switch units and multiple memory units arranged in an array. The memory units have an adjustable threshold voltage. In each column, all memory units have a first end thereof connected to a source line and a second end thereof connected to a bit line. In each row, all memory units have a third end thereof connected to a word line via one of the switch units. Multiple rows of memory units are correspondingly connected to the multiple switch units, each of the multiple switch units has a control end thereof connected to a local word line of the memory unit sub-array, and the local word line is controlled to control whether to activate the memory unit sub-array. In this way, the invention enables all memory unit sub-arrays in one row to share multiple DACs, and all memory unit sub-arrays in one column to share multiple ADCs, thereby reducing the circuit area, lowering the circuit cost, and meeting requirements of a high integration level and a low cost.

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Inventors:
WANG SHAODI (CN)
Application Number:
PCT/CN2019/094769
Publication Date:
December 30, 2020
Filing Date:
July 05, 2019
Export Citation:
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Assignee:
BEIJING ZHICUN WITIN TECH CORPORATION LIMITED (CN)
International Classes:
G11C16/04; G11C16/08; G11C16/10; G11C16/24
Foreign References:
CN209766043U2019-12-10
CN100530430C2009-08-19
CN103177758A2013-06-26
US20190057727A12019-02-21
CN108777155A2018-11-09
Other References:
PATIL, A.D. ET AL.: "An MRAM-Based Deep In-Memory Architecture for Deep Neural Networks", IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS(ISCAS), 1 May 2019 (2019-05-01), XP033573932, ISSN: 2158-1525, DOI: 20200228104559Y
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