Title:
COPPER-CLAD LAMINATE FOR FORMING INTEGRATED CAPACITOR LAYER, MULTILAYER PRINTED WIRING BOARD, AND PRODUCTION METHOD FOR MULTILAYER PRINTED WIRING BOARD
Document Type and Number:
WIPO Patent Application WO/2015/125928
Kind Code:
A1
Abstract:
The purpose of the present invention is to provide a capacitor-layer-forming material or the like with which, when drilling is used to form through-hole-forming holes in the production of a multilayer printed wiring board having an integrated capacitor circuit and a high number of layers, cracks are not formed in a capacitor dielectric layer. Accordingly, a copper-clad laminate for forming an integrated capacitor layer is provided, which is used in order to form, as an inner layer of a multilayer printed wiring board, an integrated capacitor circuit comprising a copper layer, a capacitor dielectric layer, and a copper layer. The copper-clad laminate for forming the integrated capacitor layer is characterized in that the complex elastic modulus (Er) of a resin film in the thickness direction, said resin film configuring the capacitor dielectric layer, is less than 6.1 GPa.
Inventors:
KUWAKO FUJIO (JP)
MATSUSHIMA TOSHIFUMI (JP)
HOSOI TOSHIHIRO (JP)
MATSUSHIMA TOSHIFUMI (JP)
HOSOI TOSHIHIRO (JP)
Application Number:
PCT/JP2015/054832
Publication Date:
August 27, 2015
Filing Date:
February 20, 2015
Export Citation:
Assignee:
MITSUI MINING & SMELTING CO (JP)
International Classes:
H05K3/46; B32B15/08
Domestic Patent References:
| WO2005107350A1 | 2005-11-10 |
Foreign References:
| JP2008235545A | 2008-10-02 | |||
| JP2004071589A | 2004-03-04 | |||
| JP2007273530A | 2007-10-18 |
Attorney, Agent or Firm:
YOSHIMURA, KATSUHIRO (JP)
Katsuhiro Yoshimura (JP)
Katsuhiro Yoshimura (JP)
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