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Patent Searching and Data


Title:
COPROCESSOR FOR COMPLEX CALCULATION PROCESSING, AND PROCESSOR SYSTEM
Document Type and Number:
WIPO Patent Application WO/2012/111053
Kind Code:
A1
Abstract:
In order to enable the execution of various modulation/demodulation/synchronization processes in multiple wireless communication systems quickly and efficiently with one system, a coprocessor (11) for complex calculation processing that forms a processor system (100) is equipped with: a complex calculation circuit (22) that, in response to command from a main processor (10), executes complex calculations with respect to complex number data, said calculations being required for wireless communication; and memory controllers (20, 21) that operate in parallel with the complex calculation circuit, accessing memories. The complex calculation circuit (22) is provided with a trace circuit that monitors the calculation result data for the complex number data series that have been read sequentially from the memories, and detects a normalization coefficient for the purpose of performing a normalization process on the calculation result data.

Inventors:
TAKEUCHI TOSHIKI (JP)
IGURA HIROYUKI (JP)
Application Number:
PCT/JP2011/005222
Publication Date:
August 23, 2012
Filing Date:
September 15, 2011
Export Citation:
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Assignee:
NEC CORP (JP)
TAKEUCHI TOSHIKI (JP)
IGURA HIROYUKI (JP)
International Classes:
G06F9/38; G06F17/16; H04B1/707; H04J11/00
Foreign References:
JP2006262322A2006-09-28
JP2003016051A2003-01-17
Other References:
HIROYUKI IKURA: "An 800MOPS, 110mW, 1.5V, Parallel DSP for Mobile Multimedia Processing", PROCEEDINGS OF THE 1998 IEICE GENERAL CONFERENCE, 6 March 1998 (1998-03-06), pages 141
Attorney, Agent or Firm:
IEIRI, Takeshi (JP)
House ON 健 (JP)
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Claims: