[0001] This description relates generally to electronic circuits, and more particularly to a current regulator system.

BACKGROUND

[0002] Power supply circuits can be implemented in a variety of different ways. Examples of power supply circuits include synchronous rectifier power converters, asynchronous rectifier power converters, resonant power converters, and any of a variety of other types of switching power converters. A typical power supply circuit can thus activate one or more switches to convert an input voltage to an output voltage. Power supply circuits are typically implemented in wireless electronic devices. As a result, the input voltage is typically provided by a battery. Thus, the operational life of the battery is typically limited by the amplitude of the input current that is provided from the input voltage to generate the output voltage in the power supply circuit. For example, in a switching power supply circuit that provides current through an inductor, the operational life of the battery can be based on an average amplitude of the input current through an operating cycle of the switching power supply circuit.

SUMMARY

[0003] An example circuit includes a switching voltage regulator having a first input, a second input, and an output. The first input is coupled to a source of an input current. A current regulator has an input, a first output and a second output. The input is coupled to the source of the input current. The current regulator provides at the first output a comparison signal having a logic state responsive to a current sampling voltage. The current regulator provides a reference current at the second output proportional to a maximum average amplitude setpoint of the input current over a switching period of the switching voltage regulator. A switch controller has a first input, a second input, a third input and an output, the first input coupled to the first output of the current regulator circuit. The second input is coupled to the output of the switching voltage regulator, and the third input is adapted to be coupled to a reference voltage source. The output is coupled to the second input of the switching voltage regulator.

[0004] An example of a power supply system includes a switching voltage regulator comprising at least one switch configured to conduct an input current to generate an output voltage responsive to a switching signal and based on an input voltage. The system also includes a current regulator configured to generate a current sample voltage based on an amplitude of the input current relative to a reference current defining a maximum average amplitude setpoint of the input current to set a switching time defining a switching period of the at least one switch. The system also includes a switch controller configured to provide the switching signal to control the at least one switch based on an amplitude of the output voltage relative to a reference voltage and based on the switching time.

[0005] An example of an integrated circuit (IC) includes a switching voltage regulator comprising at least one switch configured to conduct an input current to generate an output voltage responsive to a switching signal and based on an input voltage. The IC also includes a current regulator configured to generate a current sample voltage across a sampling capacitor. The current sample voltage can be based on an amplitude of the input current relative to a reference current that is set at a first external pin and which is proportional to a maximum average amplitude setpoint of the input current to set a switching time defining a switching period of the at least one switch. The IC includes an input pin adapted to be coupled to a source of the reference current. The IC further includes a switch controller configured to provide the switching signal to control the at least one switch based on the switching time and based on an amplitude of the output voltage relative to a reference voltage that is set at a second external pin. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] FIG. 1 is an example of a block diagram of a power supply system.

[0007] FIG. 2 is an example of a schematic electrical circuit diagram of a power supply circuit. [0008] FIG. 3 is an example of timing diagrams.

[0009] FIG. 4 is another example of timing diagrams.

[0010] FIG. 5 is an example of a schematic electrical circuit diagram of current flow in a power supply circuit.

[0011] FIG. 6 is another example of a schematic electrical circuit diagram of current flow in a power supply circuit.

[0012] FIG. 7 is another example of a schematic electrical circuit diagram of a power supply circuit.

[0013] FIG. 8 is another example of a schematic electrical circuit diagram of current flow in a power supply circuit.

[0014] FIG. 9 is another example of a schematic electrical circuit diagram of current flow in a power supply circuit.

[0015] FIG. 10 is another example of a schematic electrical circuit diagram of current flow in a power supply circuit.

[0016] FIG. 11 is another example of a schematic electrical circuit diagram of current flow in a power supply circuit.

[0017] FIG. 12 is another example of a schematic electrical circuit diagram of current flow in a power supply circuit.

[0018] FIG. 13 is another example of a schematic electrical circuit diagram of current flow in a power supply circuit.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

[0019] This description relates generally to electronic circuits, and more particularly to a current regulator system. The current regulator system can be included in a power supply system, such as a switching power supply system. The power supply system can also include a switching voltage regulator that includes at least one switch that is controlled by a switch signal to provide an input current from an input voltage and through an inductor to generate an output voltage. The power supply system further includes a switch controller that is configured to generate the switch signal, such as based on the output voltage relative to a reference voltage, and to a current sampling voltage that has an amplitude associated with a switching time of the switching voltage regulator to regulate an amplitude of the input current.

[0020] As an example, the input voltage is provided from a battery. Therefore, the current regulator system can be configured to regulate the amplitude of the input current to mitigate current draw from the battery, and to therefore extend the operating life of the battery. The current regulator system can include a sampling capacitor that is configured to generate the current sampling voltage that is based on a sampling current. The sampling current can be based on a charging current that is associated with the input current and a reference current. As one example, the charging current is generated based on the input current and which is proportional to the input current. As another example, the charging current is a current that has a fixed amplitude that is estimated to be proportional to the input current. The reference current can have an amplitude that is proportional to a maximum average amplitude setpoint of the input current over a switching period.

[0021] The current sampling voltage can have an amplitude that is based on the amplitude of the charging current minus a reference current during a first switching phase of the switching voltage regulator. For example, the reference current is arranged to flow from the sampling capacitor. Thus, during the first switching phase of the switching voltage regulator, the amplitude of the current sampling voltage can increase. During a second switching phase of the switching voltage regulator, the amplitude of the current sampling voltage can be based on the reference current only, such that the amplitude of the current sampling voltage can decrease during the second switching phase of the switching voltage regulator. The duration of time between the beginning of charging of the sampling capacitor in the first sampling phase to the end of the discharging of the sampling capacitor in the second sampling phase (e.g., between equal charges of approximately zero) can define the switching time of the switching voltage regulator. Thus, the switch controller can monitor the amplitude of the current sampling voltage to switch between the switching phases of the switching voltage regulator, and to thus regulate the amplitude of the output voltage and the input current.

[0022] FIG. 1 is an example of a block diagram of a power supply system 100. The power supply system 100 can be implemented in any of a variety of wireless electronic devices, such as laptop computers, tablet computers, smart phones, or any of a variety of other electronic devices. The power supply system 100 is configured to generate an output voltage VOUT from an input voltage Vi _N. As an example, the input voltage V _IN is provided from a battery. As described herein, the power supply system 100 can provide regulation of an input current h _N that is drawn from a battery to mitigate an average amplitude of the input current h _N , and therefore to extend the operational life of the battery. As an example, the power supply system 100 is fabricated on or as part of an integrated circuit (IC).

[0023] The power supply system 100 includes a switching voltage regulator 102 that includes at least one switch 104 that is controlled by a respective at least one switching signal, shown in the example of FIG. 1 as a signal SS, to generate the output voltage VOUT based on the input voltage VIN. AS an example, the switching voltage regulator 102 operates as a buck regulator or a boost regulator, and/or operates in buck and boost modes, to generate the output voltage VOUT· For example, the switch(es) 104 include a high-side switch (e.g., P-channel field effect transistor (PFET)) and a low-side transistor (e.g., N-channel field effect transistor (NFET)) that are alternately activated to provide current through an inductor to generate the output voltage VOUT at an output of the switching voltage regulator 102. As described herein, the activation of the switch(es) 104 can be defined by switching phases, such as a first switching phase and a second switching phase, that define changes in the current through the inductor and which collectively define a switching period of the switching voltage regulator 102.

[0024] The power supply system 100 also includes a current regulator system 106 that is configured to regulate an amplitude of the input current Ii _N. As described above, the input current h _N can be drawn from a battery, such that monitoring and regulating the amplitude of the input current h _N can result in an extension of the operational life of the battery. In the example of FIG. 1, the current regulator system 106 includes a reference current generator 108 that is configured to generate a reference current that has an amplitude that is proportional to a maximum average amplitude setpoint of the input current h _N over a switching period. As an example, the reference current generator 108 is set at an external pin of the associated IC on which the power supply system 100 is fabricated (e.g., as a grounded resistor).

[0025] The current regulator system 106 can include a sampling capacitor that is configured to generate a current sampling voltage VSMPL that is based on a charging current that is associated with the input current I _IN and based on the reference current. As one example, the charging current is a current that is generated based on the input current h _N and which is proportional to the input current Ii _N. As another example, the charging current is a current that has a fixed amplitude that is estimated to be proportional to the input current. For example, the charging current and the reference current are each proportioned in amplitude with respect to the input current h _N , such that the reference current is proportional to the maximum average amplitude setpoint of the input current h _N over a switching period.

[0026] As an example, the current sampling voltage VSMPL has an amplitude that is based on the amplitude of the charging current minus the reference current during a first switching phase of the switching voltage regulator 102, such as defined by the switching signal(s) SS. For example, the reference current flows from the sampling capacitor to pull current away from the charging current that is provided to the sampling capacitor. Thus, during the first switching phase of the switching voltage regulator 102, the amplitude of the current sampling voltage VSMPL can increase, and can be proportional to the sensed amplitude of the input current Ii _N. During a second switching phase of the switching voltage regulator 102, the amplitude of the current sampling voltage VSMPL can be based on the reference current but not on the charging current. For example, the switching signal(s) SS can include signals that operate switches to control the charging current being provided to the sampling capacitor. Therefore, the amplitude of the current sampling voltage VSMPL can decrease during the second switching phase of the switching voltage regulator 102, and can therefore be proportional to the target regulation amplitude of the input current

[0027] For example, the current regulator system 106 includes a sampling comparator that is configured to identify approximately zero volts across the sampling capacitor, and thus an approximate zero voltage amplitude of the current sampling voltage VSMPL· AS described herein, the term “approximately” can include some deviation from an exact value (e.g., +/- 5%). Therefore, the sampling comparator can identify an approximately equal amplitude of the current sampling voltage VSMPL across the sampling capacitor at the beginning and end of a given switching period of the switching voltage regulator 102. In the example of FIG. 1, the output of the sampling comparator is shown as a comparison signal CMPi.

[0028] The power supply system 100 further includes a switch controller 110. The switch controller 110 is configured to provide the switching signal(s) SS responsive to the comparison signal CMPi. For example, the sampling comparator monitors the amplitude of the current sampling voltage VSMPL to switch from the second switching phase of the switching voltage regulator 102 to the first switching phase of the switching voltage regulator 102, and thus to a next switching period of the switching voltage regulator 102. The next switching period can also be initiated based on an amplitude of the output voltage VOUT relative to a reference voltage VREF· AS an example, the reference voltage VREF can be set at an external pin of the associated IC on which the power supply system 100 is fabricated (e.g., as a fixed voltage source). Therefore, the switch controller 110 can control the switching time of the switching voltage regulator 102 based on the amplitude of the current sampling voltage VSMPL· For example, the switch controller 110 also includes a state machine that is configured to generate the switching signal(s) SS, such as based on the amplitude of the current sampling voltage VSMPL and the amplitude of the output voltage VOUT relative to the reference voltage VREF·

[0029] As a result of the switch controller 110 controlling the switching period of the switching voltage regulator 102 based on the current sampling voltage VSMPL, the power supply system 100 can regulate the amplitude of the input current h _N to mitigate the power consumption from the associated battery, thereby extending the operational life of the battery. For example, by implementing the reference current generator 108 to pull the reference current from the sampling capacitor and providing the switching period transition on the time between a beginning amplitude of the current sampling voltage VSMPL in the first switching phase is approximately equal to a final amplitude of the current sampling voltage VSMPL in the second switching phase, the power supply system 100 can reduce the average amplitude of the input current h _N through the switching period of the switching voltage regulator 102. Accordingly, the power supply system 100 can extend the operational life of the battery that provides the input voltage Vi _N. Additionally, as described in greater detail herein, the power supply system 100 can operate in any of a variety of waveforms of the current through the inductor of the switching voltage regulator 102.

[0030] FIG. 2 is an example of a schematic electrical circuit diagram of a power supply circuit 200. The power supply circuit 200 can be implemented in any of a variety of wireless electronic devices, such as laptop computers, tablet computers, smart phones, or any of a variety of other electronic devices. The power supply circuit 200 is configured to generate an output voltage VOUT from an input voltage VIN- The power supply circuit 200 can be the power supply system 100 in the example of FIG. 1. Therefore, reference is to be made to the example of FIG. 1 in the following description of the example of FIG. 2.

[0031] The power supply circuit 200 includes a switching voltage regulator 202. The switching voltage regulator 202 includes a high-side switch, shown as a PFET Pi, a low-side switch, shown as an NFET Ni, a first output switch, shown as an NFET N ₂ , and a second output switch, shown as an NFET N _3. The PFET Pi interconnects the input voltage V _IN at a source and a switching node 204 at a drain, and the NFET Ni interconnects the switching node 204 at a drain and a low-voltage rail, shown in the example of FIG. 2 as ground, at a source. The NFET N ₂ interconnects the output voltage VOUT at a drain and a switching node 206 at a source, and the NFET N ₃ interconnects the switching node 206 at a drain and the low-voltage rail at a source. An inductor Li interconnects the switching nodes 204 and 206 and is configured to conduct a current I _L.

[0032] The PFET Pi is controlled by a switching signal INi, the NFET Ni is controlled by a switching signal IN ₂ , the NFET N ₂ is controlled by a switching signal OUTi, and the NFET N ₃ is controlled by a switching signal OUT _2. The activation of the FETs Pi, Ni, N ₂ , and N ₃ in a sequence provides the current I _L through the inductor Li in switching phases defined by the switching signals INi, IN ₂ , OUTi, and OUT ₂ , respectively. For example, the activation of the PFET Pi and NFET N3 provides the input current I _IN to flow from the input voltage V _IN to the switching node 204 during the first switching phase based on the switching signal INi and OUT2, such that the current I _L is approximately equal to the input current I _IN during the first switching phase of the switching voltage regulator 202. During the second switching phase of the switching voltage regulator 202, the PFET Pi and NFET N3 are deactivated and the NFET Ni and NFET N2 are activated by the switching signal IN ₂ and OUT 1 to conduct the current I _L from the low-voltage rail through the inductor Li.

[0033] FIG. 3 is an example of timing diagrams. The timing diagrams include a first timing diagram 302 that shows inductor current I _L plotted as a function of time for a converter operating in buck mode, and a second timing diagram 304 that shows inductor current I _L plotted as a function of time for a converter operating in boost mode. The inductor current I _L can be the current through the inductor Li of the switching voltage regulator 202 in the example of FIG. 2. Therefore, reference is to be made to the example of FIG. 2 in the following description of the example of FIG. 3. For simplicity sake, the transition times of the timing diagrams 302 and 304 are aligned. However, the transition times can differ between the buck and boost modes.

[0034] In the first timing diagram 302, the switching voltage regulator 202 begins a first switching phase at a time T _0. At the time T ₀ , the PFET Pi and the NFET N ₃ are activated by the switching signals INi and OUT ₂ , respectively. Therefore, the input current I _IN flows from the input voltage VIN, through the PFET Pi, and through the inductor Li as the current I _L , and through the NFET N3. Thus, in the example of FIG. 3, the current I _L is demonstrated as increasing from an amplitude of I _L o, which is an amplitude greater than or equal to zero, to an amplitude ILI at a time Ti. At the time Ti, the NFET N3 is deactivated by the switching signal OUT ₂ and the NFET N ₂ is activated by the switching signal OUTi. Therefore, the input current IIN flows from the input voltage VIN, through the PFET Pi, and through the inductor Li as the current I _L , and through the NFET N ₂ , such as to charge an output capacitor (not shown in the example of FIG. 2). Thus, in the example of FIG. 3, the current I _L is demonstrated as increasing from the amplitude I _LI to an amplitude I _I 2 at a time T ₂ , and thus at a lesser slope than between the times T ₀ and Ti.

[0035] The switching voltage regulator 202 switches from the first switching phase to the second switching phase at the time T ₂ . At the time T2, the PFET Pi is deactivated and the NFET Ni is activated by the switching signals INi and IN ₂ , respectively, and the NFET N ₂ remains activated. Therefore, the input current h _N ceases, and the current I _L flows from the low-voltage rail, through the NFET Ni, through the inductor Li, and through the NFET N2. Thus, in the example of FIG. 3, the current I _L is demonstrated as decreasing from the amplitude E2 to an amplitude I _L 3 at a time T ₃ , with the amplitude I _L3 being less than the amplitude I _Li . At the time T ₃ , the NFET N2 is deactivated by the switching signal OUTi and the NFET N ₃ is activated by the switching signal OUT ₂ . Therefore, the current I _L flows from the low-voltage rail, through the NFET Ni, through the inductor Li, and through the NFET N ₃ . Thus, in the example of FIG. 3, the current I _L is demonstrated as decreasing from the amplitude I _L3 to the initial amplitude I _L o at a time T . The second switching phase concludes at the time T . The first and second switching phases can define a switching period, such that a next switching period is shown in the example of FIG. 3 as beginning at the time T ₄ . For example, an idle time at which the current I _L remains at zero can occur between switching periods, such as during deactivation of the power supply circuit 200 or in a discontinuous mode of operation of the power supply circuit 200.

[0036] The second timing diagram 304 is arranged similar to the first timing diagram 302, and can define a boost mode of operation of the power supply circuit 200. As an example, the boost mode of operation is based on a variation in topology of the power supply circuit 200 to vary the amplitude of the current I _L . The second timing diagram 304 is therefore shown to demonstrate that the principle of operation of the power supply circuit 200, as described herein, is applicable to any of a variety of inductor current waveforms.

[0037] Referring back to the example of FIG. 2, the power supply circuit 200 includes a current regulator system 208 that is configured to regulate an amplitude of the input current Ii _N . As described above, the input current h _N can be drawn from a battery, such that monitoring and regulating the amplitude of the input current h _N can result in an extension of the operational life of the battery. In the example of FIG. 2, the current regulator system 208 includes a transconductance amplifier 210 that has a first input that is coupled to the switching node 204 through a first switch SWi controlled by a switching signal Si and to the input voltage V _IN through a second switch SW2 controlled by a switching signal S2. The transconductance amplifier 210 also has a second input that is coupled to the input voltage V _IN through a third switch SW ₃ controlled by a switching signal S ₃ and to a third switching node 212. The third switching node 212 is coupled to the input voltage V _IN through a PFET P _2. As an example, the PFET P ₂ is a replica switch with respect to the PFET Pi, such that the PFET P ₂ has a channel width that is scaled-down by a factor of K relative to the PFET Pi. In the example of FIG. 2, the PFET P ₂ is activated by the switching signal INi, such that the PFET P ₂ is activated concurrently with the PFET Pi to generate a charging current I _CH that has an amplitude approximately equal to the amplitude of the input current h _N divided by K (e.g., ICH = IIN / K).

[0038] The transconductance amplifier 210 is configured to generate a signal CT that is provided to a PFET P ₃ to provide the charging current I _CH to a sampling node 214 through a switch SW4 controlled by a switching signal S4. A sampling capacitor Cs interconnects the sampling node 214 and a node 220. The sampling node 214 and the node 220 are also coupled by a switch SW5 that is controlled by a switching signal S5. A voltage source 218 provides an offset voltage VOFF to the node 220. Additionally, a switch SW ₆ that is controlled by a switching signal S ₆ interconnects the sampling node 214 and a node 216, and a switch SW7 that is controlled by a switching signal S ₇ interconnects the nodes 216 and 220.

[0039] The current regulator system 208 also includes a current source 222 that is coupled to the sampling node 214 through a switch SWx that is controlled by a switching signal Sx. The current source 222 be the reference current generator 108 in the example of FIG. 1. For example, the current source 222 is provided at an external pin of the associated IC on which the power supply circuit 200 is fabricated (e.g., as a grounded resistor). Therefore, when the switch SWx is closed, the current source 222 is configured to conduct the reference current IREF from the sampling node 214, and thus from the sampling capacitor Cs. For example, the offset voltage VOFF (e.g., approximately 350 mV) provides sufficient headroom for the reference current IREF· As described above, the reference current I _REF can have an amplitude that is proportional to a maximum average amplitude setpoint of the input current h _N over a switching period of the switching voltage regulator 202. For example, the proportionality of the reference current IREF to the maximum average amplitude setpoint of the input current h _N is likewise scaled by the factor of K, and thus the proportionality constant as the charging current I _C H- AS an example, the reference current IREF has an amplitude that is expressed as follows:

IREF = ITAR / K Equation 1

Where: ITAR is the maximum average amplitude setpoint of the input current IIN over a switching period of the switching voltage regulator 202. [0040] The current regulator system 208 also includes a sampling comparator 224 that has inputs at the nodes 216 and 220. The sampling comparator 224 is therefore configured to monitor the sampling voltage V _SMPL on the sampling capacitor Cs when the switch SW ₆ is closed (e.g., based on common mode operation defined by the offset voltage V _OFF )· The sampling comparator 224 can generate a first comparison signal CMPi responsive to determining that the sampling voltage V _SMPL has an amplitude of approximately zero.

[0041] The power supply circuit 200 further includes a switch controller 226. The switch controller 226 includes a state machine 228. The first comparison signal CMPi is provided to the state machine 228 that also receives a second comparison signal CMP ₂ from a reference comparator 230. In the example of FIG. 2, the reference comparator 230 is configured to compare the output voltage V _OUT with a fixed reference voltage V _REF · Based on the comparison signals CMPi and CMP ₂ , the state machine 228 can generate the switching signals IN, OUT, and S that are provided to the respective PFETs Pi through P ₃ , the NFETs Ni through N ₃ , and the switches SWi through SW _8. Therefore, the state machine 228 can define the first and second switching phases of the switching voltage regulator 202, and therefore the switching period of the switching voltage regulator 202. The state machine 228 can also provide the controls for operating the switches SWi through SW ₈ to provide the operation of the current regulator system 208 in each of the first and second switching phases to regulate the amplitude of the input current

IlN·

[0042] The example power supply circuit 200 can be configured differently than shown in the example of FIG. 2. For example, the switching voltage regulator 202 is not limited to the arrangement of the high and low-side switches Pi, Ni, N ₂ , and N _3. As one example, the PFET Pi, and by extension the replica PFET P ₂ , is arranged as N-channel transistors instead.

[0043] Operation of the power supply circuit 200 is shown in greater detail in FIGS. 4-6. FIG. 4 is another example of timing diagrams. The timing diagrams include a first timing diagram 402 that shows inductor current I _L plotted as a function of time for a converter operating in buck mode. The first timing diagram 402 is therefore the same as the first timing diagram 302 in the example of FIG. 3. A second timing diagram 404 is the sampling voltage V _SMPL plotted as a function of time. FIG. 5 is an example of a schematic electrical circuit diagram 500 of current flow in in the power supply circuit 200 in the first switching phase of the switching voltage regulator 202, and FIG. 6 is an example of a schematic electrical circuit diagram 600 of current flow in in the power supply circuit 200 in the second switching phase of the switching voltage regulator 202. Accordingly, reference is to be made to the examples of FIGS. 4-6 in the following description.

[0044] In the first timing diagram 402, the switching voltage regulator 202 begins the first switching phase at a time To. At the time To, the PFET Pi and the NFET N ₃ are activated by the switching signals INi and OUT ₂ , respectively. Additionally, with reference to the example of FIG. 5, the switches SWi, SW ₄ , SW ₇ , and SWs are closed by the switching signals Si, S ₄ , S ₇ , and Ss, respectively. Therefore, the input current I _IN flows from the input voltage VIN, through the PFET Pi, and through the inductor Li as the current I _L , and through the NFET N3. Thus, in the example of FIG. 4, the current I _L is demonstrated as increasing from an amplitude of I _L o to an amplitude ILI.

[0045] At the time Ti, the NFET N3 is deactivated by the switching signal OUT ₂ and the NFET N ₂ is activated by the switching signal OUTi. Therefore, the input current I _IN flows from the input voltage V _IN , through the PFET Pi, and through the inductor Li as the current I _L , and through the NFET N _2. Thus, the current I _L continues to increase in amplitude from the time Ti to the time T ₂ during the first switching phase of the switching voltage regulator 202. Additionally, with further reference to the example of FIG. 5, during the first switching phase defined between the times T ₀ and T ₂ , the input current I _|N is emulated by the charging current I _C H through the replica PFET P ₂ , based on the matched PFETs Pi and P ₂ concurrently activated by the switching signal INi, with the charging current I _CH having a scaled amplitude approximately equal to the amplitude of the input current h _N divided by the channel-width scale factor K (e.g., ICH = IIN / K).

[0046] Because of the closure of the switch SWi, the transconductance amplifier 210 receives an approximately equal voltage at each of the inputs at the switching node 204 and the node 212 due to the high gain of transconductance amplifier 210. The transconductance amplifier 210 can be configured as a high bandwidth transconductance amplifier 210 to track the slope of the current I _L (e.g., the input current I _|N during the first switching phase of the switching voltage regulator 202), and can be configured with low offset to measure the current I _L as absolute, as opposed to relative. Low offset can be implemented, for example, by providing trimming, calibrating, or chopping of the transconductance amplifier 210, or providing auto-zero techniques using switches SW ₂ and SW ₃ , as described in greater detail herein. [0047] The transconductance amplifier 210 provides a control signal CT to the PFET P ₃ to conduct the charging current I _C H through the PFET P ₃ and through the switch SW to the sampling node 214. While the charging current I _CH is provided to the sampling node 214, based on the closure of the switch SWx, the reference current IREF flows from the sampling node 214. As a result, a sampling current ISMPL is provided through the sampling capacitor Cs. The current ISMPL therefore has an amplitude that is equal to the charging current I _C H minus the reference current IREF· Thus, the sampling current ISMPL begins charging the sampling capacitor Cs to increase the amplitude of the sampling voltage VSMPL· Because the switch SW ₆ is open and the switch SW ₇ is closed during the first switching phase of the switching voltage regulator 202, the sampling comparator 224 is not monitoring the sampling voltage VSMPL· Therefore, the first comparison signal CMPi is asserted at a logic-high state.

[0048] Referring back to the example of FIG. 4, the switching voltage regulator 202 switches from the first switching phase to the second switching phase at the time T _2. At the time T ₂ , the PFET Pi is deactivated and the NFET Ni is activated by the switching signals INi and IN ₂ , respectively, and the NFET N ₂ remains activated. Additionally, with reference to the example of FIG. 6, the switches SWi, SW ₄ , and SW ₇ are opened by the switching signals Si, S ₄ , and S ₇ , respectively, and the switches SW ₂ , SW ₃ , and SW ₆ are closed by the switching signals S ₂ , S ₃ , and S ₆ , respectively. The switch SW ₈ remains closed during the second switching phase of the switching voltage regulator 202. Therefore, the input current h _N ceases, and the current I _L flows from the low-voltage rail, through the NFET Ni, through the inductor Li, and through the NFET N _2. Thus, in the example of FIG. 4, the current I _L is demonstrated as decreasing from the amplitude I _L2 to an amplitude I _L3 at a time T _3. At the time T ₃ , the NFET N ₂ is deactivated by the switching signal OUTi and the NFET N ₃ is activated by the switching signal OUT _2. Therefore, the current I _L flows from the low-voltage rail, through the NFET Ni, through the inductor Li, and through the NFET N _3. Thus, in the example of FIG. 4, the current I _L is demonstrated as decreasing from the amplitude IL ₃ to the initial amplitude ILO at a time T _.

[0049] With reference to the example of FIG. 6, in the second switching phase of the switching voltage regulator 202, the PFETs Pi and P ₂ are both deactivated, which ceases the flow of the input current h _N , and by extension, the charging current ICH· The switches SW ₂ and SW ₃ are closed to provide zeroing of the transconductance amplifier 210. Because the charging current ICH ceases to flow, the charging current I _C H is no longer provided to the sampling node 214. However, the switch SWx is still closed in the second switching phase of the switching voltage regulator 202, resulting in the reference current I _REF continuing to draw charge from the sampling capacitor Cs. As a result, the sampling voltage VSMPL decreases beginning at the time T ₂ during the second switching phase of the switching voltage regulator 202.

[0050] Due to the closure of the switch SW ₆ , the sampling comparator 224 compares the sampling voltage VSMPL at the sampling node 214 with the voltage at the node 220, and therefore monitors the voltage across the sampling capacitor Cs. Responsive to the sampling voltage VSMPL having an amplitude of approximately zero, and thus the sampling capacitor Cs has approximately zero charge, the sampling comparator 224 can de-assert the first comparison signal CMPi. As described herein, a zero amplitude of the sampling voltage VSMPL refers to an approximately zero amplitude across the sampling capacitor Cs, based on the sampling voltage VSMPL being referenced to the offset voltage VOFF at the node 220. The zero amplitude of the sampling voltage VSMPL can also refer to an approximately negative amplitude of the sampling voltage VSMPL based on the sampling capacitor Cs, such that the inverting input of the sampling comparator 224 has a greater voltage amplitude than the sampling voltage VSMPL at the non inverting input of the sampling comparator 224.

[0051] Responsive to the de-assertion of the first comparison signal CMPi, and responsive to a logic-low amplitude of the second comparison signal CMP ₂ as provided by the reference comparator 230 (e.g., responsive to the reference voltage VREF being greater than the output voltage VOUT), the state machine 228 can change the state of the switching signals IN, OUT, and S. Therefore, the state machine 228 can switch the switching voltage regulator 202 from the second switching phase to the first switching phase, and thus the beginning of a next switching period. Therefore, the state machine 228 can dictate the time duration of the switching periods of the switching voltage regulator 202 based on the amplitude of the input current h _N relative to the reference current IREF (e.g., based on the sampling voltage VSMPL) to regulate the amplitude of the input current Ii _N.

[0052] As an example, upon completion of a switching period, the state machine 228 implements an idle (e.g., sleep) mode for the power supply circuit 200, such as based on a deactivation mode for the power supply circuit 200 or for a discontinuous mode of operation for the switching voltage regulator 202. For example, during an idle mode, the switch SWx is opened by the switching signal S ₈ to disconnect the reference voltage IREF from the sampling capacitor Cs. Additionally, the switches SW ₂ and SW ₃ can remain closed to provide zeroing of the transconductance amplifier 210, the switch SW ₅ can be closed by the switching signal S ₅ to provide zeroing of the sampling capacitor Cs, and the switch SW ₆ can remain closed to latch the first comparison signal CMPi provided by the sampling comparator 224. The state machine 228 therefore can await a change in state of the second comparison signal CMP ₂ to begin a next switching period.

[0053] Because the power supply circuit 200 provides switching times based on the amplitude of the input current h _N relative to the reference current IREF (e.g., based on the sampling voltage VS _MPL ), the power supply circuit 200 can regulate the amplitude of the input current I _IN in a manner that is more effective than input current regulation in a typical power supply circuit. For example, as described above, the current regulation of the power supply circuit 200 is implemented for more complex waveforms of the inductor current I _L , as well as non-zero initial amplitudes of the inductor current I _L , as opposed to being limited to triangular inductor current waveforms with an initial zero amplitude, as is the case for a typical power supply circuit. Additionally, the power supply circuit 200 provides real-time measurement of the input current I _IN during each cycle of the switching voltage regulator 202, and thus an actual peak amplitude of the inductor current I _L , as opposed to regulating the input current based on a fixed peak current amplitude estimate as is provided in a typical power supply circuit. Furthermore, a typical power supply circuit requires multiple capacitors for comparing multiple charges (e.g., a charge transmitted from the input and a charge of a desired average input current) to perform input current regulation. The power supply circuit 200 includes only a single capacitor for current regulation (e.g., the sampling capacitor Cs), which can provide for a more compact circuit and remove the requirement for matching between two or more capacitors. Accordingly, the input current regulation provided by the power supply circuit 200 can be substantially more effective than input current regulation of a typical power supply circuit.

[0054] FIG. 7 is another example of a schematic electrical circuit diagram of a power supply circuit 700. The power supply circuit 700 can be implemented in any of a variety of wireless electronic devices, such as laptop computers, tablet computers, smart phones, or any of a variety of other electronic devices. The power supply circuit 700 is configured to generate an output voltage VOU _T from an input voltage V _IN - The power supply circuit 700 can be the power supply system 100 in the example of FIG. 1. Therefore, the description of the example of FIG. 7 also refers to FIG. 1. The power supply circuit 700 in the example of FIG. 7 is provided as another example of the current regulation technique that implements an open-loop topology for a transconductance amplifier (as described in greater detail herein), as opposed to the closed-loop topology for the transconductance amplifier 210 in the example of FIG. 2. Therefore, the power supply circuit 700 need not require stability compensation resulting in support of a high slope of the inductor current I _L based on a smaller inductance of the inductor Li.

[0055] The power supply circuit 700 includes a switching voltage regulator 702. The switching voltage regulator 702 includes a high-side switch, shown as a PFET Pi, a low-side switch, shown as an NFET Ni, a first output switch, shown as an NFET N2, and a second output switch, shown as an NFET N _3. The PFET Pi interconnects the input voltage Vi _N at a source and a switching node 704 at a drain, and the NFET Ni interconnects the switching node 704 at a drain and a low-voltage rail, shown in the example of FIG. 7 as ground, at a source. The NFET N ₂ interconnects the output voltage V _OUT at a drain and a switching node 706 at a source, and the NFET N ₃ interconnects the switching node 706 at a drain and the low-voltage rail at a source. An inductor Li interconnects the switching nodes 704 and 706 and is configured to conduct a current I _L.

[0056] The PFET Pi is controlled by a switching signal INi, the NFET Ni is controlled by a switching signal IN ₂ , the NFET N ₂ is controlled by a switching signal OUTi, and the NFET N ₃ is controlled by a switching signal OUT _2. The activation of the FETs Pi, Ni, N ₂ , and N ₃ in a sequence provides the current I _L through the inductor Li in switching phases defined by the switching signals INi, IN ₂ , OUTi, and OUT ₂ , respectively. For example, the activation of the PFET Pi provides the input current h _N to flow from the input voltage V _IN to the switching node 704 during the first switching phase based on the switching signal FN), such that the current I _L is approximately equal to the input current h _N during the first switching phase of the switching voltage regulator 702. During the second switching phase of the switching voltage regulator 702, the PFET Pi is deactivated and the NFET Ni is activated by the switching signal IN ₂ to conduct the current I _L from the low-voltage rail through the inductor Li. Therefore, the switching voltage regulator 702 operates substantially the same as the switching voltage regulator 202 in the example of FIG. 2.

[0057] The power supply circuit 700 also includes a current regulator system 708 that is configured to regulate an amplitude of the input current In the example of FIG. 7, the current regulator system 708 includes a first transconductance amplifier 710 that has a first input that is coupled to the switching node 704 through a first switch SWi controlled by a switching signal Si and to the input voltage V _IN through a second switch SW2 controlled by a switching signal S2. The first transconductance amplifier 710 also has a second input that is coupled to the input voltage V _IN . The current regulator system 708 also includes a second transconductance amplifier 712 that has a first input that is coupled to a node 714 and to the input voltage Vi _N through a switch SW ₃ controlled by a switching signal S ₃ . The first and second transconductance amplifiers 710 and 712 can be fabricated approximately identically, and can therefore have an approximately equal transconductance (GM) factor. The second transconductance amplifier 712 also has a second input that is coupled to the input voltage Vi _N. The node 714 is coupled to the input voltage V _IN through a PFET P _2. As an example, the PFET P ₂ is a replica switch with respect to the PFET Pi, such that the PFET P ₂ has a channel width that is scaled-down by a factor of K relative to the PFET Pi.

[0058] In the example of FIG. 7, the PFET P ₂ is activated by the switching signal INi, such that the PFET P ₂ is activated concurrently with the PFET Pi to conduct the reference current IREF that is generated from a current source 716 through a switch SW4 that is controlled by a switching signal S4. The current source 716 can be the reference current generator 108 in the example of FIG. 1. For example, the current source 716 is provided at an external pin of the associated IC on which the power supply circuit 700 is fabricated (e.g., as a grounded resistor). Therefore, when the switch SW4 is closed, the current source 716 is configured to conduct the reference current IREF from the input voltage VIN and through the PFET P _2. As described above, the reference current IREF has an amplitude that is proportional to a maximum average amplitude setpoint of the input current h _N of the switching voltage regulator 702. For example, the proportionality of the reference current IREF to the maximum average amplitude setpoint of the input current h _N (expressed as ITAR) is likewise scaled by the factor of K, as provided above in Equation 1.

[0059] The first transconductance amplifier 710 is configured to generate a charging current Ic _H that is provided to a sampling node 718 through a switch SW5 controlled by a switching signal S5. For example, the charging current I _CH has an amplitude that is expressed as follows:

Ic _H ⁼ GM * Ii _N * RDSON Equation 2

Where: GM is the transconductance of the first transconductance amplifier 710; RDSON is the activation resistance of the PFET Pi.

Additionally, the second transconductance amplifier 712 is configured to generate a current I _R that is provided through a switch SW6 that is controlled by a switching signal S6 and through a diode-connected NFET N4. As an example, in the example of FIG. 7, the current I _R has an amplitude that is expressed as follows:

I _R = GM * I _TAR * K * RDSON Equation 3

Where: GM is the transconductance of the second transconductance amplifier 712, which is approximately equal to the transconductance of the first transconductance amplifier 710;

K*RDSON is the activation resistance of the PFET P ₂ , which is approximately equal to K-times the activation resistance of the PFET Pi. [0060] The diode-connected NFET N4 has a gate and drain that are coupled to a sample and hold capacitor Ci and a gate of an NFET N5 through a switch SW7 that is controlled by a switching signal S _7. Therefore, the NFETs N and N ₅ are arranged as a current mirror, with the current I _R being provided to the capacitor Ci when the switch SW7 is closed to charge the capacitor Ci. The voltage Vi on the capacitor Ci thus provides an activation voltage for the NFET N5 to mirror the current I _R through the NFET N5. Therefore, the NFET N5 likewise conducts the current I _R.

[0061] Similar to the power supply circuit 200, the sampling node 718 is coupled to a sampling capacitor Cs and has a sampling voltage VSMPL· The sampling capacitor Cs interconnects the sampling node 718 and a node 720. The sampling node 718 and the node 720 are also coupled by a switch SWx that is controlled by a switching signal Sx. A voltage source 722 provides an offset voltage VOFF to the node 720. Additionally, a switch SW ₉ that is controlled by a switching signal S ₉ interconnects the sampling node 718 and a node 724, and a switch SW10 that is controlled by a switching signal S10 interconnects the nodes 720 and 724. In the example of FIG. 7, the NFET N5 is coupled to the sampling node 718 at a drain. Therefore, the NFET N5 is configured to conduct the current I _R from the sampling node 718, and thus from the sampling capacitor Cs. For example, the offset voltage VOFF (e.g., approximately 350 mV) provides sufficient headroom for the current I _R.

[0062] The current regulator system 708 includes a sampling comparator 726 that has inputs at the nodes 724 and 720. Therefore, the sampling comparator 726 is configured to monitor the sampling voltage VSMPL on the sampling capacitor Cs when the switch SW9 is closed (e.g., based on common mode operation defined by the offset voltage VOFF)· The sampling comparator 726 can generate a first comparison signal CMPi responsive to determining that the sampling voltage VSMPL has an amplitude of approximately zero.

[0063] The power supply circuit 700 further includes a switch controller 728 that includes a state machine 730. The first comparison signal CMPi is provided to the state machine 730 that also receives a second comparison signal CMP ₂ from a reference comparator 732. In the example of FIG. 7, the reference comparator 732 is configured to compare the output voltage VOUT with a fixed reference voltage VREF· Based on the comparison signals CMPi and CMP ₂ , the state machine 730 can generate the switching signals IN, OUT, and S that are provided to the respective PFETs Pi through P ₃ , the NFETs Ni through N3, and the switches SWi through SW10, respectively. Therefore, the state machine 730 can define the first and second switching phases of the switching voltage regulator 702, and therefore the switching period of the switching voltage regulator 702. The state machine 730 can also provide the controls for operating the switches SWi through SW10 to provide the operation of the current regulator system 708 in each of the first and second switching phases to regulate the amplitude of the input current Ii _N.

[0064] The power supply circuit 700 is not limited to the example shown in FIG. 7. For example, the switching voltage regulator 702 is not limited to the arrangement of the high and low-side switches Pi, Ni, N ₂ , and N _3. As one example, the PFET Pi, and by extension the replica PFET P ₂ , is arranged as N-channel transistors instead.

[0065] Operation of the power supply circuit 700 is shown in greater detail in FIGS. 4, 8, and 9. FIG. 8 is another example of a schematic electrical circuit diagram 800 of current flow in the power supply circuit 700 in the first switching phase of the switching voltage regulator 702, and FIG. 9 is another example of a schematic electrical circuit diagram 900 of current flow in the power supply circuit 700 in the second switching phase of the switching voltage regulator 702. Accordingly, the following description also refers to the examples of FIGS. 4, 8, and 9.

[0066] In the first timing diagram 402, the switching voltage regulator 702 begins the first switching phase at a time T _0. At the time T ₀ , the PFET Pi and the NFET N ₃ are activated by the switching signals INi and OUT ₂ , respectively. Additionally, with reference to the example of FIG. 8, the switches SWi, SW4, SW5, SW ₆ , SW7, and SW10 are closed by the switching signals Si, S , S ₅ , S ₆ , S7, and Si ₀ , respectively. Therefore, the input current I _|N flows from the input voltage V _IN , through the PFET Pi, and through the inductor Li as the current I _L , and through the NFET N _3. Thus, in the example of FIG. 4, the current I _L is demonstrated as increasing from an amplitude ILO to an amplitude ILI.

[0067] At the time Ti, the NFET N ₃ is deactivated by the switching signal OUT ₂ and the NFET N ₂ is activated by the switching signal OUTi. Therefore, the input current I _IN flows from the input voltage Vi _N , through the PFET P _|, and through the inductor L _| as the current I _L , and through the NFET N _2. Thus, the current I _L continues to increase in amplitude from the time Ti to the time T ₂ during the first switching phase of the switching voltage regulator 702. Additionally, with further reference to the example of FIG. 8, during the first switching phase defined between the times T ₀ and T ₂ , the input current I _IN flows through the PFET P _| and the reference current flows through the PFET P ₂ based on the matched PFETs Pi and P ₂ concurrently activated by the switching signal INi. The first transconductance amplifier 710 generates the charging current I _CH based on the input current I _IN and having an amplitude defined by Equation 2 above based on the closure of the switch SWi. Similarly, the second transconductance amplifier 712 generates the current I _R based on the reference current and having an amplitude defined by Equation 3 above based on the closure of the switch SW4.

[0068] Based on the closure of the switch SW5, the charging current I _CH is provided from the first transconductance amplifier 710 to the sampling node 718. Based on the closure of the switch SW ₆ , the current I _R is provided from the second transconductance amplifier 712 through the NFET N4. The current I _R charges the capacitor Ci to provide the voltage Vi at the gate of the NFET N5, and the current I _R is mirrored from the NFET N4 to the NFET N5. As a result, a sampling current ISMPL is provided through the sampling capacitor Cs. The current ISMPL therefore has an amplitude that is equal to the charging current I _C H minus the current I _R. Thus, the sampling current ISMPL begins charging the sampling capacitor Cs to increase the amplitude of the sampling voltage VSMPL· Because the switch SW9 is open and the switch SW10 is closed during the first switching phase of the switching voltage regulator 702, the sampling comparator 726 is not monitoring the sampling voltage VSMPL· Therefore, the first comparison signal CMPi is asserted at a logic-high state.

[0069] Referring back to the example of FIG. 4, the switching voltage regulator 702 switches from the first switching phase to the second switching phase at the time T _2. At the time T ₂ , the PFET Pi is deactivated and the NFET Ni is activated by the switching signals INi and IN ₂ , respectively, and the NFET N2 remains activated. Additionally, with reference to the example of FIG. 9, the switches SWi, SW , SW ₅ , SW ₆ , SW ₇ , and SWi ₀ are opened by the switching signals Si, S ₄ , S5, S6, S7, and S10, respectively, and the switches SW2, SW3, and SW9 are closed by the switching signals S2, S3, and S9, respectively. Therefore, the input current I _IN ceases, and the current I _L flows from the low-voltage rail, through the NFET Ni, through the inductor Li, and through the NFET N _2. Thus, in the example of FIG. 4, the current I _L is demonstrated as decreasing from the amplitude E2 to an amplitude I _L 3 at a time T _3. At the time T ₃ , the NFET N2 is deactivated by the switching signal OUTi and the NFET N3 is activated by the switching signal OUT _2. Therefore, the current I _L flows from the low-voltage rail, through the NFET Ni, through the inductor Li, and through the NFET N _3. Thus, in the example of FIG. 4, the current II is demonstrated as decreasing from the amplitude IL3 to the initial ILO at a time T _4.

[0070] With reference to the example of FIG. 9, in the second switching phase of the switching voltage regulator 702, the PFETs Pi and P2 are both deactivated, which ceases the flow of the input current h _N , and by extension, the reference current IRE _F . The switches SW ₂ and SW ₃ are closed to provide zeroing of the first and second transconductance amplifiers 710 and 712. Because the charging current I _CH ceases to flow from the first transconductance amplifier 710, the charging current I _CH is no longer provided to the sampling node 718. Similarly, the current IR ceases to flow from the second transconductance amplifier 712. However, the sampled voltage Vi across the capacitor Ci continues to provide activation of the NFET N ₅ in the second switching phase of the switching voltage regulator 702, resulting in the current I _R continuing to draw charge from the sampling capacitor Cs. As a result, the sampling voltage VSMPL decreases beginning at the time T ₂ during the second switching phase of the switching voltage regulator 702.

[0071] Due to the closure of the switch SW9, the sampling comparator 726 compares the sampling voltage VSMPL at the sampling node 718 with the voltage at the node 720, and therefore monitors the voltage across the sampling capacitor Cs. Responsive to the sampling voltage VSMPL having an amplitude of approximately zero, and thus the sampling capacitor Cs has approximately zero charge, the sampling comparator 726 can de-assert the first comparison signal CMPi. Responsive to the de-assertion of the first comparison signal CMPi, and responsive to a logic-low amplitude of the second comparison signal CMP ₂ as provided by the reference comparator 732 (e.g., responsive to the reference voltage VREF being greater than the output voltage VOUT), the state machine 730 can change the state of the switching signals IN, OUT, and S. Therefore, the state machine 730 can switch the switching voltage regulator 702 from the second switching phase to the first switching phase, and thus the beginning of a next switching period. Therefore, the state machine 730 can dictate the time duration of the switching periods of the switching voltage regulator 702 based on the amplitude of the input current Ii _N relative to the reference current I _REF (e.g., based on the sampling voltage VSMPL) to regulate the amplitude of the input current Ii _N.

[0072] Similar to as described above, upon completion of a switching period, the state machine 730 can implement an idle (e.g., sleep) mode for the power supply circuit 700, such as based on a deactivation mode for the power supply circuit 700 or for a discontinuous mode of operation for the switching voltage regulator 702. For example, during an idle mode, the switches SW2 and SW3 remains closed to provide zeroing of the transconductance amplifiers 710 and 712, the switch SWx is closed by the switching signal Sx to provide zeroing of the sampling capacitor Cs, and the switch SW ₉ remains closed to provide zeroing of the sampling comparator 726. The state machine 730 therefore can await a change in state of the second comparison signal CMP ₂ to begin a next switching period.

[0073] FIG. 10 is another example of a schematic electrical circuit diagram showing current flow in a power supply circuit 1000. The power supply circuit 1000 can be implemented in any of a variety of wireless electronic devices, such as laptop computers, tablet computers, smart phones, or any of a variety of other electronic devices. The power supply circuit 1000 is configured to generate an output voltage VOUT from an input voltage VIN- The power supply circuit 1000 can be the power supply system 100 in the example of FIG. 1. Therefore, the description of FIG. 10 also refers to FIG. 1. The power supply circuit 1000 in the example of FIG. 10 provides another example of the current regulation technique that implements estimated values for the peak and valley amplitudes of the inductor current I _L. For example, the estimates for the peak and valley amplitudes of the inductor current I _L is calculated in any of a variety of ways, such as the operating modes of the power supply circuit 1000, the relative amplitudes of the input voltage VIN and the output voltage VOUT, duty-cycles, factory testing/calibration, or any of a variety of methods.

[0074] The power supply circuit 1000 includes a switching voltage regulator 1002. The switching voltage regulator 1002 includes a high-side switch, shown as a PFET Pi, a low-side switch, shown as an NFET Ni, a first output switch, shown as an NFET N2, and a second output switch, shown as an NFET N ₃ . The PFET Pi interconnects the input voltage Vi _N at a source and a switching node 1004 at a drain, and the NFET Ni interconnects the switching node 1004 at a drain and a low-voltage rail, shown in the example of FIG. 10 as ground, at a source. The NFET N ₂ interconnects the output voltage VOU _T at a drain and a switching node 1006 at a source, and the NFET N ₃ interconnects the switching node 1006 at a drain and the low-voltage rail at a source. An inductor Li interconnects the switching nodes 1004 and 1006 and is configured to conduct a current I _L .

[0075] The PFET Pi is controlled by a switching signal INi, the NFET Ni is controlled by a switching signal IN ₂ , the NFET N ₂ is controlled by a switching signal OUTi, and the NFET N ₃ is controlled by a switching signal OUT ₂ . The activation of the FETs Pi, Ni, N ₂ , and N ₃ in a sequence provides the current I _L through the inductor Li in switching phases defined by the switching signals INi, IN ₂ , OUTi, and OUT ₂ , respectively. For example, the activation of the PFET Pi provides the input current h _N to flow from the input voltage Vi _N to the switching node 1004 during the first switching phase based on the switching signal INi, such that the current I _L is approximately equal to the input current h _N during the first switching phase of the switching voltage regulator 1002. During the second switching phase of the switching voltage regulator 1002, the PFET Pi is deactivated and the NFET Ni is activated by the switching signal IN ₂ to conduct the current I _L from the low-voltage rail through the inductor Li. Therefore, the switching voltage regulator 1002 operates substantially the same as the switching voltage regulator 202 in the example of FIG. 2.

[0076] The power supply circuit 1000 also includes a current regulator system 1008 that is configured to regulate an amplitude of the input current ½. In the example of FIG. 10, the current regulator system 1008 includes a first current source 1010 that generates a first current E, a second current source 1012 that generates a second current I ₂ , and a third current source 1014 that generates a third current I ₃ . As an example, the currents f, I ₂ , and I ₃ , in combination, are the charging current I _C H during the first switching phase, as described in greater detail herein. The first current source 1010 interconnects the input voltage V _IN and a switch SWi that is controlled by a switching signal Si, the second current source 1012 interconnects the input voltage V _IN and a switch SW ₂ that is controlled by a switching signal S ₂ , and the third current source 1014 interconnects the input voltage Vi _N and a switch SW ₃ that is controlled by a first switching signal S ₃ . The parallel arrangements of the current source 1010 and the switch SWi, the current source 1012 and the switch SW ₂ , and the current source 1014 and the switch SW ₃ are arranged in series with a switch SW ₄ that is controlled by a switching signal S ₄ .

[0077] The switch SW4 is coupled to a sampling node 1016. A sampling capacitor Cs interconnects the sampling node 1016 and a node 1018. The sampling node 1016 and the node 1018 are also coupled by a switch SW ₅ that is controlled by a switching signal S ₅ . A voltage source 1020 provides an offset voltage VOFF to the node 1018. Additionally, a switch SW ₆ that is controlled by a switching signal S ₆ interconnects the sampling node 1016 and a node 1022, and a switch SW7 that is controlled by a switching signal S7 interconnects the nodes 1018 and 1022. [0078] The current regulator system 1008 also includes a current source 1024 that is coupled to the sampling node 1016 through a switch SWx that is controlled by a switching signal Sx. The current source 1024 can be the reference current generator 108 in the example of FIG. 1. For example, the current source 1024 is provided at an external pin of the associated IC on which the power supply circuit 1000 is fabricated (e.g., as a grounded resistor). Therefore, when the switch SWx is closed, the current source 1024 is configured to conduct the reference current IREF from the sampling node 1016, and thus from the sampling capacitor Cs. For example, the offset voltage VOFF (e.g., approximately 350 mV) provides sufficient headroom for the reference current IREF. AS described above, the reference current I _REF can have an amplitude that is proportional to a maximum average amplitude setpoint of the input current h _N of the switching voltage regulator 1002. For example, the proportionality of the reference current IREF to the maximum average amplitude setpoint of the input current Ii _N (expressed as ITAR) is likewise scaled by the factor of K, as provided above in Equation 1. In addition, the current regulator system 1008 includes a current source 1026 that is coupled to the sampling node 1016 through a switch SW9 that is controlled by a switching signal S9. The current source 1026 generates the current I ₃ , which is approximately equal to the current I ₃ generated by the current source 1014 described above.

[0079] The switching voltage regulator 1008 includes a sampling comparator 1028 that has inputs at the nodes 1018 and 1022. The sampling comparator 1028 is therefore configured to monitor the sampling voltage VSMPL on the sampling capacitor Cs when the switch SW ₆ is closed (e.g., based on common mode operation defined by the offset voltage VOFF)· The sampling comparator 1028 can generate a first comparison signal CMPi responsive to determining that the sampling voltage VSMPL has an amplitude of approximately zero.

[0080] The power supply circuit 1000 further includes a switch controller 1030 that includes a state machine 1032. The first comparison signal CMPi is provided to the state machine 1032 that also receives a second comparison signal CMP ₂ from a reference comparator 1034. In the example of FIG. 10, the reference comparator 1034 is configured to compare the output voltage VOUT with a fixed reference voltage VREF· Based on the comparison signals CMPi and CMP ₂ , the state machine 1032 can generate the switching signals IN, OUT, and S that are provided to the respective PFET Pi, the NFETs Ni through N3, and the switches SWi through SW ₉ , respectively. Therefore, the state machine 1032 can define the first and second switching phases of the switching voltage regulator 1002, and therefore the switching period of the switching voltage regulator 1002. The state machine 1032 can also provide the controls for operating the switches SWi through SW ₉ to provide the operation of the current regulator system 1008 in each of the first and second switching phases to regulate the amplitude of the input current Ii _N.

[0081] The power supply circuit 1000 is not limited to the circuit shown FIG. 10. For example, the switching voltage regulator 1002 is not limited to the arrangement of the high and low-side switches Pi, Ni, N ₂ , and N3. As one example, the PFET Pi is arranged as an N-channel transistor instead.

[0082] Operation of the power supply circuit 1000 is shown in greater detail in FIGS. 4 and 11-13. FIG. 11 is another example of a schematic electrical circuit diagram 1100 of current flow in the power supply circuit 1000 in the first switching phase of the switching voltage regulator 1002, FIG. 12 is another example of a schematic electrical circuit diagram 1200 of current flow in the power supply circuit 1000 in the first switching phase of the switching voltage regulator 1002, and FIG. 13 is another example of a schematic electrical circuit diagram 1300 of current flow in the power supply circuit 1000 in the second switching phase of the switching voltage regulator 1002. Accordingly, the description of FIG. 11 also refers to the examples of FIGS. 4 and 11-13.

[0083] In the first timing diagram 402, the switching voltage regulator 1002 begins the first switching phase at a time T _0. At the time T ₀ , the PFET Pi and the NFET N3 are activated by the switching signals INi and OUT ₂ , respectively. Therefore, the input current F _N flows from the input voltage VIN, through the PFET Pi, and through the inductor Li as the current I _L , and through the NFET N _3. Thus, in the example of FIG. 4, the current I _L is demonstrated as increasing from an amplitude of ILO to an amplitude ILI.

[0084] Additionally, with reference to the example of FIG. 11, the switches SWf, SW , SW ₇ , and SW ₈ are closed by the switching signals Si, S ₄ , S ₇ , and S ₈ , respectively, from the time To to the time Ti. Therefore, from the time T ₀ and Ti, the current Ii flows from the current source 1010, through the closed switches SWi and SW ₄ , and to the sampling node 1016. While the current I ₄ is provided to the sampling node 1016, based on the closure of the switch SW ₈ , the reference current IREF flows from the sampling node 1016. As a result, a sampling current ISMPL is provided through the sampling capacitor Cs. The current ISMPL therefore has an amplitude that is equal to the current Ii minus the reference current IREF· Thus, the sampling current ISMPL begins charging the sampling capacitor Cs to increase the amplitude of the sampling voltage V _SMPL from the time T ₀ to the time T _| Because the switch SW ₆ is open and the switch SW ₇ is closed during the first switching phase of the switching voltage regulator 1002, the sampling comparator 1028 is not monitoring the sampling voltage VSMPL· Therefore, the first comparison signal CMPi is asserted at a logic-high state.

[0085] Referring to the example of FIG. 4, at the time T ₄ , the NFET N ₃ is deactivated by the switching signal OUT ₂ and the NFET N ₂ is activated by the switching signal OUTi. Therefore, the input current h _N flows from the input voltage VIN, through the PFET Pi, and through the inductor L ₄ as the current I _L , and through the NFET N _2. Thus, the current I _L continues to increase in amplitude from the time T ₄ to the time T ₂ during the first switching phase of the switching voltage regulator 1002. Additionally, with reference to the example of FIG. 12, the switch SWi is opened by the switching signal Si, the switches SW ₄ , SW ₇ , and SW ₈ remain closed, the switch SW ₂ is closed by the switching signal S ₂ , and one of the switches SW ₃ and SW ₉ is closed by the respective one of the switching signals S ₃ and S ₉ , depending on the operational mode of the switching voltage regulator 1002.

[0086] For example, for the buck mode operation of the timing diagram 402 (and the timing diagram 302 in the example of FIG. 3), the switch SW ₃ is closed. However, for the boost mode operation shown in the timing diagram 304 in the example of FIG. 3, the switch SW ₉ is closed instead. Therefore, the amplitude of the current I ₃ is added to the amplitude of the current I ₂ at the sampling node 1016 for a buck mode of operation, or the amplitude of the current I ₃ is subtracted from the amplitude of the current I ₂ in the boost mode of operation. While the example of FIG. 12 shows both switches SW ₃ and SW ₉ as being concurrently closed, only one of the switches SW3 and SW9 is closed at a given time, depending on the operational mode of the switching voltage regulator 1002. Therefore, the current Ii can be the charging current I _C H that is provided to the sampling node 1016 from the time To to the time Ti, and the combination of the currents I2 and I3 (additive or subtractive) can be the charging current I _CH that is provided to the sampling node 1016 from the time Ti to the time T2.

[0087] Based on the closure of the switch SW , the charging current I _C H is provided to the sampling node 1016 during the first switching phase of the switching voltage regulator 1002. While the charging current I _CH is provided to the sampling node 1016, based on the closure of the switch SWx, the reference current IREF flows from the sampling node 1016. As a result, a sampling current ISMPL is provided through the sampling capacitor Cs. The current ISMPL therefore has an amplitude that is equal to the charging current I _CH minus the reference current IREF· Thus, the sampling current ISMPL begins charging the sampling capacitor Cs to increase the amplitude of the sampling voltage VSMPL· Because the switch SW ₆ is open and the switch SW7 is closed during the first switching phase of the switching voltage regulator 1002, the sampling comparator 1028 is not monitoring the sampling voltage VSMPL· Therefore, the first comparison signal CMPi is asserted at a logic-high state.

[0088] Referring back to the example of FIG. 4, the switching voltage regulator 1002 switches from the first switching phase to the second switching phase at the time T _2. At the time T ₂ , the PFET Pi is deactivated and the NFET Ni is activated by the switching signals IN) and IN ₂ , respectively, and the NFET N2 remains activated. Additionally, with reference to the example of FIG. 13, the switches SW2, SW3, SW9, SW ₄ , and SW7 are opened by the switching signals Si, S3, S9, S ₄ , and S7, respectively, and the switch SW ₆ is closed by the switching signal S _6. The switch SW ₈ remains closed during the second switching phase of the switching voltage regulator 1002. Therefore, the current h _N ceases, and the current I _L flows from the low-voltage rail, through the NFET Ni, through the inductor Li, and through the NFET N2. Thus, in the example of FIG. 4, the current I _L is demonstrated as decreasing from the amplitude E2 to an amplitude E3 at a time T _3. At the time T ₃ , the NFET N ₂ is deactivated by the switching signal OUTi and the NFET N ₃ is activated by the switching signal OUT _2. Therefore, the current I _L flows from the low-voltage rail, through the NFET Ni, through the inductor Li, and through the NFET N3. Thus, in the example of FIG. 4, the current I _L is demonstrated as decreasing from the amplitude E3 to the initial amplitude I _L o at a time T _4. [0089] With reference to the example of FIG. 13, in the second switching phase of the switching voltage regulator 1002, the currents Ii, I ₂ , and I ₃ cease. Therefore, the charging current Ic _H ceases to flow to the sampling node 1016. However, the reference current I _REF continues to flow from the sampling node 1016, resulting in the current I _REF continuing to draw charge from the sampling capacitor Cs. As a result, the sampling voltage VSMPL decreases beginning at the time T ₂ during the second switching phase of the switching voltage regulator 1002.

[0090] Due to the closure of the switch SW ₆ , the sampling comparator 1028 compares the sampling voltage VS _MPL at the sampling node 1016 with the voltage at the node 1018, and therefore monitors the voltage across the sampling capacitor Cs. Responsive to the sampling voltage VS _MPL having an amplitude of approximately zero, and thus the sampling capacitor Cs has approximately zero charge, the sampling comparator 1028 can de-assert the first comparison signal CMPi. Responsive to the de-assertion of the first comparison signal CMPi, and responsive to a logic-low amplitude of the second comparison signal CMP ₂ as provided by the reference comparator 1034 (e.g., responsive to the reference voltage V _REF being greater than the output voltage VOU _T ), the state machine 1032 can change the state of the switching signals IN, OUT, and S. Therefore, the state machine 1032 can switch the switching voltage regulator 1002 from the second switching phase to the first switching phase, and thus the beginning of a next switching period. Therefore, the state machine 1032 can dictate the time duration of the switching periods of the switching voltage regulator 1002 based on the amplitude of the input current h _N relative to the reference current I _REF (e.g., based on the sampling voltage VS _MPL ) to regulate the amplitude of the input current Ii _N.

[0091] Similar to as described above, upon completion of a switching period, the state machine 1032 can implement an idle (e.g., sleep) mode for the power supply circuit 1000, such as based on a deactivation mode for the power supply circuit 1000 or for a discontinuous mode of operation for the switching voltage regulator 1002. For example, during an idle mode, the switch SWx is opened by the switching signal Sx to cease the flow of the reference current I _REF , and the switch SW ₅ is closed by the switching signal S ₅ to provide zeroing of the sampling capacitor Cs. The switch SW ₆ can remain closed to latch the first comparison signal CMPi provided by the sampling comparator 1028. The state machine 1032 therefore can await a change in state of the second comparison signal CMP ₂ to begin a next switching period.

[0092] Accordingly, the examples of FIGS. 7-13 describe other examples of a power supply circuit that can regulate the input current h _N based on the amplitude of the input current I _IN relative to the reference current I _REF (e.g., based on the sampling voltage VSMPL)· Therefore, similar to the power supply circuit 200, the power supply circuits 700 and 1000 can regulate the amplitude of the input current h _N in a manner that is more effective than input current regulation in a typical power supply circuit. For example, as described above, the current regulation of the power supply circuits 700 and 1000 is implemented for more complex waveforms of the inductor current I _L , as well as non-zero initial amplitudes of the inductor current I _L. Additionally, the power supply circuit 700 provides real-time measurement of the input current h _N during each cycle of the switching voltage regulator 702, and thus an amplitude of the inductor current I _L , in an open-loop manner that negates the need for bandwidth-limiting stability compensation. Alternatively, the power supply circuit 1000 provides measurement of an estimated amplitude of the input current h _N at each cycle of the switching voltage regulator 1002 to provide for a more simplistic circuit that can achieve superior regulation of the input current h _N relative to a typical power supply circuit. Accordingly, the input current regulation provided by the power supply circuits 700 and 1000 can be substantially more effective than input current regulation of a typical power supply circuit.

[0093] In this description, the term "couple" may cover connections, communications, or signal paths that enable a functional relationship consistent with this description. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first example, device A is directly coupled to device B; or (b) in a second example, device A is indirectly coupled to device B through intervening component C if intervening component C does not substantially alter the functional relationship between device A and device B, so device B is controlled by device A via the control signal generated by device A.

[0094] Also, in this description, a device that is “configured to” perform a task or function may be configured (e.g., programmed and/or hardwired) at a time of manufacturing by a manufacturer to perform the function and/or may be configurable (or reconfigurable) by a user after manufacturing to perform the function and/or other additional or alternative functions. The configuring may be through firmware and/or software programming of the device, through a construction and/or layout of hardware components and interconnections of the device, or a combination thereof. Furthermore, a circuit or device described herein as including certain components may instead be configured to couple to those components to form the described circuitry or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and/or inductors), and/or one or more sources (such as voltage and/or current sources) may instead include only the semiconductor elements within a single physical device (e.g., a semiconductor die and/or integrated circuit (IC) package) and may be configured to couple to at least some of the passive elements and/or the sources to form the described structure, either at a time of manufacture or after a time of manufacture, such as by an end user and/or a third party.

[0095] Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.