Title:
DATA SCHEDULING SYSTEM, RECONFIGURABLE PROCESSOR AND DATA SCHEDULING METHOD
Document Type and Number:
WIPO Patent Application WO/2022/262341
Kind Code:
A1
Abstract:
Disclosed in the present invention are a data scheduling system, a reconfigurable processor and a data scheduling method. The data scheduling system comprises a first FIFO, a first write pointer control module, a second FIFO, a second write pointer control module, a read pointer control module, an empty-state determination control module and a full-state determination control module. Every time data to be processed is transmitted from the first FIFO to a reconfigurable array, the first write pointer control module pre-allocates a first write cache address; every time the reconfigurable array writes a processing result into the second FIFO, the second write pointer control module allocates a second write cache address; every time the processing result cached in the second FIFO is read by a system bus, the read pointer control module allocates a read cache address; the empty-state determination control module determines an empty state of the second FIFO according to the second write cache address and the read cache address; and the full-state determination control module determines a full state of the second FIFO according to the first write cache address and the read cache address.
Inventors:
ZHAO WANG (CN)
XU DENGKE (CN)
CHANG ZIQI (CN)
XU DENGKE (CN)
CHANG ZIQI (CN)
Application Number:
PCT/CN2022/081524
Publication Date:
December 22, 2022
Filing Date:
March 17, 2022
Export Citation:
Assignee:
AMICRO SEMICONDUCTOR CO LTD (CN)
International Classes:
G06F15/78
Foreign References:
| US6920526B1 | 2005-07-19 | |||
| CN103677732A | 2014-03-26 | |||
| CN111367495A | 2020-07-03 | |||
| US20200012594A1 | 2020-01-09 |
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