Title:
DELAY DETECTION CIRCUIT OF DELAY-LOCKED LOOP, DELAY-LOCKED LOOP CIRCUIT, AND STORAGE APPARATUS
Document Type and Number:
WIPO Patent Application WO/2024/011768
Kind Code:
A1
Abstract:
The embodiments of the present disclosure relate to the field of semi-conductors, in particular to a delay detection circuit of a delay-locked loop, a delay-locked loop circuit, and a storage apparatus. The delay detection circuit of the delay-locked loop comprises: a phase detector, which is configured to receive a feedback clock signal and a reference clock signal and output a first signal and a second signal, the difference between an edge of the first signal and an edge of the second signal representing a phase difference between the feedback clock signal and the reference clock signal; and a conversion circuit, which is configured to receive the first signal and the second signal, delay the first signal at least once, compare the edge difference between the first signal and the second signal after each delay, and output a code value, the code value representing an actual delay amount of the first signal of the last delay compared with the first signal.
Inventors:
ZHANG YA'NAN (CN)
Application Number:
PCT/CN2022/124152
Publication Date:
January 18, 2024
Filing Date:
October 09, 2022
Export Citation:
Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
H03L7/081
Foreign References:
| US20080042704A1 | 2008-02-21 | |||
| US20050218937A1 | 2005-10-06 | |||
| CN104753524A | 2015-07-01 | |||
| CN112234956A | 2021-01-15 | |||
| US20080061851A1 | 2008-03-13 |
Attorney, Agent or Firm:
SHANGHAI CHENHAO INTELLECTUAL PROPERTY LAW FIRM GENERAL PARTNERSHIP (CN)
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