Title:
DELAY LINE
Document Type and Number:
WIPO Patent Application WO/2005/091499
Kind Code:
A1
Abstract:
[PROBLEMS] To attain equivalent characteristics even if a shield member between spiral inductors is removed in a delay line where first and second spiral inductors are facing each other. [MEANS FOR SOLVING PROBLEMS] A first spiral inductor (45) is formed on the upper surface of a first dielectric substrate (43). A second spiral inductor (51) is formed on the upper surface of a second dielectric substrate (49). The second dielectric substrate (49) is laid on the lower surface of the first dielectric substrate (43), and the first and second spiral inductors (45, 51) are via-connected in series through the first dielectric substrate (43) at the central part such that they are coupled positively. Capacitor electrodes each occupying an area of 20-60% of the outer circumferential region of the relevant pattern are formed at the central parts of the first and second spiral inductors. A third dielectric substrate (55) having a first ground layer (57) formed thereon is laid on the upper surface of the first dielectric substrate (43). A second ground layer (59) is laid on the lower surface of the second dielectric substrate (49).
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Inventors:
KAMEYA MASAAKI (JP)
Application Number:
PCT/JP2005/004431
Publication Date:
September 29, 2005
Filing Date:
March 14, 2005
Export Citation:
Assignee:
ELMEC CORP (JP)
KAMEYA MASAAKI (JP)
KAMEYA MASAAKI (JP)
International Classes:
H01F27/00; H03H7/34; H01F17/00; (IPC1-7): H03H7/34; H01F17/00; H01F27/00
Foreign References:
JPS62173816U | 1987-11-05 | |||
JPH10163783A | 1998-06-19 | |||
JPH05275960A | 1993-10-22 | |||
JPS5472443U | 1979-05-23 | |||
JPH1075146A | 1998-03-17 | |||
JPH10214722A | 1998-08-11 |
Attorney, Agent or Firm:
Saito, Yoshiharu (3F. 2-14 Minami-Ohtsuka 3-Chome, Toshima-K, Tokyo 05, JP)
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