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Patent Searching and Data


Title:
DIFFERENTIAL AMPLIFICATION CIRCUIT, RECEPTION CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2021/124450
Kind Code:
A1
Abstract:
According to the present invention, a differential amplification circuit unit comprises: first and second transistors (205, 206) that are located between a current source circuit and a load circuit and receive differential input signals at the gates to generate differential output signals at the drains; and a third transistor (433) that is connected between the sources of the first and second transistors and receives a control signal at the gate, while a replica amplification circuit unit comprises: a voltage generation circuit that generates first and second reference voltages; first and second replica transistors (416, 417) that are replicas of the first and second transistors and receive the first and second reference voltages at the gates to generate replica output signals at the drains; a third replica transistor (415) that is connected between the sources of the first and second replica transistors and receives the control signal at the gate; and an operational amplifier (422) that generates the control signal in accordance with the difference between at least one of the first and second reference voltages and the replica output signal.

Inventors:
FUJIMURA TAKUYA (JP)
KANO HIDEKI (JP)
Application Number:
PCT/JP2019/049423
Publication Date:
June 24, 2021
Filing Date:
December 17, 2019
Export Citation:
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Assignee:
SOCIONEXT INC (JP)
International Classes:
H03F3/45
Foreign References:
JP2017538363A2017-12-21
US20110001562A12011-01-06
JP2010034733A2010-02-12
US20090015328A12009-01-15
Attorney, Agent or Firm:
KOKUBUN, Takayoshi (JP)
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