TECHNICAL FIELD

[1] This disclosure relates generally to light field displays and: cameras, and more particularly to distributed multi-screen arr ys for high density displays .

BACKGROUND

[2] Electronic displays are utilized in a earner y of applications. For estampIe, displays are used in smartphones, laptop computers, and digital cameras . Spine oevicts , such as smartphones arid digital cameras, cay i aelude an image sensor in addition to an electronic display, hile some cameras and electronic displays separately capture and reproduce light fields, light field displays and light field cameras are generally not integrated with one another.

[3] In one embodiment, an electronic display assembly includes a circuit board and a plurality of display facets. Each display facet is coupled to one side of the circuit board. Each display facet includes a plurality of display panels. Each display facet includes a selectable display resolution from a plurality of display resolutions. Each display facet is individual Iy addressable such that the plurality of display facets are configurable to provide heterogeneous display resolutions. The circuit board includes a plurality of facet locations. Each particular facet location is configured to transmit signal® to a particular display facet that is electrically coupled to the particular facer J oc tios , thereby displaying light on the particular display facet at a particular selected display resolution.

[4j The present disclosure presents several technical advantages. Some embodrmer.es provide a complete and accurate recreation of a target light field chile remain lag lightweight and comfortable to near for a user. dope embodiments provd.de a thin electronic system which offers both opacity ana controllable unidirectional emulated trant;patency, as well as digital display capabilities such as virtual reality i VS) , augmented reality (An) , and mined reality (MR; . Some embodiments provide a direct sensor-to-display system that utilizes a direct association of input pixels to corollary output pixels to circumvent the need for image ran sierras 1 o:. , This reduces the complexity, ccut, and power requirements for some systems. Some embodiments provide in--layer signal processing configura ions that provide for local, distributed processing of large quantities of data (e.g., luOk of image data or morel . thereby circumventing bottlenecks as well asperformance, power, and transmission line issues associated with eaisting solutions. Some embodiments utilize micro.lens layers with arrays of plenoptic ceils to accurately capture arid display a volume of light to a viewe , The pi optic cells include opaque cell walla to eliminate optical crosstalk between ceils, thereby improving the accuracy of the replicated light field.

[5] Some embodiments provide three-dimensional electronics by geodesic faceting. lb such embodiments, a flexible circuit board with an array of email, rigid surfaces (e, g., display and/or sensor facets) may be formed into any 3D shape, which is especially useful to accommodate the narrow radii of curvature (e , g . , 3G-60 mm) necessary for head-mounted Ksai-¾ye trapped displays, Some e:r bodicere: a provide distributed uiti~screen arrays fox high density displays . In such embodi ents , an array of small, high-resolation micro displays (e,g,, display facets) of custom sires and shapes are formed and then assembled on a larger, flexible circuit board that may then be formed into a 3D shape ; e , g , . a semispherical surface) , Each micro display may act independently of any other display, thereby providing a large array of many high- resolution displays with unique content on each, such that the whole assembly together forms essentially single extremely high-resolution display. Some embodiments provide a distributed multi-aperture camera array . Such embodiments provide an array of small image sensors {e _> g, , sensor facets) of custom sites and shapes, all of which are assembled on a larger, flexible circuit board that is then formed to a 3D ie,g,, semi-spherical) shape. Each discrete image sensor may act independently of any other image sensor i order to provide a large ar ay of many apertures capturing: unique content on each, such that the whole assembly essentially becomes a seamless, very high resolution, multi-node camera,

[6] Other technical advantages mill be readily apparent to one skilled in the art from FIGURES !¾ through 42 _f their descriptions, and the claims. Moreover, while specific advantages have been enumerated above, various embodiments may include all, come, or none of the enumerated advantages. BRIEF DESCRIPTION OF THE

[7] For a mors complete understandin of the present disclosure and its advantages, reference is non made to toe following description, _· taken in con unction with the accompanying drawings, in which:

[81 FIGURES IA-10 illustrate a reference scene with carious three-dimensional (3D) objects and various viewing positional according: to certain embodiments;

[9j FIGURES 2A-2C illustrate viewing the 3D objects of FIGURES 1A-1C through a transparent panel , according to certain embosi me ots ;

[10] FIGURES 3A-3C Illustrate viewing the 3D objects of FIGURES IA-IC through a camera image panel, according to certain endodiments ?

[11: FIGURES iA-iC illustrate viewing the 3D objects of

FIGURES IA-IC through an emulated-t ransparency electronic: panel, according to certain embodiments:

:[ 123 FIGURES 5A-5C illustrate viewing the 3D objects of

FIGURES la-lC through the camera image panel of FIGURES 3A~3C from an alternate angle, according to certain embodiments ;

[13] FIGURES 6A--6C illustrate viewing the 3D objects of

FIGURES 1A-1C through the emuiated-transparency electronic panel of FIGURES 3A-4C from an alternate angle, according to certain embodiments;

[14] FIGURE 7 illustrates a cut-away view of an emulated transparency assembly, according to certain embo i ents /

[1:5 } FIGURE 8 illustrates an exploded view of the emulated transpa rency assembly of FIGURE 7 according to ce rtain embed im nts ; [161 FIGURE 9 illustrates a method of nranuf&cturiny the emulated transparency assembly of FIGURE 7 ,, according to certain embodiments

[171 FIGURE 10 illustrates a direct sensor-to-display

Sysfcexn that may ho used by the emulated: transparency assembly or FIGURE 7 _f according to certain embodiments;

[18] FIGURE 11 illustrates a method of manufacturing the direct sensor-to-display system ex FIGURE 10, according to cartain embed menfcs ;

[1.91 F1GUPES 12-13 illustrate carious in-layer signal processing configurations that may he used by the emulated transparency assembly of FIGURE 7, according to certain embodiment s ;

[20] FIGURE If illustrates a method of manufacturing the In-layer signal processing systems of FIGURES 12-13, according to certain embodiments ;

[21] FIGURE 15 illustrates a plenoptic cell assembly that may be used by the emulated transparency assembly of FIGURE 7y according to certain embodiments;

F22] FIGURE 16 illustrates a cross section Of a portion of the plenoptic ceil assembly of FIGURE 15, according to certain embodiments ;

F23] FIGURES 17.R-17C illustrate cross sections of a portion of the plenoptic ceil assembly of FIGURE 1.5 with various incoming fields of light, according bo certain embodiments ;

[24] FIGURES IR.a-lHB illustrate a method of manufacturing the plenoptic cell assembly of FIGURE 15, according to certain embodiments; [25] FIGURES 19A--1SB illustrate another method of manufacturing the plenoptic cell aorerally of FIGURE 15, according to certain embodiments;

[26] FIGURES 20--21 ill -.nitrate a plenoptic ceil assembly that say be xsannfactured by the methods of BIGDRES IfA-lib, according to cert in embodiments ;

[27] FIGURE 22 11lust rabes a flexible circait board that may be used by the emulated transparency assemo ^' .y of FIGURE 7, according to certain embodiments ;

:[28j FIGURE 23 illustrates additional details of the flexible circuit board of FIGURE 22, according to certain embodiments ;

[291 FIGURE 24 illnstraf.es a data flow through the flexible circuit board of FIGURE 22, according to certain exabodiments ;

[30] FIGURE 25 illustrates a method of k-anu factoring an electronic -assembly using the flexible circuit board of FIGURE 22, according to certain embed1 reefs;

[31] FIGURE 26 illustrates a cut-away view of a curved maltx-display array, accordlxig to certain embodiments;

[32] FIGURE 27 illustrates an exploded risw of the carved mult i --display array of FIGURE 21 , according to certain embodiments ;

[33] FIGURES 28-29 illustrate logic facets and display facets of the curved multi-display array of FIGURE 26, according to certain exsbodiments ;

[34] FIGURE 30 illustrates a back side of the flexible circuit beard of FIGURE 22, according to certain embodiments ;

[35] FIGURE 31 illustrates a data flow through theflexible circuit board of FIGURE 30, according to certain ended· o::rc:a; [36] FIGURE 32 illustrates the flexible circuit board of FISURE 3D that has been formed into a se ispherical shape:, according to certain erbodr.mon:; s ;

[37] FIGURE 33 illustrates a data flow through the flexible circuit board of FIGURE 32, according to certain enbodimexxts ;

[38] FIGURE 34 illustrates an array of 1 ogre facets that have been formed into a Hemispherical shape, according to cartain e bodirnents;

[33] FIGURE 35 illustrates roamurn car ions between the logic facets of FIGURE 31, according to certain ernbodixaents

[10] FIGURE 36 illustrates a method of maxu;facharing the curved multi-display air ray of FIGURE 26, according to certain embodiments; ^'

[411 FIGURE 37 iilustxiates a cut-away view of a curved multi camer array, according to certain embodiments;

[421 FIGURES 38-33 illustrate exploded views of the curved multi -camera array of FIGURE 37, according to certaix; embodiments ;

[43] FIGURE 48 illustrates a back slew of the flexible circuit board of FIGURE 32, according to certain embodiments ;

[44] FIGURE 41 illustrates data flow through the flexible ci cuit board of FIGURE 40, according to certain embedimenfcs ; and

] 45 ] FIGURE 42 ill strates a method of manufacturing the carved xnuiti---camera array of FIGURE 37, according to certain embodiments . DETAILED DESCRIPTION OF £X¾MFLS EMBODIMENTS

G 461 Electronic dieploys are utilized it a variety of applications , For example, displays are isad ia smartphones, laptop computers, and digital cameras, Soxae devices, such as smartphones and digital cameras, may include an image sensor in addition to at electronic display. Devices with displays and image sensors, however, are generally limited in their ability to accurately capture and display the full photonic environment .

r 471 To address problems and limitations associated with existing electronic displays, embodiments of the disclosure provide various electronic asaexablies tor capturing and displaying light fields, FIGURES IA-9 are directed to display assemblies with elec ;;onJ rally emulated transparency, FIGURES 10-11 are directed to direct earnera-to-display systems, FIGURES 12-14 are directed to in-layer signal processixxg, FIGURES 15-21 are directed to plenoptic cellular imaging syshexts, FIGURES 22-25 are directed to three- dimensional (3D) electronics distribution by geodesic faceting, FIGURES 26-36 are directed to distributed multi screen arrays for high density displays, and FIGURES 37-42 are directed to distributed multi-aperture camera arrays.

:[ 481 To facilitate a better runletsbanding of the present disclosure, the following tramples of certain embodir-ents are given. The following examples are act to be read to limit or define the scope of the disclosure.

Embodiments of the present disclosure and its advantages are best understood by referring to FIGURES 1A-42, where like numbers are used to indicate like and corresponding parts.

[43] FIGURES la-9 illustrate various aspects of an assembly with electronically emulate transparency , according to certain embodiments In general, the electronic assembly illustrated in detail in FIGURES 7-0 may be used in different applications to provide features such as virtual reality (VR) ,. augmented reality (SR) , and mixed reality (MR), For VR applications- a digital display is required which can completely replace a view or the real world; similar to how a standard computer monitor blocks the view of the scene behind it. Hcwevcr _f for AR applications, a digital display is; required which can overlay data on top of that view of the real world _; such as a pilot's heads-up display in a modern cockpit . MR applications require a combination of both.

Typical systems used to provide some or all of these features are not desirable for a number of reasons. For example typical solutions do not provide an accurate or complete recreation of a target light field. As another example existing solutions sire typically bulky and not comfortable for users ,

[50] To address proble s: and limitations with existing electronic displays; embodiments of the disclosure provide a thin electronic system which offers both opacity and controllable unidirectional emulated transparency; as well as digital display capabilities. From one side th surface appears opaque, but from tire opposite side the surface can appear fully transparent _; appear fully opaque, act as a digital display _; or any combi· at ion of these. In some embodiments _; simultaneous plenoptic sensing and display technologies are combined within a single layered structure to form wha appears to- be a unidirectional visually transparent surface. The system may include multiple .layers of electronic arui optics for the purpose of srtificialJy recre ting transparency that may be augmented and/or digitally controlled. Individual i age sensor pixels on one side may be arranged spatially fco match the positions of display pixels on the opposite side of the a;; eon/d.y , In some embodiments , all electronic driving circuitry as well as some display logic circuitry may be sandwiched between the sensor layer and display layer, and each sensor pixel's Output signal slay be channeled through the circuitry to the corresponding display pixel cm the opposite side. In seems embodiments, this centrally-processed signal is aggregated with the incoming signal from the plenoptrc imaging sensor array on the opposite side, and is handled according to the following modes of operation. In VP. mode, the external video feed overrides the camera data, completely replacing the user's view of the outside world with the incoming view from the video, In AS mode, the external video feed is overlaid on the camera data, resulting in a combined view of both the external world and the view from the video ie,g,, the video data is simply added to the scene) , In MR mode, the external video feed is mixed with the camera data, allowing virtual objects to appear to interact with actual objects in the real world, alterin the virtual content to make is appear integrated with the actual environment through object occlasion, lighting, etc,

[51] Some embodiments combine stacked transparent high dynamic range iBDR} sensor and display pixels into a single s ructure, with sensor pixels on one side of the assembly ana display pixels on the other, and with pixel - for pixel alignment between camera arid display. Both the sensor and display pixel arrays ay be focused by groups of micro lenses to capture and display feur-dimeusional light fields, Thismeans that the complete view of the real world is captured on one side of the assembly and electronically reproduced on the other, allowing fo partial or complete alte atlog of the irsco ing image while m intaining image clarity, luminance, and enough angular resolution for the display side to appear tr nsparent, e en when viewed at oblique angles,

[ 52] FIGURES !¾~6C are provided to illustrate the differences between electronically emulated transparency provided by embodiments of the disclosure and typical camera images (such as through a camera viewfinder or using a smartphone to display its current camera image) - FIGURES iA~lC illustrate a reference scene with various 3D objects 110 (i.e,, 1104-0 } and a frontal viewing position according to certain embodiments . FIGURE In is a top view of an arrangement of it objects 110 and a frontal viewing direction of 3D objects 110. FIGURE IB is a perspective view of the same arrangement of 3D objects lit and frontal viewing directio as El ORE 1Ά. FIGURE 1C is the resulting front view of 3D objects 110 fret· the position illustrated In FIGURES 1¾ and IB. As ca be seen, the vie in FIGURE 1C of 3D objects 110 is a normal, ex ended view of 3D objects 110 pi . e . , the view of 3D objects 110 is not altered am all because there is nothing: between the viewer and 3D objects ilOs

[531 FIGURES 24-20 illustrate viewing the 30 obj cts 110 of FIGURES 14-1C through a transparent panel 210, according to certain embodiments , Transparent panel 210 may be, for example, a piece of transparent glass. FIGURE 2,A is a top view of a frontal viewing direction of 3D objects 110 through transparent panel 210, and FIGURE 2B is a perspective view of the same arrangement of 3D objects 110 and frontal viewing direction as FIGURE 24, FIGURE 20 is the resulting front view of 3D objects 110 through transparent panel 210 from the position illustrated in FIGURES 2A and 2B, Is can be seer; _; the view in FIGURE 2C of 3D objects 110 through transparent panel 210 is a no seal, expected view of 3D objects

HO (i.e., the view of 3D objects 110 is not altered at all because the viewer is looking through a transparent panel 210 f In other words, the view of 3D objects 110 through transparent panel 210 in FIGURE 2C is the sere as the view in

FIGURE 1C where no object is between the viewer and 3D objects110 d . e . , ''perceived’' transparency) _> Stated another way,· the edges of- the projected imagery on transparent pane! 210 line up with the view of the actual 3D objects 110 behind transparent panel 210 to create a view-aligned image 22GA of 3D objec llOh a view-aligned image 220B of 3B object IIGB, and a view-aligned image 220C of 3D object HOC.

154] FIGURES 3A--3C illustrate viewing the 3D objects 110 of FIGURES : 3- 1C through a earner a image panel 310, according to certain embodiments - Camera image panel 310 may be, for xam le _; a camera viewfinder or a display of a smartphone that is displaying its current camera image , In these images , camera image panel 310 is at an angle (erg., 30 degrees) to the viewer to illustrate ho such systems do not provide true emulated transparency . FIGURE 3A is a top view f a frontal viewing direction of 3D objects 110 through camera image panel 310- and FIGURE 3B is a perspective view of the same arrangement of 3D ob _j ects 110 and frontal viewing direction as FIGURE 3A. FIGURE 3C is the resulting front view of 3D chjects 110 through camera image panel 313 from the position illustrated in FIGURES 3Ά and 3B, As can be seen, the view in FIGURE 3€ of 3D objects 113 through camera image panel 31 G is different from a view of 3D objects 110 through transparent panel 210. Here, camera image panel 313 redirects the lines of sight that are normal to camera image panel 313- thereby shooing no perceived transparency (i.e., the image on cartara image parser 310 is not aligned with the vise but instead depicts the image acquired by the redirected i.iaes of sights .. Stated another cay, the edges of the projected ixsagery on camera image panel 310 do not line up with the iew of the actual 3D objects 110 behind camera image panel 310,

This is illustrated by an unaligned image 32CA of 3D object IIGA and an unaiigned iiaage 32OB of 3D object 11OK oh camera age panel 310 in FIGURE; 3€.

[5b] FIGURES 4A-4C illustrate viewing the 3D objects 110 of FIGURES 1A-IC through an emulated---transparency electronic pans! 410, according to certain embodiments. In these images, _· emulated transparency panel 410 is at an angle ; s 30 degrees) to the viewer to illustrate hoc emulated transparency pairs:! 410 provides true emulated transparency unlike camera imago panels 310, FIGURE it is a top view of a frontal viewing direction of 3D objects 110 through emulated transparency panel 410, and FIGURE 4 B is a perspective view of the same arrangement of 3D objects 110 and frontal viewing direction as FIGURE 4A, FIGURE 1C is the resulting front view of 3D objects 110 through emulated transparency panel 410 from the position illustrated in FIGURES 4A and 4B, As can be seen, fcho view in FIGURE iC of 3D objects 110 through emulated transparency panel 110 is different from a view of 3D objects 110 through camera image panel 310 but is similar to s view of 3D objects 110 through transparent panel 210, Eero, emulated transparency panel 410 does not redirect the lines of sight from the viewer through emulated transparency panel 410, but allows them to remain virtually unchanged and thereby providing emulated transparency U . o , , the image or. emulated transparency panel 410 is aligned with the view as in transparent panel 210} . Like transparent pane 1 210, the edges of the projected image ry on emulated transparency panel 410 lines up pith the vies? of the actual 3D objects 110 hehiud emulated t r anoparen cy panel 410 to create vieg-al igned image 2201 of 3D object 110A view-aligned image 220B of 3D object HOB; and view-aligned image 220C of 3D object HOC.

[56] FIGURE 5A-5C illustrate viewing the 3D objects

110 of FIGURES lA-IC through the camera image panel 310 of FIGURES 3L -301 but from an alternate angle. In. these images, camera image panel 310 is at a different 30 degree angle to the vreuer to further illustrate how such systems: do not provide true emulated transparency. Like in FIGURES 33- 30b the edges of the projected imagery on camera image; panel 310 do not line UP ith the mi.aw of tine actual 3D objects 110 behind camera image panel 310. This is illustrated by an unaligned image 3200 of 3D object HOC and an anaiiyned image 320E of 3D object .1103 on camera image panel 310 in FIGURE SC,

[571 EXSUPER 63-6C illustrate viewing the 3D objects

110 of FIGURES XA--1C through the oruiated-transparency electronic panel 410 of FIGURES iA-4C _f but from an alternate angle. Like in FIGURED 4A-4C, the edges of the projected imagery on cavoiated transparency panel 410 in FIGURE 6C line up pith the flop of the actual 3D objects HQ behind emulated transparency panel 410 to create view-aligned image 222B of 3D object HOB and view-aligned image: 22 DC ex 3D object HOC,

[ 5 B j As illustrated above in FIGURES 4A-HC and SA-6C, emulated transparency panel 410 provides view-aligned images 220 of 3D objects 110 behind emulated transparency panel 410. thereby providing electronically-emulated transparenc . FIGURES 7-3 illustrate an example embodiment of emulated transparency panel 410. FIGURE 7 illustrates a cnt-aeay view of an emulated· transparency asssiably 710 which may be emulated I: ranspa res :y panel ilO, _· and FIGURE 8 illustrates an exploded view of the emulated transparency a.aseedy 710 of FIGURE 7, according to certain embodiments .

[59: in some embodiments, emulated transparency assembly 710 includes two o nolens arrays 720 [ i , n , , a sensor side microiens arxay 720L and a display side microiens array 720B) , an image sensor layer 73Q, a circuit board 740, and an electronic display layer 760, In general, incoming light field 701 enters sensor side mere lens array 72 Oh where it is detecte by image sensor layer 730, Electronically-replicated outgoing: light field 702 is then generated by electronic display later 760 and projected through display side microiens array 72 OB. As explained in more detail below, the uniquearrangement and features of emulated transparency assembly 710 permits it to provide electronically-emulated transparency via electronica 11y-replicate outgoing light field 702, as well as otter features described below. While a specific shape of emulated transparency assembly 710 is illustrated in FIGURES 7-8, emulated transparency assembly 710 may hare any appropriate shape including any polygonal or non-polygonal shape, arid betas flat and non-flat configurations ,

[GO] Microiens arrays 720 [i.e. , sensor side microiens array 72Qh and display side micro leus array 72.bE} are generally layers of micrdlenses , In sums embodiments, each microiens: of microiens arrays 720 is a pienop l lc cell 1510 as described in more detail below in reference to FIGURE 15. In general, each microiens of sensor side microiens array 7201 is configured to capture a portion of incoming light field 701 and direct it to piwels within image sensor layer 730. Similarly, each microiens of display side microiens array ?20B is configured to emit a portion of eiectronicaiiy-rspiicated outgoing light field 702 that is generated by pixels of electronic display layer 760. In spite embodiments , each microiens of sensor side microiens array 72G& and display side microiens array 720B is in a 3D straps with a collimating lens oil one end of the 3D shape. The 3D shape ray be, for exempt e, a triangular polyhedrons a rectangular cuboid, a pentagonal polyhedron, a hexagonal polyhedron, a heptagonal polyhedron, or an octagonal polyhedron, In seen embossments , each microiens of sensor side microiens array 720Ά and display side microiens array ?20:B includes _: opaque wails such as cell wails 1511 (discussed below in reference; to FIGQRE 15 ^¾ that are configured to prevent light from bleeding into adjacent microienses . In some embodiments, each microiens of sensor side microiens array 72 Oh and display side microlens array 72 OS additionally or alternatively includes a light incidence angle rejection coating such as filter layer 1S40 described below to prevent light from bleeding into adjacent microlenses .

:j 61 ] in some embodiments, the micro!cases of sensor side microiens array 720A are oriented towards a first direction, and the microlenses of display side microiens array 720B are oriented towards a second direction that is 180 degrees from the first direction. In other words, same embodiments of emulated transparency assembly 710 include a sensor side microiens array 720A that is oriented exactly opposite from display sloe microiens array 7208. In other embodiments, any other orientation of sensor side microiens array 7 OA and display side microiens array 72GB is possible

(62] In general, image sensor layer 730 includes a plurality of sensor pixels that are configured to detect incoming light field 701 fter it passes through sensor side microiens array 720A, In soxse embodiments, linage sensor layer 730 includes an array of sensor units 735 ·; o . g .. sensor units 735A--C as illustrated in FIGURE 8} 1 Each sensor unit 735 may use a defined portion of image sensor layer 730 fe.g., a specific area such as a portion of a rectangular grids or a specific number or pattern of sensor pixels within image sensor layer 730 _< In some embodiments, each sensor unit 735 corresponds to a specific logic unit 755 of logic unit layer 759 as described below. In some embodiments , image sensor layer 730 is coupled to or otherwise immediately adjacent to sensor side microiens array 720h _> In some embodiments, image sensor layer 730 is between sensor side microiens array 720L and circuit board 740. In other embodiments, image sensor layer 730 is between sensor side microiens array 72OA and logic unit layer 750. In some embodiments, other appropriate layers may be included in emulated transparenc assembl 710 on either: side of image sensor layer 730. Furthermore, while a specific number and pattern of sensor units 735 are illustrated, any appropriate number (including only one) and pattern of sensor units 735 an be used.

[53^ Circuit hoard 740 is any appropriate rigid o flexible circuit board. In general, circuit board 740 includes various pads and traces that provide electrical connections between various layers of e ulate transparency assembly 710. As one example, in embodiments that include circuit board 740, circuit board 740 may be locate between image sensor layer 730 and logic unit layer 750 as illustrated in FIGURES 7~-8 in order to provide electrical connections between image sensor layer 730 and logic unit layer 750. In other embodiments, circuit board 740 may be located between logic unit layer 750 and electronic display layer 76 in order to provide electrical connections between logic unit layer 750 and electronic display layer 760. In some embodiments , circuit board 740 includes an array of unit attachment locations 745 {e- gc _f unit attachment locations 745h~C as illustrated in FIGURE 5) , Each unit attachment location 715 may be a defined portion of circuit board 7¾0 ) e .. g , a specific area such as a portion of a rectangular grid and nay include a plurality of pads ) a , g . , ball grid array (Boh) pad)and/or vias , In some embodiments, each unit attachment location 745 corresponds to a specific sensor unit 735 of image sensor layer 730 and a specific display unit 765 of electronic displa layer 760 ( e . g unit attachment location

7451 corresponds to sensor unit 7551 and display unit 765A) and is configured to permit electrical communication berecor; the corresponding specific sensor unit 735 and the specific di spIay unit 765.

[64) logic unit layer 750 provides optional /add! tienal logic and/or processing fox emulated transparency assembly 710. In general. logic unit layer 750 emulates transparency by directing signals from the pluralit of sensor pixels of image sensor layer 735 to the plurality of display pixels of electronic display layer 766. thereby emitting electronical ly- repiicated outgoing light field 702 from display side microlens array 720B at angles that correspond fo angles of the incoming light field 701 detecte through sensor side microiens array 720&. By emitting electronically·· replicated outgoing light field 702 from display side microiens array 72 OB at ang les that correspond to angles of the ) aeon Lo light field 701 detected through sensor side nr) orolens array 720h _? an image is displayed that matches what would be seen if emulated transparency assembly 710 pas not present emulated transparency; . In some embodiments, logic unit layer 750 Includes an array of logic units 755 ; a , g . , logic units

755A-C as Illustrated in FIGURE 8) . Each logic units 755 may be a defined portion of logic unit layer 750 (e . g . , a specific area such as a portion of a rectangular grid) .. In some embodiments, each logic unit 755 is a separate physical, _· rigid unit that is later joined to or coupled to other logic units 755 in order to form logic unit layer 750,. In some embodiments, each logic unit 755 corresponds to a specific sensor unit 735 of image sensor layer 73:0 and a specific display unit 755 of electronic display layer 750 ( c . g . , logic unit 755A corresponds to /and is electrically coupled to) sensor unit 735A and display unit 765 ) - In some embodiments, logic unit layer 758 is located between circuit board. 770 and electronic display layer 750, In other embodiments, logic unit layer 750 is betueeh image sensor layer 730 and circuit board ?¾G. In some embodiments, other appropriate layers stay be included in emulated transparency assembly 710 on either side of logic unit layer 750. Furtherspre, chile a specific number and pattern of logic units 755 is illustrated, any appropriate number (including none or only one) and pattern of logic units 755 may be used.

[651 In general, elect onic display layer 760 includes a plurality of display pixels that are configured to generate and project electronical l -replicated outgoing light field 702 through display side microiens array 720B. In some embodiments, electronic display layer 760 includes an array of display units 755 (e.g., display units 765A--C as illustrated in FIGURE 8} · Each display uni 70S may be a defined portion of electronic display layer 7G0 (e.g., a specific area such as a portion of a rectangular grid; or a specific number or patte n of display piaels within eiechronic dis lay layer 760. In some embodiments, each display unit 765 corresponds to a specific logic unit 755 of logic u it layer 750. In sore embodiments, electronic display layer 60 is coupled to or otherwise immediately adjacent to display side microlens array 72GB, In some embodiments, electronic display layer 760 is between display side microiens array 72GB and circuit board 740. It other embodiments, electronic display layer 760 is be tween d.i spray side microsere array 72GB and logic unit layer 750. In some embodiments , other appropriate layers may be loci ad·.;o in emu r ted transparency assembly 710 on either side of electronic display layer 760, harthe more _y while a specific number and pattern of display units 765 are illustrated _; any appropriate number (including only one) and pattern of display units 765 may be used,

(661 In some embodiments, the sensor pixels of image sensor layer 730 may be: sensor pixels 1800 as described in EIGURES 18-20 and their associated descriptions in y,3. Patent Application do, 15/724,027 entitled "Stacked Transparent Pixel Structures for Image Sensors," which is incorporated herein by reference in its entirety. In som embodiments _; the display pixels of electronic display layer 780 axe display pixels 100 as described in FIGURES 1-4 and their associated descriptions in U.S. Patent Application bo, 15/724,004 entitled "Stacked Transparent Pixel Structures for Electronic Displays _; " which is Incorporated herein by reference in its enti ety,

(67d While FIGURES 7-8 depict emulated transparency assembly 710 as having arrays of sensors, displays, and electronics, other embodiments nay have single-unit setups, urteermors, while the illustrated embodiment s of emulated transparency assembly 710 depict unidirectional emulated transparency (i,e, allowing the capture of incoming light field 701 from a single direction and displaying a corresponding electron! cally---repiicated outgoing light field 702 in the opposite direction} a other embodiments may include arrangements and combinations of: emulated transparency assembly 710 that permit bidirectional transparency„

[bd FIGURE 3 illustrates a method 900 of manufacturing hive emulated transparency assembly 710 of FIGURE 7, according to certain embodiments. Method 300 may begin in step 910 where a plurality of unit attachment locations are formed on a circuit board. In some embodiments, the circuit board is circuit board 740 and the unit attachment locations are unit attachment locations 145. I some embodiments, each unit attachment location corresponds to one of a plurality of display units such as display units 765 and: one of a plurality of sensor units such as sensor units 735.

[69] Lt step 320, a plurality of sensor units are coupled to a first side of the circuit board. In some embodiments, the sensor units are sensor units 735, In some embodiments, each sensor unit is coupled in step 320 to a respective one of the uni t. attachment locations of step 910, In some embodiments, the sensor units are first formed into an image sense.:: layer such as image reason layer 730, and the image sensor layer is coupled to the first side of the circuit board in this step.,

[70 j h.t step 930, a plurality of display units are coupled to a second side of the circuit board that is opposite the first side. In some embodiments, the display units are display units 765, In some embodiments, each display unit is coupled to a respective one of the unit attachment locations. In some embodiments, the display units are first formed into a display layer such as electronic display layer 760, as'si the display layer is coupled to the second side of the circuit board in this step.

[ 71 f A;· step 940, a first plurality of microienses are coupled to the plurality of sensor units of step 92:0. In sore mbodi ents, the microienses are plenoptic ceils 1510. In some embodiments, the microienses are first formed into an microiens array layer such as sensor side microlens array 720A, and the microiens array layer is coupled to the sensor unit .

[72] At step 955, a second plurality of microienses are coupled to the plurality of display units of step 930 In some embodiments, the microienses are plenoptic cells 1510. In some embodiments, the microienses are first formed into an mi.or;, leas array layer such as display side microiens array 720B:, and the microiens array layer is coupled to the display units, after step SS0, method 905 may end.

73] In sore· embodiments , method 900 may additionally include coupling a plurality of logic units between the circuit hoard of step 910 and the plurality of display units of step 930. In some embodiments, th logic units axe logic units 755, In some embodiments, the plurality or logic units are coupled between the circuit board and the plurality of sensor units of step 920.

174 ] Particular embodiments may repeat one or more steps of method 900, where appropriate. Although this disclosure describes and iiiustrates particular steps of method 900 as occurring in a particular order, this disclosure contemplates any suitable steps of method 990 occurring in any suitable order (e.g., any temporal order). Moreover, although t is disclosure describes add illustrates an example cm ..dated transparency assembly manufaeluring method including the particular steps of method 310, this disclosure contemplates any suitable emulated transparency assembly manufacturing method including any suitable _: steps, which may include all, some, or none of the steps of method 900 where appropriate _> Furthermore, although this disclosure describes and illustrates particular components, devices:, or systems carrying out particula steps of method SQG, this disci core contemplates any suitable combination or any suitable componen s , dev.; ces , or systems carrying out any suitable steps of method 300.

[75] FIGURE 10 illustrates a direct sensor-to-display system [1030 that may fee implemented by the emulated transparency assembly of FIGURE 7, according to certain embodiments .. In general, FIGURE 10 illustrates non embodiments of emulated transparency assembly 710 utilise a direct association of input pixels to corollary output pixels. In some embodi ent s , this is accomplished fey using a layered approach such that the image sensor layer 730 and electronic display layer 760 are In close proximity to one another, mounted on opposite side of a shared substrate em;:,, circuit board 740} as illustrated in FIGURES 7-3, Signals 5 rem image sensor layer 730 may be propagated directly to electronic display layer 760 through circuit board 740 (and logic unit layer 730 in some embodiments) . Logic unit layer 730 provides simple processing with optional input for any necessary control or augmentation. Typical electronic sensor/dispiay pairs (e.g. , a digital camera) do no express a one-to-one relationship in that the display is not coupled directly with the input sensor and thus requires some degree of image transformation. Certain embodiments of the disclosure,· however, implement a one-to-one mapping between input and output pixels (i,e„ , the sensor pixel and display pixel layouts are identical) ,· thereby circumventing the need for any image transformation , This reduces the complexity and power requirements of emulated transparency as sarms1y 710.

[76] As illustrated in FIGURE 1 Cp each sensor unit 735 is directly coupled to a corresponding display unit 765- Hor example, sensor unit 735A may be directly coupled to display unit 753A, _· sensor unit 735B may be directly coupled to display unit 765B, and so on. in some embodiments, _· the signaling between sensor units 735 and display unite 765 ma be any appropriate differential signaling such as low-voltage differential signaling [LVDS) - fore specifreally, each sensor unit 735 may output first signals in a specific format (e,g, _f LVDS) that corresponds to incoming light field 701, In some embodiments!· the first signals are sent via a corresponding logic unit 755, which in turn sends second signals to display unit 765 in the same format as the first signals LVDS}. In other embodiments the first signals are sent directly to display uni s 765 from sen or units 735 _* o , g . , sensor units 735 and display units 765 are coupled directly to opposite sides of circuit board 760) . Display unit 755 receives the second signals from the logic unit 755 [or the first signals directly from the sensor unit 735 via circuit board 740) and uses them to generate outgoing light field 702.

[77] Because no conversion is needed in the signalin between sensor units 735 and display units 765, emulated t ransparency assembl 710 may provide many benefits from typical display/sensor combinations. First, no signal processors are needed to convert the signals from sensor units 735 to display units 765. For example, do off-board signal processors arc needed to perform image transformation between sensor no: f s 735 and display units 765, This reduces the space, complexity, weight, and cost requirements for emulated transparency assembly 710, Second, emulated transparency assembly 710 may provide greater resolutions than would typically be possible for display/sensor combinations . By directly coupling sensor units 735 with display units 765 and not requiring any processing or transformation of data between the units, the resolution of sensor units 735 and display units 765 may be far greater than would typically be possible. Furthermore, emulated transparency assembl 710 may provide heterogeneous resolutions across sensor units 735 and display units 765 at any particular time, That is, a particular sensor unit 735 and corresponding display unit 765 may have a pa ticul r resolution that is different from other sensorunits 735 and display units 765 at a particula tiine, and the resolutions of each sensor unit 735 and display unit 765 may be changed at any time, _<

[781 In some embodiments, each particular sensor pixel of a sensor unit 735 is mapped to a single display pixel of a corresponding display unit 765, and the display pixel displays light corresponding to light captured by its mapped sensor pixel. This is illustrated best in FIGURES G7Ά--17B, As one example, each center sensing pixel 1725 of a particular pienoptic cell 1510 of sensor side microlens array 727A (e.g,, the bottom pienoptic cell 1510 of sensor side mi.oroiens array 720A in FIGURE 17Ά; is mapped to a center display pixel 1735 of a cor esponding pienoptic ceil 1510 of display side miorolens array 720B (e.g,, the bottom pienoptic cell 1510 of display side microlens array 720B in FIGURE 17A) . As another exaisple _f each top sensing pixel 1725 of a particular plenoptic ceil 1510 of sensor side microlens array 7255 ] o , g , , the top plenoptic cell 1510 of sensor side coercions array 720 in FIGURE I?B) is mapped to a bottom display pixel 1735 of a corresponding plenoptic cell 1510 of display side micrelena array 720B i e . g . , the top plenoptic ceil 1510 of display side microlens array 720B in FIGURE 17B) .

[79] In some embodiments , sensor units 735 are coupled directly to circuit board 740 while display units 765 are coupled to logic units 755 {which are in turn coupled to ci rcui.t board 740] as 11Instrated in FIGURE 8. In other embodiments, display units 755 are coupled directly to circuit board 740 while sensor units 735 are coupled to logic units 755 (which gre in turn coupled to circuit board 740}, In other embodiments , both sensor units 735 and display units 765 are coupled directly to circuit board 740 without any intervening logic unit s 755) In such embodi men -..a , sensor units 735 and display units 765 are coupled to opposite sides of circuit board 74Q at unit attachment locations 745 (e . g . , sensor unit 735A and display unit 765Ά are coupled to opposite sides of circuit board 740 at unit attachment location 745/G .. if 80 ] FIGURE 11 illust rates a method 1100 of manuxactarimg the direct sensor~to~di:spiay system IGOO of FIGURE 10, according to certain embodiments Method 3130 may begin at step 1110 where a plurality of unit attachment locations are formed on a circuit board. In some embodiments, the circuit board is circuit board 74G and the unit attachment locations are unit attachment locations 745, In sore embodiments, each unit attachment location corresponds to one of a plurality of display units and one of a plurality of sensor units. The display units may be display units 765· and the seneor units soy be sensor units 735. 1n some embodimen s each particular unit attachment location includes EGA pads that are configured to couple to one of the plurality of sensor units and/or one of the plurality of logic units. In some embodiments- each particular unit attachment location includes a plurality of interconnection pads configured to electrically couple the particular unit a tenement location to one or more adjacent unit attachment locations- In some embodiment a , the unit attachment locations are arranged into a plurality of columns and plurality of rocs as illustrate in FIGURE 8

[81:| At step 1 i 10 - a plurality of sensor units are coupled to a first side of the circuit board,. In co e embodiments each sensor unit is coupled to a respective one of the unit attachment locations of step 1110, At step 1130- a plurality of display units are coupled to a second side of the circuit board that is opposite to the first side- In some embodiments- each display unit is coupled to a respective one of the unit attachment locations of step 1110 such that each particular one of the plurality of sensor pixel units is mapped to a corresponding one of the plurality of display pixel units. By mapping eseh particular sensor pixel unit to one of the display pixel units- the display pixels of each particular one of the plurality of display pixel units are configured to display light corresponding to light captured by sensor pixels of its mapped sensor pixel unit. After step 1X30- method 1100 may end,

[32] Particular embodiments may repeat one or more steps of method 11 Oh, where appropriate. Although this disclosure describes and illustrates particular steps of method 1X00 as occurring In a particular order, this disclosure contemplates any suitable steps of method 1100 occurring in any suitable order (o , g , , any temporal order}. Morsove _K , although this disclosure describes and illustrate» an example direct sensor-to-di play system manufacturing method including the particular steps of method 1100, this disclosure contemplates any suitable direct sensor-to-d splay system manufactazing method including any suitable steps, which may include all, some, or none of the steps of method 1100, where appropriate . Furthermore, although this disclosure describes and illustrates particular components, devices, or systems carrying out particular steps of method 1100, this disclosure contemplates any suitable combination of any suitable components, devices, or systems carrying out any suitable steps of method 1100,

[83! F!GiJRSS 12-13 illustrate various in-layer signal processing configurations that may be used by emulated transparenc assembly 710 of FIGURE 7, according to certain embodiment s _> In general, the configurations of FIGERES 12-13 utilise a layer of digital logic (e.g. _f logic unit layer 750} that is sandwiched between the camera and display (i„e,, between image sensor layer 730 and electronic display layer 760), These configurat ons allow for local, distributed processing of large quantities of data · o . a . , 160k of image data or more), thereby circumventing bottlenecks as well as pe formance, power, and transm ssion line issues associated with typical configura ions. Homan visual acuity represents a tremendous amount of data which must be processed in real- time, Typical imaging aysterns propagate a single data stream to/from. a high-powered processor i o . g . , a CPU or GPU), which may or may not serialize the data for manipulation. The bandwidth required for thorn approach at human 277/20 visual soul cy fax exceeds that of any known transmissio protocols. Typical systems also use a sastei controller which is responsible fox either processing all ;.coord no /on lyoi.oe data or managing distribution to smaller processing nodes. Regardless _f all data must be transported off-system/ ofr-chip, manipulated, and then returned to the display deviceis} .

However, this typical approach is unable to handle the enormous amount of data required by huma visual acuity, tabod.imerits of the disclosure, however, harness the: faceted nature of a sensor / ^' display combination ns described herein to docentra1ise and loca11 ze si.gna1. prooes sing . Th is enab1es previously unachievable real-time digital image processing.

S4d As illustrated in FIGURES 12-13, certain embodiments of emulated transparency assembl 710 include logic: unit layer 750 that contains the necessary logic to manipulate input signals from Image sensor laye 730 and provide output signals to electronic display layer 760. In some embodiments:, logic u it layer 750 is located between image sensor layer 730 and circuit beard 750 as illustrated in FIGURE 12, In other embodiment s , logic unit layer 75:0 is located between circuit board 740 and electronic displa layer 760 as illustrated in FIGURE 13. In general, logic unit layer 750 Is a specialised image processing layer that is capable of minin an input signal directly from image sensor layer 730 and performing one or more mathematical operations ( o , g , , matrix transforms} on the input signal before outputting a resulting signal directly to electronic display layer 76b, Since each logic unit 755 of logic unit layer 750 is responsible Only for lids associated facet: fi.e., sensor unit 735 or displa unit 765} , the data of the particular logic unit 755 can be manipulated with no appreciable impact to the system-level J/Q, This effectively circumvents the need to parallelize any incoming aenact data for centralised processing. The distributed approach enables emulated transparency assembly 710 to provide multiple features such as magnification/ room /each facet applies a scaling transform to its input), vision correction /each facet applies a simulated optical transformation compensating for common vision issues such as near-sightedness, far-sightednes , astigmatism, etc.), color blindness correction (each facet applies a color traasformation compensating for common color blindness issues) , polari ration (each facet applies t ansformation simulating nave polarisation allowing for glare reduction), and dynamic range reduction (each facet applies a transformation that darkens high-intensity regions (e,g, Sun) and lightens low-intensity regions (s,g, shadows)). Furthermore, since any data transformations remain localised to logic unit layer 750 of each facet, there may be no need for long t ransmission lines. This oi rcumyents issues of cross talk:, signal integrity, etc. Additional ly, since the disclosed embodiments do not require optical transparency (but instead harness emulated transparency) , there is no functional impact to placing an opaque processing layer between the sensor and display facets,

[8Sj In seme embodiments , logic unit layer 75C contains discrete logic units (e.g,, transistors) that are formed directly on circuit board 740. For example, standard photo lithography techniques may be used to form logic unit layer 750 directly on circuit board 740, In other embodiments, each logic unit 755 is a separate integrated circuit ⁽ IC/ that is coupled to either a sensor facet or a display facet, or directly to circuit board 750, hs used herein, "facet" refers to a discrete unit that is separately manufactured and then coupled: to circuit board 710.. For example, a "display facet" may refer to a unit that includes _: a combination of an electronic display layer 760 and a display side microlens array 720B, _· and a "sensor facet" may refer to a unit that includes a combination of an image sensor layer 730 and a sensor side microiens array 750A. In some embodiments, a display facet may include a single display unit 750,. or it may include multiple display units 765. Similarly, a sensor facet may include a single sensor unit 735, or it may include multiple sensor units 735- In sone embodiments , a logic unit 755 may be included in either a sensor facet or a display facet . In embodiments where a logic unit 755 is a separate IC that is coupled directly to either a. display or sensor facet (as opposed to being formed directly on circuit board 740) _f any appropriate technique such as 3D IC design with through- silicon vias may be used to couple the IC of logic unit 755 to a wafer of the facet,

186) In some embodiments, logic unit layer 750 is an application-specific integrated circuit {ASIC) or an arithmetic logic unit (ALtd , but not a general purpose processor- This allows logic unit layer 750 to be power efficient, Furthermore, this allows logic unit layer 750 to operate without cooling, further reducing cost and powerrequi ements of emulated transparency assembly 719,

[87] In some embodiments, logic units 755 are configured to communicate using the same protocol as sensor units 735 and display units: 765, For enample, in embodiments where logic units 755 are discrete ids , the ICs may be configured to communicate in a same protocol as the sensor and display facets ie.g., lAdlS or Inter-Integrated Circuit Tills eliminates the problem of having to translate between the sensor and display facet , thereby reducing power and cost.

[8S] In seme embodiments, logic unit layer 750 performs one or more operations on signals received from image sensor layer 730 before transmitting output signals to electronic display layer 760, For example , logic unit layer 750 may transform received signals from image sensor layer 730 to include augme ted information for display on electronic display layer 760 This may be used, for example, to provide Mi to a viewer, In some e bo iments; logic unit layer 75D may completely replace received: signals from .Image sensor layer 730 with alternate information for display on electronic display layer 760, This may be used _; for example, to provide Vh to a viewer,

[89] FIGURE 14 Illustrates a method 1700 of manufacturing the in-layer signal process fug systems of FIGURES 12-17, accordin to certain embodiments , Method 1400 may begin in step 1410 where a plurality of sensor units sire coupled to a first side of a circuit, board. In some embodiments, the sensor units are sensor units 735, and the circuit board is circuit board 740. In seme embodiments, each sensor unit is coupled to one of a plurality of unit attachment locations such as unit attachment locations 745. Each sensor unit includes a plurality of sensor pixels,

[90] At ste 1420, a plurality of display units are formed. In s one embodiments , the display units are a combination of display units 765 and logic units 735. Each display unit may be formed by combining an electronic display and a logic unit into a single 3D integrated circuit using through- silicon vias. Each display unit includes a plurality of display pixels. [91] At step 1430, the plurality of display unit» of step 1420 are coupled to a second side of the circuit hoard that is opposite the first side, In some embodiments , each logic unit is coupled to a respecti e one of the unit attachirtent loc tions. After step 1430, method 1400 cay a rot,

[92] Particular embodixsents may repeat one or moresteps of method 1400, where appropriate. Although this disclosure dea rates and illustrates particular steps or xaethod 1400 as occurring in a particular order, this disclosure contemplates any suitable steps of xaethod 1400 occurring in any suitable orde ( e . g . , any temporal order) . Moreover, although this disclosure describes and illustrates an escample in-layer signal proses sing system manufacturing method including the particular steps of method 1400, this disclosure contemplates any suitable xn-iayer signal processing system manufacturing method including any suitable steps, which may include a11, some, or none of the steps of method 1400, where appropriate. Furthermore, although this disclosure describes and illustrates: particular components, devices, or sys exts carrying out particular steps chi method 1900, this disclosure contemplates any suitable combination of any suitable ooc·:roc:ocR:.¾ , devices:, or systems carrying out any suitable steps of method 1420,

[S3] FIGURES 13--17C illustrate various views of an array 1500 of pienoptic cells 1510 that may be used within xrb.erolens arrays 72GA-B of emulated transparency assembly 710, FIGURE 15 illustrated a pienoptic ceil assembly 1500, FIGURE 16 illustrates a cross section of a portion of the pienoptic ceil assembly 1500 of FIGURE 15, and FIGURES 17A-17C 1,1 lustrahe cross sections of a port ion of the; pienoptic oel 1 assembly 1500 of FIGURE 15 with va :·: ous incoming and outgoing fields of light.

[94] Standard electronic displays typically include planar arrangements of pixels which form a f o-d.i mens!oral rasterized itage, conveying inherently two-dimensional data. One limitation is that the planar image cannot be rotated in order to perceive _: a different perspective within the scene being convoyed , In order to clearly view this image;, regardless of what is portrayed within the image itself, either a viewer's eyes or the lens of a camera must focus on the screen. By contrast _y a volume of light entering the eyes from the real world allows the eyes to naturally focus on any point within that volume of light. This plenoptic ''field" of right contains rays of light from the scene as they naturall enter the eye, as opposed to a virtual image focused by an external lens at a single focal plane. While existing light field displays ma b able to replicate this phenomenon, _: they present substantial tradeoffs between spatial and angular resolutions, resulting in the perceived volume of light looking fumy or scant in detail.

[95] To overcome problems and limitation with existing light field displays, embodiments of the disclosure provide a coupled light field capture an display system that is capable of recording and then electronically recreating the incoming plenoptic volume of light. Both the capture and the display process are accomplished by an arrangement of plenoptic cells 1510 responsible for recexding or displaying smeller views of a larger compound image. Each plenoptic ceil 1510 of the sensor is itself comprised of a dense cluster of image sensor pixels, and each plenoptic ceil of the displa is itself comprised of a dense cluster of displa pixels. In both cases, light rays entering the sensor cells or exiting the display cells are focused by one or more transparent iensiets 1512 to produce a precisely tuned distribution of near col lirasted rays. This essentially records an incoming light field and reproduces it on the opposite side of the assembly , More specifically, for the sensor, _· the volume of light entering the lens (or series of lenses) of phis cell is focused onto the image pixels such that each pixel usurers light iron only one direction, as determined by its position within the cell and the profile of the lens. This allows rasterised encoding of Hue various angular rays within the light field, with the number of pixels in the ceil determining the angular resolution recorded . lor the display,· the light emitted from the pixels is focused: by an identical lens (or series of lenses) to create a volume of light that matches what was recorded by th sensor, pins any electronic augmentation or alterations c , ., , _· from logic unit layer 750 described above) . The cone of emitted light from this cell contains a subset of rays at enough interval angles to enable the formation of a light field for the iewe , where each output ray direction is determined by the position of its originating pixel within the cell and the profile of the lens.

[96] Pienoptic ceils IS!O may be utilized by both sensor side rrdcroiens array 7201 and display side miorolens array 720B, Fo example, multiple pienoptic cells 1510A may be included in sensor side mi ore Lens array 720A, and each pienoptic cell if 1:0A may be coupled to or otherwise adjacent to an image sensor 1520. Image sensor 1520 may be a portion of image sensor layer 73:0 and may include a sensor pixel array 112:5 that includes sensing pixels 1725. Similarly, multiple pienoptic ceils 151 OB may be included in display side xmlcroieis: array 7203, aad each plenoptic cell 1510B iray be coupled to or otherwise adjacexxt to a display 1530. Display 1530 may be a portion of electronic display layer 760 and may ieeladd a display pixel array 1625 that Includes display pixels 1733. Sexxsing pixels 1725 may be sensor pixels 1000 as described in FIGURES 18--20 axd their associated descriptions ip Odd. Patent Application No. 15/727 , 027 entitled ^' 'Stacked Transparent Pixel Structures fee: brago Sensors," which is incorporated herein by reference in its entirety. Display pixels 1735 ray be display pixels 100 as described in FIGURES I--4 and their associated descriptions in 0.0. Patent Application Ho. 15/727.004 entitled "Stacked Transparent Pixel Structures for Electronic Displays," which is incorporated herein by reference in its entirety.

[571 In come embodiments, plenoptic cell 1510 ineludes a transparent isnsie 1512 and cell walls 1514. Specifically, plenoptic cell 1510A includes transparent lensiei 1512A and ceil walls 1514A, and plenoptic ceil 1510:8 includes transparent lenslet. 15133 and cell walls I5I4B. In sore embodiments, transparent leuslet 1512 contaixxs a 3D shape with a collimating lens on one end of the 3D shape. Far example, as illustrated in FIGURE 15, transpsrent lenslet 1512 may be a rectangular cuboid with a collimating lens on one and of the rectangular cuboid _> In otter eu.oodimes as , the 3D shape of transparent lensiet 1512 xaay be a triangular polyhedron, a pentxagonal polyhedron, a hexagonal polyhedron, a heptagenai polyhedron, an octagonal pol hedron, a cylinder, or axxy other appropriate shape. Each plenoptic cell 1510A includes an input field of view iFGv) 1610: (e, g,, 35 degrees:, axxd each plenoptic cell 15103 includes an output FOE 1620 [e.g., 30 degrees)„ In some embodiments, input FGV 1610 matches output FOv 1620 for corresponding pienoptie cells 1510.

:[ 98 ] Transparent lenslet 1512 may be formed from any appropriate transparent optical material, tor exa ple, transparent lenslet 1512 may be formed from a polymer, silica glass, or sapphire. In some embodiments , transparent lenslet IS 12 may be to.men from a polymer such as polycarbonate or acrylic. In some embodiments , transparent lenslets 1512 may he replaced with waveguides and/or photonic crystals in order to capture and/or produce a light field.

if S3 } In general, cell walls 1514 are barriers to present optical crosstalk between adjacent pienoptie cells 1510. ceil walla 1514 may be formed from any appropriate material that is opaque to visible light when hardened. In some embodiments , cell walls 1514 are formed fro a polymer. Presenting optical cross talk using ceil walls 1514 Is described in more detail below- in reference to FIGURES 17A and let

RIGG] In some embodiments, image sensor 1520 includes or ^¬ is coupled to backplane circuitry 163 Gb, and display 1530 includes or is coupled to backplane circuitry 163GB. In general, backplane circuitry 1630A--B provides electrical connections to permit image data to flow fro image sensor

1520 to display 1550. In some embodiments , backplane circuitry 153Ch and backplane circuitry 163GB are the opposite sides of a single backplane. In se e embodiments., backplane circuitry 1.630A and backplane circuitry IS30B are circuit board 740,

El013 In some embodiments, a filter layer 1640 may be included on one or both ends of transparent lenslet 1512 in order to restrict the entry or exit of Light to a specific incidence angle. Fo example, a first filter layer 1640¾ may fee included on the convex end of transparent iensiet 1512, and/or a second filter layer 164 OB may be included on the opposite end of transparent Iensiet 1512. Similar to cell wails 1514, each a coating or film may also limit image bleed between adjacent transparent ionslets 1512 to an acceptable amount, Filter layer 1640 may be used in addition to or in place of cell walls 1514.

[1021 1 ^' didRES 17¾-170 each illustrate a croc s-sect Lor··:;! view of seven adjacent pienoptic cells 1510 for a sensor side mierolens array 7201 and a corresponding display side microlens array 720E. These figures snow no incoming light fields 701 sirs captured by image sensors 1520 and electronically replicated on display 1530 to emit a virtually identical field of light, in FIG0RB 17&, an incoming light field 1710 from objects directly in front of file sensor pienoptic cells 1510 are focused by the transparent le slets 1512 of the sensor pienoptic ceils 1510 onto center sensing pixels 1725, Corresponding light is then transmitted by corresponding center display pixels 1735 of corresponding display pienoptic ceils 1510. The transmitted light is focused and emitted as emitted light field 1711 by the transparent ienslets 1 ¾12 of display pienoptic cells 1510, Emitted light field 1711 precisely matches the zero degree: source light field ii,e., incoming light field 1710), In addition, emitted light rays striking ceil walls 1514 at location 1740 that would otherwise penetrate adjacent display pienoptic ceil 1510 are blocked by the opaque ceil wails 1514, thereby preventing optical cross-talk.

[ 1Q:31 In FIGURE 17E an incoming light field 1720 from objects fourteen degrees off the amis of sensor pienoptic ceils 1510 ace focused by the transparent lenslets 1512 of the sensor plenoptic ceils 1510 onto top sensing pixels 1725, Corresponding light is then transmitted by correspon ing opposite (i . e bottom) display pixels 1735 of corresponding display plenoptic ceils 1510, The transmitted light is focused and emitted as emitted light field 1721 by tbs transparent Iensiets 1512 of display plenoptic ceils 1510, Emitted light field 1721 precisely matches the 14 degree sourc light field P.. e . , incoming light field 17203 ,

[104) In FIGORE 7C, an incoming light field 1730 fro objects 25 degrees off the axis of sensor plenoptic cells I51.G are focused by the transparent Iensiets 1512 of the sensor plenoptic cells 1510 entirely onto cell wails 151 . Because incoming light field 1730 Is focused entirel onto ceil walls 1514 of sensor plenoptic ceils 15I G instead of sensing pixels 17 lip no corresponding light is transmitted by corresponding display plenoptic ceils 151 G, In addition, incoming light rays striking cell walls 1514 at location 1750 that would otherwise penetrate adjacent sensor plenoptic cells 15X0 are blocked by the opaque cell walls 1514, thereby preventing optical cross-talk ,

[105 FI GIJRES 18A--18B illuatrate a method ofmanufacturing tbs plenoptic ceil assembly of FIGURE 15. according to certain embodiments .. In FIGURE I8A, a microlens array (EILA) sheet 1810 is formed or obtained. Fife sheet 1810 includes a plurality of iensiets as illustrated, In FIGURE X8B, a plurality of grooves 1820 are cut around each of the plurality of Iensiets of H1A sheet 1810 to a predetermined depth. In some embodiments, grooves 1820 may be cut using multiple passes to achieve the desired depth. In some embodiments, grooves 1820 may be cut using laser ablation, etching, lithog aphic processes, sr any other appropriate method. After grooves I 8 0 ere cut to the desired depth, they are filled with a material configured to prevent light from bleeding through grooves 1820. In some exsbodiments, the materiel is any light absorbing (s,g, , carbon nanotufcesf o opaque: material (e.g., a non-reflective opaque material or a tinted polymer} when hardened. The resulting plsnoptic cell assembly after grooves 1820 are filled and aliened to harden is illustrated in FIGURES 22-21.

[106] FIGURES 19A~19B illustrate another method ofmanufacturing the plenoptic ceil assembly ox FIGURE 18, according to certain embodiment s . In FIGURE 19A, a pre-for ed lattice 1830 having voids 1810 is obtained or formed , Lattice 1830 is ade of any suitable material as described above for cell wails 1514. Lattice 183G may be formed from; any suitable method including, but not limited to, additive manufacturing and ablation of cell matter.

[103] In FIGURE 1SB, voids 1810 are filled with an optical polymer 1850. Optical polymer 1850 may be any suitable material as described above for transparent lensier 1512. After voids 1840 are filled with optical polymer 1850, the final lens profile is created using molding or ablation. .Ail example of the resulting plenoptic cell assembly after the lenses are formed is illust ated in FIGURES 20-21.

[108] FIGUEE 22-23 ill uatra es a flexrbis cireuit boa rd 2210 that may be used as circuit board 740 by the emulated transparency assembly 710 of FIGURE 7, according to certain embodiments. Generally, -wrapping electronics around a 3D shape suc as spherical or semi spherical surface is a nontrivial task. Though various examples of flexible and even stretchable circuitry are currently available, there ar several hardies to overcome w en ositioning such electronics on a small radius fe.g,, 30 60 mm) spherical or semi spherical surface. For example, bending of flexible electronics substrates in one direction does not inherently indicate adaptability to compound curvature, as the torsional forces required for such curvature can be damaging to the thin films involved. As another example questions remain about the degree of stretekabiiity and lifetime of stretchable electronics currently available,

[10si To address the problems and limitations of current solutions, embodiments of the disclosure present a 3D en g., spherical or seraispherical) electronics manufacturing method using a geodesic faceted approach consisting of an array of small, rigid surfaces built on a single flexible circuit. In some embodiments, the flexible circuit, is cut to a specific net shape and then wrapped to a 3D shape (e,g,, a spherical or semisphsricai shape· and locked into place to prevent wear and tear from repeated flexing. The method is especially useful to accommodate the narrow radii of curvature (e,g, 30-60 iss) necessary for head-mounted near-eye wrapped displays. In some embodiments, the assembly includes a single, foundational flexible printed circuitry layer, with rigid sensor and display arrays layered on opposite sides of the flexible circuit. The entire assembly including sensor and display layers may be manufactured by standard planar semiconductor processes : o . g . , spin coatings, photolithography, etc,). The rigid electronics layers may he etched to term individual sensor and display units ii,e,, ''facets"} and then connected to the flexible circuitry by connection pads and adhered through patterned conductive and non-condnotlve adhesives. This permits the: flexible circuitry to fold slightly at the edges between he rigid facets , 1n seme ej¾bociitie _: nts _f following planar manufsctur ing, the fully cured and functional electronic: stack is formed to the desire final 3D shape using one aide of a final rigid polymer casing as a mold, In thrs v/a y the arrays of rigid electronics facets are not deformed but simply fall into place In their mold, with the flexible circuitry bending at defined creases/gaps to match the faceted interior of th casing . The assembly may be finally capped and sealed using an opposite matchin side of the rigid casing,

:[ 110| Embodiments of the disclosure are not limited to only spherical ox semisoner ca1 shapes, although such shapes are certainly contemplated. The disclosed embodiments may be formed into any compound curvature or any other revolved shape. Furthermore, the or solored embodiments may be burned into any non-uniform curvature, as well as non-curved (i,e, fiat) _: surfaces,

[111] FIGURE 22 illustrates flexible circuit board 2210 in two different states: a fiat flexible circuit board 2210A and a 3D-shaped flexible circuit board 22 IDE, Flexible circuit board 2210 includes facet locations 2220, which in general are locations in which facets (e,g,, sensor facets 3735, di play facets 2655, or logic facets 2655 discussed below) gay be installed on flexible circuit board 2210. In some embodiments, flexible circuit board 2210 includes gaps 2215, As illustrated in the bottom portion of FIGURE 22, when flexible circuit board 2210 is flat, at least some of facet location 2220 are separated from one or more adjacent facet locations 2220 by one or more gaps 2215, As illustrated in the top portion of FIGURE 22, when flexible circuit board 2210 is formed into a 3D shape, gaps 2215 may be substantially eliminated, thereby forming a continuous surface across at least some of the facets that are coupled at facet locations 2220 (s a continuous sensing surface across multiple sensor facets 3735 or a continuous display surface across multiple display facets 2665) _<

[1121 in general , facet locations 2220 may have any shape. In some embodiments, facet locations 2220 are in the _S hape of a polygon (e,g·, , a triang ;.e, square, rectangle, pentagon, hexagon, heptagon, or octagon) . In some embodiments, facet locations 2220 are all identical. In other embodiments, aoeovor , facet locations 2220 ail share the same polygon shape (e.g., all are hexagonal), but have different dimensions. In seme embodiments , facet locations 2229 have heterogeneous shapes (e,g,, some are rectangular and some are hexagonal) . buy appropriate shape of facet Locations 2220 may he used.

[113] In some embodiments, facet locations 2220 are arranged in columns 2201, In some embodiments, facet locations 2220 are additionally er alternativel arranged in roes 2202. While a specific pattern of facet locations 2220 is .illustrated, any appropriate pattern of facet locations 2220 may be used.

[Hi! FIGuRE 23 illustrates additional details of flexible circuit boar 2210, according to certain embodiments, in some embodiments, each facet location 2220 includes pads and/or vies for coupling sensor or display facets to flexible circuit board 2210. As an example, some embodiments of flexible circuit board 2210 include BGA pads 2240 at each facet location 2220. Any appropriate pattern and number of pads/viaa may be included at each facet location 2220.

[115] In general, each particular facet location 222:0 is configured to transmit signals between a parti Ctrl.at s¾asor facet coupled to the particular facet location and a particular display facet coupled to an opposite side of the particular facet location. For example* a particular facet location 2221) cay have a sensor facet 3735 coupled to oneside* and a displa facet 2 iff coupled to its opposite side. The particular facet location 2220 provides the necessaryelectrical connections t pert·it signals from the sensor facet 3735 to travel directly to the display facet 2665 _* thereby enabling the display facet. 2665 to display light that corresponds to light captured by the sensor facet 3735.

[116:1 In some embodiments _f wire traces 2230 are included on flexible circuit board 2210 to electrically connect facet locations 2220, For example _* wire traces 2230 may conne t to interconnectio pads 2250 of each facet location 2226 in order to electricall connect adjacent facet locations 2220, In some e bodi ents, facet locations 2220 are serially connected via wire traces 2230, For example, FIGURE 24 illustrates a serial data flow through flexible circuit board 2210* according to certain embodiments , In this example* each facet location 2220 is assigned a unique identifier [eg., ^; 1 _* - "2 ^ and so on) * and data flows serially through facet locations 2220 via wire traces 2230 as illustrated. In this manner _* each facet location 2220 may be addressed by a single processor or logic unit using its unique identifier. Any appropriate addressing scheme and data flow pattern may be used . [1171 FIGURE 25 illustrates a method 2300 of manufacturing an electronic assembly using flexible circuit boar 2210 of FIGOPi; 22, according to certain embodiments, At step 2510, a plurality of facet locations are formed on a flexible circuit board. In some embodiments , the facet locations are facet locations 222:0, and the flexible circuit board is flexible circuit board 2210, bach facet location corresponds to one of a plurality of sensor facets an one of a plurality of display facets. The sensor facets may be censor facets 3735, and the display facets may be display facets £665. In some em odiment , the plurality of facet locations are arranged into a plurality of facet columns sued as column 2201. In some embodiments, the plurality of facet locations are additionally or alternatively arranged into a plurality of facet rams such as rows 2202,

[115] At step £520, the flexible circuit board of step 2510 is cut: or otherwise shaped into a pattern that permits the flexible circuit board to be later formed into a 3D shape such as a spherical o se ispherical shape. When the flexible circuit board is fiat, at least some of the facet locations are separated from one or more adjacent facet locations by a plurality of gaps such as gaps 2215. When the flexible circuit board is rented into the 3D shape, the plurality of gaps sire substantially eliminated,

[113] At step 2530, the electronic: assembly is assembled b coupling a first plurality of rigid facets to a first side of the fiemibie circuit board. The first plurality of rigid facets may be sensor facets 3735 or display facets £665, Each rigid facet is coupled to a respective one of the facet locations. In some embodiments, the first plurality of rigid facets are coupled to connection pads on the first side of the flexible circuit board using patterned conductive and nonceno ctive adhesives ,

i[120] In some embodimenta , the first plurality of rigid facets of step 2330 are rigid sensor facets such as sensor facet 3735, and method 2500 further includes coupling a plurality of rigid display facets such as display facet 2665 to a second side of the flexible circuit board that is opposite the first side. In this case, each particular facet location is configured to transmit igns is between a particular rigid sensor facet electrically coupled to the particular facet location and a particular rigid display facet electrically coupled to the same particular facet location. This permits light to be displayed from the particular rigid display facet tha corresponds to light captured by the corresponding rigid sensor facet,

[121] At step 2540, the assembled electronic assembly is formed into the desired 3D shape. In some embodiments, this step involves placing the flexible circuit board with its coupled ri id facets into one side of a rigid ca ing that: is in the desired shape. This allows the rigid facets to fall into defined spaces in the caning and the flexible circuit: board to bend at defined: creases /gaps between the rigid facets. After placing the flexible circuit board with its coupled rigid facets into one side of the rigid casing, an opposite matching side of the rigid casing may be attached to the first side, thereby sealing the assembly into the desired shape .

iI22] Particular embodiments may repeat one or more steps of method 2500, where appropriate. Although this disclosure describes and illustrates particular steps of method 2500 as occurring in a particular order, this disclos re contompiai sc any suitable steps of sethod 2500 occurring in any suitable order (e,g,, any temporal orders, Morsos&r, although this disclosure describes and illustrates an example method of manufacturing art electronic assembly using flexible circuit board, this disclosure contemplates any suitable netted of manufacturing an electronic assembly using flexible circuit board, which may include ail _/ some, or none of the steps of method 2500, where appropriate. Furthermore, although this disclosure describes and illustrates particular components, devices, or systems carrying out particular steps of method 2500, this disclosure contemplates any suitablecombination of any suitable components, devices, or systems carrying out any suitable steps of method 2500,

[123] FIGURES 26-36 illustrate distributed multi—screen arrays for high density displays, according to certain embodiments. In general, to provide a near-eye display capable of emulating the entire visual field of a single human eye, a high dynamic range image display with a resolution orders of magnitude greater chan current common displayscreens is required. Such displays should be able to provide a light field display with enough angular and spatial resolution to accommodate 20/20 hitman visual acuity. This is an enormous amount of information, equating to a total horizontal pixel count of 10 OK to 20OK. These displays should also wrap around the entire field of vision of one human eye ( approximately 160 ^” horizontally and 130 ^” vertically), For rendering binocular vision, a pair of such displays spanning the entirety of a curved surface around each eye would be necessary. Typical displays available today, however, are unable to meet these requirements. [124] To address these and other limitations of currentdisplays, amooeinen lx of the disclosure provide as array of small, high-resolution micro displays display facets

2565) of custom sizes and shapes _j all of which are formed and then assembled on a la ger _; flexible circuit board 2210 that may be formed into a 3D shape : e . g . , a semispher leal surface) - The micro displays may be mounted to the interior side of serai spherical circuitry, where another layer containing an array of TFT logic units [o · . , logic units 755) may be included to handle all the powe and signal management . Typically, one logic unit 755 may be ncluded for each micro display. Each micro display operates as a discreet unit _; displaying: data from the logic unit behind it, Any additional information (e,g, _f such as or ter ns i video for AR, ¾'R, or DR applications) may be passed to the entire array via a central control processor. In seise embodiments _; the external data signal progresses serially from one micro display to the next as a packed multiplex stream _; while the TFT logic unit for each display determines the source and section of the signal to read. This allows each unit to act independently of any other displ y _; providing a large array of many high-resolution displays with unique content or; each _; such that the whole assembly together forms essentially a single ax:: rarely high- resolution display ,

[125] To fulfill the requirements of resolution; color clarity, and luminance output, each micro display may have a unique, high performance pixel architecture , For example, each micro display screes may include arrays of display pixels 100 as described in FIGURES l-'; and their associated descriptions in U,S, Patent Application Fo , 15/724,000 entitled "Shacked Transparent Pixel Structures for Electronic Displays; ^'v which is incorporated. herein by reference in its entirety, The micro display screens cay be assembled on the same substrate using any appropriate method. Such simultaneous manufactu ing using standard semiconductor layering and photolithographic processes virtually eliminates the overhead and costs associated with production and packaging of cany individual screens- greatly improving affordability-

[126] FIGURE 26 illustrates a cut-away view of a curved multi-display array 2600,. according to certain embodiments . FIGURE 26 is essentially the back side of flexible circuit board 221016 of FIGURE 22 with the addition of logic facets 2655 and display facets 2665 coupled to flexible circuit board221OB at facet locations 2220, In general- each logic facet 2655 Is an individual logic unit 755 from logic unit layer 75:0 - Similarly _; each display facet 2665 is ah Individual display unit 765 from display layer 7SQ coupled with a portion of microlens array 720.

[127] In some embodiments _f each individual logic facet 2655 Is coupled to flexible circuit board 2210.- and each individual display facet 2665 is then coupled to one of the logic facets 2655, In other embodiments _; each logic facet: 2655 is first coupled one of the display facets 2665. _< and the combined facet is then coupled to flexible circuit board 2210, In such embodiments - the combined logic facet 2655 and display facet 2665 may be referred to as a display facet 2665 for simplicity , hs used herein _:.· "display facet" may refer to both embodiments : · . o .... an individual display facet 2665 or a combination of display facet 26:65 with a logic facet 2655} -

[1281 In general _; each display facet 2665 can b individually addressed (e.g, _? by a central control processor not pictured) _; and a collection of display facets 2665 may represent a dynamic, heterogeneous collect ion forming a singular collective,. In other words, multi-display array 26GD provides a tiled electronic display system showing imagery through individual display facets 2165 that together form a complete whole. Each individual display facet 2665 is capable of providing multiple different display resolutions and can be customized on the fly to run a different resolution, color range, frame rate, etc. For scampi e , one display facet 2665 may have a 512x512 display resolution while an adjacent display facet 2665 (of equal size; has a 128x128 display reso ution, wherein the former represents a higher concentration of imagery data. In this example, these two displays are heterogeneous, but are individually controllable and wort in unison to form a singular display image,

[129] The overall collection of display facets 2665 can follow any curved or flat surface structure, for example, display facets 2665 may on formed into a semispherical surface, a cylindrical surface, an oblong spherical surface, or any other shaped surface,

1130] Logic facets 2655 and display facet 2665 may be in any appropriate shape, in some embodiments, the shapes of logic facets 2655 and display facets 2665 match each other and the shape of facet locations 2220. in some embodiments, logic facets 2655 and display facets 2665 are in the shape of a polygon such as a triangle, a quadrilateral, a pentagon, a hexagon, a heptagon, or an octagon. In some embodiments, some or ail of logic facets 2655 and display facets 2665 have non- polygonal shapes . For example, display facets 2665 on the edges of flexible circuit board 2210 may not be polygonal as they may have curved cutoffs so as to enhance the aesthetic of the overall assemb1 [131] In -addition to having a selectable/ controllable display resolution _; each display facet 2665 cay in some embo iments also have a selectable color range from a plurality of color ranges and/or a selectable frare rate from a plurality of frame rates. In such embedment s , the display facets 2665 of a particular flegible circuit board 2210 are configurable to provide heterogeneous frame rates and heterogeneous color range. For exam le, one display facet 2665 may have a particular color range chile another display facet 2665 has a different color range. Similarly _; one display facet 2665 may have a particular frame rate while another display facet 2665 has a different frame rate.

[152] FIGURE 27 illustrates an exploded vies? of the curved multi-display array 2600 of FIGURE 26 _; and FIGURES 28- 29 illustrate additional details of logic facet 2655 and display facet 2665 _; according to certain embodiments . As illustrated in these figures, each logic facet 2655 may include interconnections pads 2850 that may be electrically coupled to interconnection pads 2250 of adjacent logic facets 2655. This may enable display facets 2665 to be serially coupled via wire traces 2230. In addition, each logic facet. 2655 may include pads 2840 in a pattern that matches pads 2940 on the fcaob side of display facet 2665, This permits logic facet 2655 and display facet 2665 to be coupled together using any appropriate technique in the art.. In some embodiments, pads 2840 and pads 2340 are EGA pads or any other appropriate surface-mounting pads .

[133] ElGUESS 30 and 32 illustrate a back side of flexible circuit board 2210 of FIGURE 22, and show similar details as described in reference to FIGURE 23, PIGOBFS 31 and 33 illustrate a serial data flow through flexible circuit board 221D, and show? similar details as described ib reierence to FIGURE 24. FIGURE 34 illustrates an array or logic facets 2655 that hare been formed into a semispherical shape , according to certain embodiments. In this figure, flexible circuit board 2210 and display facet 2665 have been removed for clarity, FIGURE 35 illustrates ccxmaunications between the logic facets 2655 of FIGURE 34, according to certain embodiments. As illustrated in this figure, each logic facet 2 _: 655 may communicate with ad acent logic facets 2655 using interconnections pads 2850, In addition, each logic facet 2655 may have a unique identification as illustrated in FIGURE 35. This permits each logic facet 2655 to be uniquely addressed by, for example, a central processing unit.

[134] FIGURE 36 Illustrates a method 3600 of manufacturing the curved multi -display array of FIGURE 26, dccoruing to certain embodiments , Method 3600 may begin in step 3610 where a plurality of facet loca 11on s are formed on a circuit board. In core embodiments, the facet locations are facet locations 2220 and the circuit board is flexible circuit board 2210, In seem c _? sOon :.menis , each facet location corresponds to one of a plurality of display facets such as display facets 2665,

[1354 At step 3620, the flexible circuit board is ou or otherwise formed Into a pastern that permits the fieri ore circuit board to be later formed into a 3D shape. When the flexible circuit board is fiat, at least some of the facet locations are separated from one or more adjacent facet locations by a plurality of gaps such as gaps 2215, When the flexible circuit board is formed into the 3D shape, the plurality of gaps are substantially eliminated. [136] At step 3¾30 _f a plurality of logic facets are coupled to a first side of the flexible circuit board:. Each logic facet is coupled to a respective one of the facet location:.? of step 3310. At step 3/6-0, a plurality of display facets are coupled to a respect im one of the plurality of logic facets of step 3630, In alternate embodiments the display facets may be nounred to the logic facets of step 3630 at the wafer love! prior to coupling the logic facets to the first side of the flexible circuit board. At step 3650 the aa seel·loo electronic display assembly is forced into the 3D shape. In some embodiments, this step may be similar to step 2540 of method 2500 described above . After step 3630 _; method 3600 m y end,

[137] Particular embodiments may repeat one or more steps of method. 3600; where appropriate. Although this disclosure describes and illustrates particular steps of metho 3600 as occurring in a particular or er this disclosure cord:ore;.[.aten any suitable steps of method 3600 occurring in any suitable order [e,g,, any temporal order;. Moreover _; although this disclosure describes and illustrates an example method of manufacturing a curved xnulti-di splay arrayr this disclosure contemplates any suitable method of manufacturing a curved multi-display array, which may include all, some, or none of the steps of method 3600, where appropriate. Furthermore, although this disclosure describes and illustrates particular components, devices, or systems carrying out particular steps of method 3600, this disclosure contemplates any suitable combination of any suitable components, devices or systems: carrying out any suitable steps of method 36Q0, :G 138 ] IGURES 37-42 illustrate a distributed multi- aperture amera array 3700, according to certain embodiments. In general, to capture the lull light field of the entire visual field of a single human eye _: < large, high dynamic range image sensor cl. th a resolution much higher than currently available is needed. Such an image sensor mould enable a light field camera with enough angular and spatial resolution to accommodate 20/2:0 human visual acuity. This is an enormous amount of information equating to a total horizontal pixel count of 100K to 30OK. This multi-aperture image sensor must also wrap around the entire field of vision of one human eye (approximately 16th horizontally and 130" ^' vertically! - For imaging binocular vision, a pair of such cameras scanning the entirety of a curved surface around each eye are necessary. Typical image censor assemblies available today are unable to meet these requirements.

[133] To overcome these and other limitations of typical image sensors, embodiments of the disclosure provide an array of small image sensors of custom sines and shapes, ail of which are assembled on a larger, flexible circuit board 2210 that is formed to a 3D (e.g,, semi-spherical ) shape . The image sensors (e.g., sensor facets: 3735; are mounted to the exterior side of flexible circuit board 2:210, where another layer containing an array of TFT logic units {e.g,, logic units 755; may be provided to handle all the power and signal management — one logic unit for each display. Each image sensor operates as a discrete unit passing readout data to the logic unit behind it (in embodiments that include logic units), where it is handled and routed accordingly (e.g., to a corresponding display facet 2565 in some embodiments ) _{< "} this allows eaen sensor facet 5755 to act independently of any other sensor facet 373:5 _; providing a large array of many apertures capturing unique content on each,· such that thewhole assembly essentially becomes a seamless, very high reso U:C ion. _; multi-node camera , it should be noted that while image sensors nay pass date to their paired logic units in some embodiments, the functionality of the image sensors themselves do not necessarily require logic unit coupling _*

[If 0] To fulfill the requirements of resolution, sector clarity _f and luminance output, each micro sensor may have a unique, high per termacce pixel architecture, her aaample, each micro sensor nay include array of sensor pixels 18GG as described in FIGURES 18-20 an their associated descriptions in U.S. Patent application do, 15/724; 027 entitled "Stacked Transparent Pixel Structures fo Image Sensors," which is incorporated herein by reference in its entirety _* The micro sensor may be assembled on the same substrate using any appropriate method. Such simultaneous manufacturing using standard semiconductor layering and photolithographic processes virtually eliminates the overhead and costs associated with production and packaging of many individual screens, greatly improvin affordability,

[liij Another characte is ic of certain endedamenta of distributed multi-aperture camera array 3700 is built-in depth perception based o parallax between different piehoptic ceils, imagery produced by cells on opposite sides of a given sensor may be used to calculate the offset of image detail, where offset distance directly correlates with proximity of the detail to the sensor surface. This scene information may foe used by a central processor when overlaying any augmented video signai _* resulting in aS/Mh content placed in front of one viewer at the appropriate depth- The information can also be sed for a variety of artificial focus blurring and depth- aensing .asks, including hi u fated depth of field _» spatial edge detection, and other vr aoa ;. effects,

[142] FIGORS 37 illustrates a cut-away view of distributed multi-aperture camera array 3700, according to certain embodiments , FIGURE 37 is essentially the flexible circuit board 2210B of FIGURE 22 with the addition of sensor facet 3735 coupled to flexible circuit board 221GB at facet locations 2220:. In some embodiments, each sensor facet. 3735 is an individual sensor unit 735 from image sensor layer 730,

[143] In some embodiment , each individual sensor facet 3733 Is coupled to flexible ci cuit board 2210. In other embodiments, each individual senso facet 3735 is coupled to one of the logic facets 2655 that has been coup.led to flexible circuit board 3210. In other embodiments, each logic facet 2655 is first coupled one of the sensor facets 3735, and the combined facet is then coupled to flexible circuit board 2210. In such o:o,od · rents , the combined logic facet 2655 and sensor facet 3735 noy be referred to as a sensor facet 3735 for simplicity. As used herein, "sensor facet' ^' may refer to both embodiments (ire,, an individual sensor facet 3735 or a combination of a sensor facet 3735 uith a logic facet 2653 ; ,

[1441 In general. each sensor facet 3735 can be individually addressed re , g , , b a central control processor not pictured) , and a collection of sensor facets 3735 may represent a dynamic, heterogeneous collection forming a singular collective. In other words, distributed multi" aperture camera array 3700 provides a tiled electronic sensor system providing imagery captured through individual sensor facets 3735 that together for a complete whole. Each individual sensor facets 3735 is capable of capturing images: at multiple different resolutions and can he customised on the fly to capture a different rescindion, _· color range, frame rate, etc. For eraapl e , one sensor facet 3735 may have a

512x512 capture resolution utile an adjacent sensor facet 3735 (of equal site] has a 128x128 capture resolution, wherein the former represents a higher concentration of .imagery data. In this example, these too: sensors are heterogeneous; but are individually controllable and work in unison to capture a singular light field,

1145] The ove all coil oof ion of sensor facets 3735 cart follow any curved or fiat surface structure. For example, sensor facets 3735 may fce formed into a semispherical surface, a cylindrical surface, an oblong spherical surface, or any othe shaped surface,

[146] Sensor facets 3735 may be in any appropriate shape. In some embodiments , _· the shapes of sensor facets 3735 match the shapes of display facets 2665 and the shape of facet locations 2220, In sore embodiments, sensor facets 3735 are in the shape of a polygon such as a triangle a quadrilateral _; a pentagon, a hexagon, a heptagon _; or an octagon. In some embodiments, some or all of sensor facets 3:735 nave non-polygonal shapes. For exa p e sensor facets 3735 on the edges of flexible circuit board 2215 may not be polygonal as they may have curved cutoffs so as to enhance the aesthetic of the overaI i aasambly .

[1471 In addition to having selectafcle/Gonfcroiiabie resolution, each sensor facets 3735 may in some embodiments also have a selectable color range from a plurality of color ranges and/or a selectable frame rate from pluralit of frame rates. In such embodiments, tire sensor facets 3735 of a particular flexible circuit beard 2210 are configurable to provide heterogeneous frame rates and heterogeneous color range . For example, one sensor facet 3735 ray have a particular color range while a nother sensor facet 3735 has a different color range. Similarly, one sensor facet 3735 rtay have a particular frame rate chile another sensor facet 3735 has a different frame rate.

148] FIGURES 38-39 illustrate exploded vises of the distributed mufti-aperture camera array 3700 of FIGURE 37, according to certain anted! rents . As illustrated in these figures, each sensor facet 3735 cay include pads 3340 in a pattern that catches pads 2243 on flexible circuit board 2210 or pads 2310 on io ic facet 2655. This permits sensor facet 3735 to be coupled to logic facet 2055 or flexible circuit board 2210 using any appropriate technique in the art. In some embodiments , pads 3340 are BGA pads or any other appropriate su face-counting pads. FIGURES 40-40 illustrate similar views of flexible circuit board 2210 as sheen in FIGURES 23-24, except that flexible circuit board 2210 has been formed into a 30 shape.

[149] FIGURE 42 illustrates a retted 4200 of canufacturing distributed culti-apertare camera array 3700, according to certain echedimehta . Elethod 4200 cay begin in step 4210 chore a plurality of facet locations are forced an a circuit board. In some embodiments, the facet locations are facet locations 2220 and the circuit board is flexible circuit beard 2210. In some embodiments, each facet incur : or: oorresponds to one of a plurality of sensor facets such as sensor facers 3735.

[153] At step 4220, the flexible circuit board is out or otherwise forced Into a pattern that permits the flexible circuit board to be later forced into a 3D shape. When the flexible circuit board is flat, at least sore of the facet locations are separated fret· one or -no re adjacent facet locations by a plurality of gaps such as caps 2215, When the flexible circuit board is formed into the 3D shape, the plurality of gaps are substantially eliminated -

[Idly at step 4230, a plurality of sensor facets are coupled to a first side of the flexible circuit board, each sensor facet is coupled to a respective one of the facet locations of step 4210, of step 4240, the assembled electronic camera assembly s formed into the 3D shape. In some embodiments, this step may be similar to step 2540 of method 2500 described above. After ste 4240, metho 4200 may end ,

[15241 Particular embodiments may repeat one cr more steps of method 4200, whe e appropriate. Although this disclosure describes and illustrates particular steps cf method 4200 _: as occurring in a particular order, this disclosure contemplates any suitable steps of method 4200 occurring is. any suitable order (e,g., any temporal order).

Moreover, although this disclosure describes and illustrates an example method of manufacturing a distributed multi- aperture camera array, this disclosure contemplates -any suitable method of manufacturing a distributed multi-aperture camera array, which may include all, some, or none of the steps of method 4200, where appropriate . Furthermore, although this disclosure describes and illustrates particular components, devices, or systems carrying out particular steps of method 4200, this disclosure eonten-plates any suitable combination of any suitable components, devices, or systems carrying out any suitable steps of method 4200. [153] Herein, ^' 'or' ^'' is inclusive and not exclusive, unless expressly indicated otherwise or indicated otherwise by context. Therefore, herein, "¾ or B" means "1 , B, or both," unless expressly indicated otherwise or indicated otherwise by context. Moreover, "and" is both joint and several, unless expressly indicated otherwise or indicated otherwise by context. Therefore, herein, "A and B ^:f tea ns "A and B, jointly or severally, " unless expressly indicated otherwise or indicated otherwise by context,

rioij The scope of this disclosure encompasses all chances, substitutions, variations, alterations, and nodi float ions to the example embodiments described or illustrated herein that a person having ordinary skill in the art would comprehend. The scope of this disclosure is not limited to the example embodiments described or illustrated herein. Moreover, although this disclosure describes and illustrates respective embodiments herein as including particular components, elements, functions, operations, or steps, any of these embodiments may include any combination or permutat ion of any of the commoner;·: s , elements, functions , operations, or steps described or illustrated anywhere herein that a person having ordinary skill in the art would comprehend. Furthermore, reference in the appended claims to an apparatus or system or a component of an apparatus or system being adapted to, arranged to, capable of, configured to, enabled to, operable to, or operative to perform a particn.nl a r function encompasses that apparatus, system, component, whether or not it or that particular function is activated, turned on, or unlocked, as long as tha apparatus, system, or component is so adapted, arranged, capable, configured, enabled, operable, or operative. f 15:5 ] Although this disclosure describes and illustrates respective embed; cores herein as inc.Lading particular components, clement;·:, functions, opera tiers, or steps , any of these embodiments pay include any combination or pe ro ratoon of any of the components, elements, functions, operations, _· or steps escribed or illustrated anywhere herein that a person having ordinary skill in the art sou.; d comprehend,

[156] Furthermore, reference in the appended claims to an apparatus or system ox a component of an apparatus or system being adapted to, arranged to, capable of, configured to, enabled to, operable to, or operative to perform a particular function encompasses that apparatus, system, componen , whether o not it or that particular function is activated, turned on, or unlocked, as long as that apparatus, system, or component is so adapted, arranged, capable, configured, enabled, operable, or operative.