Title:
DMOS TRANSISTOR HAVING A TRENCH GATE ELECTRODE AND METHOD OF MAKING THE SAME
Document Type and Number:
WIPO Patent Application WO2001071817
Kind Code:
A9
Abstract:
A trench DMOS transistor cell (110) is provided, which is formed on a substrate (111) of a first conductivity type. A body region (115a, 115b), which has a second conductivity type, is located on the substrate. At least one trench extends through the body region and the substrate. An insulating layer (117) lines the trench. The insulating layer includes first (125) and second (127) portions that contact one another at an interface (129). The first portion of the insulating layer has a layer thickness greater than the second portion. The interface is located at a depth above a lower boundary (133) of the body region. A conductive electrode (118) is formed in the trench so that it overlies the insulating layer. A source region (116b, 116c) of the first conductivity type is formed in the body region adjacent to the trench.
Inventors:
HSHIEH FWU-IUAN
SO KOON CHONG
TSUI YAN MAN
SO KOON CHONG
TSUI YAN MAN
Application Number:
PCT/US2001/040310
Publication Date:
February 06, 2003
Filing Date:
March 16, 2001
Export Citation:
Assignee:
GEN SEMICONDUCTOR INC (US)
International Classes:
H01L29/78; H01L29/423; H01L29/49; (IPC1-7): H01L29/78; H01L29/423; H01L21/336
Download PDF:
Previous Patent: FERROELECTRIC FET WITH POLYCRYSTALLINE CRYSTALLOGRAPHICALLY ORIENTED FERROELECTRIC MATERIAL
Next Patent: SURFACE PIN DEVICE
Next Patent: SURFACE PIN DEVICE