Title:
DUTY CYCLE ADJUSTER
Document Type and Number:
WIPO Patent Application WO/2024/016951
Kind Code:
A1
Abstract:
The present invention relates to a duty cycle adjuster, comprising: a first duty cycle adjustment (DCA) module, wherein the first DCA module comprises M adjustment units, which are connected in parallel, each adjustment unit comprises an NOR gate and a PMOS transistor, and each adjustment unit is configured in such a way that: a timing delay which is inputted into the NOR gate and is converted from a low level into a high level causes the PMOS to be turned on at a rising edge of a signal, so that the PMOS delays the rising edge of the signal to reduce the duty cycle of the signal; and a timing delay which is inputted into the NOR gate and is converted from a high level into a low level causes the PMOS to not be turned on at a falling edge of the signal, so that the PMOS does not change the falling edge of the signal.
Inventors:
LAI JUNGCHIN (CN)
Application Number:
PCT/CN2023/102563
Publication Date:
January 25, 2024
Filing Date:
June 27, 2023
Export Citation:
Assignee:
DOSILICON CO LTD (CN)
International Classes:
H03L7/08; H03K3/017
Foreign References:
| CN115001454A | 2022-09-02 | |||
| CN106357238A | 2017-01-25 | |||
| CN210246717U | 2020-04-03 | |||
| US20150358001A1 | 2015-12-10 |
Attorney, Agent or Firm:
SHANGHAI PATENT & TRADEMARK LAW OFFICE, LLC (CN)
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