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Title:
EDGE ADDITION-BASED CLOCK DELAY ADJUSTMENT CIRCUIT AND INTEGRATED CHIP THEREOF
Document Type and Number:
WIPO Patent Application WO/2016/041229
Kind Code:
A1
Abstract:
Provided are an edge addition-based clock delay adjustment circuit and integrated chip thereof, the clock delay adjustment circuit comprising a clock delay unit (1) used to delay at equal intervals clock signals inputted at an input end thereof, so as to obtain and output at least three clock signals delayed at equal intervals; a weighting coefficient unit (2) used to generate, according to digital codes inputted at an input end thereof, a number of weighting signals equal to the number of delayed clock signals and output the weighting signals; an edge addition unit (3) used to receive the delayed clock signals and the weighting signals, and perform a weighted addition of the delayed clock signals according to the weighting signals and output the delayed clock signals, so as to obtain new clock signals having the same number of consecutive clock rising/falling edges as the delayed clock signals. In addition, the clock delay adjustment circuit can also be made into an integrated chip. The present invention appropriately solves the problem of an existing clock delay adjustment circuit in which high-precision time-division sampling requirements cannot be met due to low adjustment precision.

Inventors:
HU RONGBIN (CN)
ZHU CAN (CN)
WANG YONGLU (CN)
ZHANG ZHENGPING (CN)
ZHANG LEI (CN)
GAO YUHAN (CN)
YE RONGKE (CN)
CHEN GUANGBING (CN)
WANG YUXIN (CN)
FU DONGBING (CN)
Application Number:
PCT/CN2014/088913
Publication Date:
March 24, 2016
Filing Date:
October 20, 2014
Export Citation:
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Assignee:
NO 24 RES INST OF CHINA ELECTRONIC TECHNOLOGY CORP (CN)
International Classes:
H03K5/13
Foreign References:
CN103970180A2014-08-06
CN102420649A2012-04-18
CN1192275A1998-09-02
CN102246415A2011-11-16
CN1573346A2005-02-02
Attorney, Agent or Firm:
J.Z.M.C. PATENT AND TRADEMARK LAW OFFICE (CN)
上海光华专利事务所 (CN)
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