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Title:
EMBEDDED COMPONENT SUBSTRATE AND SUBSTRATE FLAW DETECTION METHOD
Document Type and Number:
WIPO Patent Application WO/2016/035630
Kind Code:
A1
Abstract:
Provided are an embedded component substrate and a substrate flaw detection method with which internal structures can be inspected precisely and non-destructively from the side on which a planar conductor is provided, even when the planar conductor is provided so as to cover an embedded component. The embedded component substrate (1) is equipped with: a laminated body (2) formed by laminating a plurality of insulating layers (21-26); an embedded component embedded in the laminated body (2); and planar conductors (14, 15) provided in the laminated body (2) so as to overlap the embedded component (3) on one side in the lamination direction with respect to the embedded component (3). The planar conductors (14, 15) are provided with a plurality of apertures (16) arranged so as to overlap the embedded component (3) in substantially the entire region in which the embedded component is located, when viewed in the lamination direction.

Inventors:
TAGO SHIGERU (JP)
SHINAGAWA HIROFUMI (JP)
ADACHI TOSHIRO (JP)
Application Number:
PCT/JP2015/073952
Publication Date:
March 10, 2016
Filing Date:
August 26, 2015
Export Citation:
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Assignee:
MURATA MANUFACTURING CO (JP)
International Classes:
H05K3/46; G01N29/04; H01L23/00; H01L23/12; H05K3/00
Foreign References:
JP2014107515A2014-06-09
JP2002324979A2002-11-08
JPH11112142A1999-04-23
JP2008153693A2008-07-03
JP2004274035A2004-09-30
JP2012195468A2012-10-11
JPH04207099A1992-07-29
Attorney, Agent or Firm:
Kaede Patent Attorneys' Office (JP)
Patent business corporation Kaede Patent Attorneys' Office (JP)
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