Title:
EPITAXIAL SUBSTRATE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD
Document Type and Number:
WIPO Patent Application WO/2017/158747
Kind Code:
A1
Abstract:
To provide an epitaxial substrate manufacturing method wherein substrate breakage from an epitaxial substrate outer peripheral end portion can be suppressed.
The present invention discloses a process for manufacturing an epitaxial substrate wherein an epitaxially grown layer is formed on a cut bulk substrate formed by cutting a semiconductor single crystal. A cut surface of the bulk substrate is polished after being cut, epitaxial growth is performed in a state wherein an wafer outer peripheral end portion formed by the polishing is maintained, then chamfering of a substrate outer periphery is performed, thereby planarizing an interface between the epitaxial layer and the bulk substrate, said interface being at a substrate outer peripheral end portion, suppressing nonconformity of grinding rates at the time of removing the bulk substrate by grinding, and suppressing substrate breakage.
Inventors:
WATANABE NAOKI (JP)
YOSHIMOTO HIROYUKI (JP)
YAMADA RENICHI (JP)
YOSHIMOTO HIROYUKI (JP)
YAMADA RENICHI (JP)
Application Number:
PCT/JP2016/058239
Publication Date:
September 21, 2017
Filing Date:
March 16, 2016
Export Citation:
Assignee:
HITACHI LTD (JP)
International Classes:
H01L21/205; H01L21/304
Domestic Patent References:
| WO2014125844A1 | 2014-08-21 | |||
| WO2008078401A1 | 2008-07-03 | |||
| WO2016030963A1 | 2016-03-03 |
Foreign References:
| JPH01201922A | 1989-08-14 | |||
| JP2012253115A | 2012-12-20 | |||
| JP2012195539A | 2012-10-11 | |||
| JP2012151323A | 2012-08-09 | |||
| JP2010529646A | 2010-08-26 |
Attorney, Agent or Firm:
SEIRYO I.P.C. (JP)
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