Title:
EXAMINATION CIRCUIT AND SEMICONDUCTOR EXAMINATION DEVICE
Document Type and Number:
WIPO Patent Application WO/2023/218973
Kind Code:
A1
Abstract:
This examination circuit has: a counter that generates a delay at cyclic intervals in a master clock; a delay circuit that generates, in a signal from the counter, a delay at a temporal resolution finer than that of the cycle in the master clock; a signal generation circuit that generates a signal on the basis of a pattern signal and a signal from the delay circuit; a timing calibration circuit that derives an amount of fluctuation in a timing; and an adder that adds the amount of fluctuation to a timing setting value read out from a memory in which timing information is stored according to a timing control signal included in the pattern signal and outputs control signals for the counter and the delay circuit.
Inventors:
HAYASHI YOSHIHIKO (JP)
Application Number:
PCT/JP2023/016550
Publication Date:
November 16, 2023
Filing Date:
April 26, 2023
Export Citation:
Assignee:
V TECH CO LTD (JP)
International Classes:
G01R31/3183; G01R31/319
Foreign References:
| JPH0580126A | 1993-04-02 | |||
| JPS63298076A | 1988-12-05 | |||
| JPH03186010A | 1991-08-14 | |||
| JPH0651027A | 1994-02-25 | |||
| JPS5832178A | 1983-02-25 | |||
| JP2000206212A | 2000-07-28 | |||
| US20020077763A1 | 2002-06-20 |
Attorney, Agent or Firm:
EIKOH, P.C. (JP)
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