FIELD EFFECT TRANSISTOR AND METHOD OF PRODUCING THE SAME

Technical Field

The present invention relates to a field effect transistor and a method of producing the same. Background Art

In recent years, due to progress in liquid crystal and electroluminescence technology, flat panel displays (FPDs) have been practically implemented. In particular, since an organic electroluminescent device (organic EL device) employs a thin film material that emits a bright light at a low voltage when excited by applying a current thereto, the organic EL device has shown promise in the fields of cellular phone displays, personal digital assistants (PDAs), computer displays, information displays for automobiles and TV monitors, and also in the wider field of general illumination devices or the like, in terms of reducing the thickness, weight, size or energy consumption of the devices in these fields.

An FPD is driven by an active matrix circuit of a field effect transistor (TFT), which has an active layer of amorphous silicon or polycrystal silicon formed on a glass substrate.

Attempts have been made to use a light, flexible resin substrate instead of a glass substrate with the intention of further reducing the thickness or weight of the FPDs or improving the anti-breakage properties of the same. However, since the production of a transistor using the aforementioned silicon film requires a heat treatment at a relatively high temperature, it is generally difficult to form the transistor directly on a resin substrate, which has a low heat-resistance. In view of this, TFTs using an amorphous semiconductor that can be formed into a film at low temperature have been actively developed. Amorphous oxide semiconductors, which can be formed into a film at room temperature and can be formed on a resin film, have been attracting attention as a material for an active layer of TFTs.

However, since the active layer formed from an amorphous oxide semiconductor is prone to degradation due to moisture, oxygen or the like, the obtained TFT using this active layer may not operate in a stable manner. Further, there is a possibility of damaging the TFTs during the production thereof due to the susceptibility of amorphous oxide semiconductor to chemical changes, as well as plasma or UV rays. In order to address this problem, provision of a protection film to the active layer formed from amorphous oxide semiconductor in order to improve the reliability of the obtained TFTs has been proposed.

For example, Japanese Patent Application Laid-Open (JP-A) No. 2007-73705 proposes a technique of covering an oxide semiconductor channel layer that serves as an active layer with a protection layer. In this technique, a metal oxide film including at least one kind of metal is used as the protection layer.

JP-A No. 2008-218495 proposes a technique of increasing the carrier concentration of an amorphous oxide semiconductor layer at the gate electrode side compared to the carrier concentration at the protection layer side, and limiting the thickness of the amorphous oxide semiconductor layer to a range of 30 nm ± 15 run. In order to adjust the carrier concentration of the active layer, the mixing ratio O /Ar of a sputtering film-formation gas is increased (up to a range of 20% to 50%, specifically) during the process of forming the protection layer.

JP-A No. 2008-166716 proposes a technique of suppressing damage to an active layer during the production thereof by providing a protection layer to the active layer, the protection layer including a desorbed gas that is observed as oxygen atoms in thermal desorption spectroscopy in an amount of 3.8 x 10 ¹⁹ /cm ³ .

According to this technique, however, although the protection layer serves to suppress damages to the active layer due to moisture or oxygen, an increase in a threshold-voltage shift may be caused by the protection layer.

In view of the aforementioned circumstances, the invention aims to provide a field effect transistor that has an active layer including an amorphous oxide in which the effects of moisture or oxygen on the active layer are suppressed, and a method of producing a field effect transistor.

Specifically, the inventors have found that by providing a protection layer so as to cover at least a portion of an active layer between a source electrode and a drain electrode, the protection layer having a greater band gap than that of the active layer, effects of moisture or oxygen on the active layer can be suppressed, and unfavorable threshold- voltage shift can be remarkably improved. Summary of the Invention

In view of the above circumstances, an aspect of the present invention provides a field effect transistor including a substrate, a gate electrode, a gate insulation film, an active layer including an amorphous oxide, a source electrode, a drain electrode, and a protection layer including an amorphous inorganic material, the protection layer being provided so as to cover at least a portion of the active layer that corresponds to an area between the source electrode and the drain electrode, and the protection layer having a band gap that is greater than the band gap of the active layer. Brief Description of Drawings

Exemplary embodiments of the present invention will be described in detail based on the following figures, wherein:

Fig. 1 is a schematic view of an exemplary structure of the field effect transistor according to the invention;

Fig. 2 is a schematic view of the field effect transistor of Fig. 1 from the direction A;

Fig. 3 is a schematic view of a further exemplary structure of the field effect transistor according to the invention;

Fig. 4 is a schematic view of a yet further exemplary structure of the field effect transistor according to the invention;

Fig. 5 is a schematic view of a still yet further exemplary structure of the field effect transistor according to the invention;

Fig. 6 is a diagram showing the relationship between the wavelength and the absorbance used in the measurement of band gap; and

Fig. 7 is a diagram showing how to calculate the amount of threshold- voltage shift. Description of Embodiment

In the following, one exemplary embodiment of the field effect transistor according to the invention and the method of producing the same are described by referring to the drawings.

As shown in Fig. 1, the field effect transistor 10 according to this exemplary embodiment at least includes, on substrate 12, gate electrode 14, gate insulation film 16, active layer 18, source electrode 2OA, drain electrode 2OB, and protection layer 24, in this order. As described later, active layer 18 functions as a channel layer in which electrons or holes move. In the present exemplary embodiment, field effect transistor 10 has a bottom-gate structure. Further, in the present exemplary embodiment, field effect transistor 10 has a top-contact structure hi which active layer 18 contacts source electrode 20A and drain electrode 2OB at the top side of active layer 18 (the side not facing substrate 12). However, field effect transistor 10 may have a bottom-contact structure (described later) in which active layer 18 contacts source electrode 2OA and drain electrode 2OB at the bottom side of active layer 18 (the side closer to substrate 12).

Field effect transistor 10 is an active device that has a function of switching a current that runs between source electrode 2OA and drain electrode 20B by controlling the current that ^• runs into active layer 18 by applying a voltage to gate electrode 14.

In field effect transistor 10 according to the present exemplary embodiment, protection layer 24 is positioned so as to cover at least a portion of active layer 18 that corresponds to an area between source electrode 2OA and drain electrode 2OB, and the band gap of protection layer 24 is greater than that of active layer 18.

The inventors have found that by providing protection layer 24 to field effect transistor 10, the protection layer having a band gap that is greater than that of active layer 18, damage to active layer 18 due to moisture or oxygen can be suppressed, and the threshold- voltage shift can be improved.

In the following, components of field effect transistor 10 according to the present exemplary embodiment and methods of producing the same are described.

Exemplary materials of substrate 12 of field effect transistor 10 include YSZ (zirconia stabilized yttrium), inorganic materials such as glass, and organic materials including polyesters such as polyethylene terephthalate, polybutylene phthalate and polyethylene naphthalate, polystyrene, polycarbonate, polyethersulfone, polyarylate, polyimide, polycycloolefin, norbornene resin, and poly(chlorotrifluoroethylene). When an organic material is used as the material for substrate 12, a material having favorable heat resistance, dimension stability, solvent resistance, insulation properties, processability, low air permeability, low hygroscopicity or the like is preferably selected.

Substrate 12 preferably has flexibility, and from this point of view, an organic plastic film formed from the aforementioned organic material is preferably used. When the insulation properties of substrate 12 is not sufficient, an insulation layer may be formed on substrate 12. It is also possible to further provide a layer such as a gas barrier layer that prevents transmission of moisture or oxygen, or an undercoat layer that improves flatness of the plastic film substrate or adhesiveness of the same to the active layer.

The thickness of substrate 12 is preferably from 50 μm to 500 μm. When the thickness of substrate 12 is less than 50 μm, it may be difficult to maintain a sufficient flatness of substrate 12 per se. When the thickness of substrate 12 is greater than 500 μm, it may be difficult to freely bend substrate 12 per se, i.e., the flexibility of substrate 12 per se may not be sufficient.

Exemplary materials for gate electrode 14 include metals such as Al, Mo, Cr, Ta, Ti, Au and Ag, alloys such as Al-Nd and APC, metal oxide conductive films of tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), indium zinc oxide (IZO) and the like, organic conductive compounds such as polyaniline, polythiophene and polypyrrole, and mixtures thereof.

The thickness of gate electrode 14 is preferably from 10 nm to 1000 nm, more preferably from 20 nm to 500 nm, further preferably from 40 nm to 100 nm, in view of securing a sufficient level of wiring resistance and covering the entire structure of the same with an insulation layer.

Gate insulation film 16 can be formed from an insulating material such as SiO ₂ , SiN _x , SiON, Al ₂ O ₃ , Y ₂ O ₃ , Ta ₂ O ₅ or HfO ₁ , or a mixed crystal including two or more of these compounds. Further, a polymeric insulating material such as polyimide may also be used for gate insulation film 16.

The thickness of gate insulation film 16 is preferably from 10 nm to 1000 nm, more preferably from 50 nm to 500 nm, and particularly preferably from 100 nm to 300 nm.

Gate insulation film 16 needs to have a certain degree of thickness in order to reduce the amount of leak currents and increase the resistance to a voltage. However, when the thickness of gate insulation film 16 is increased, the voltage for driving field effect transistor 10 is also increased. Therefore, the thickness of gate insulation film 16 is preferably within the above range.

A suitable method of forming gate insulation film 16 may be selected from a gas-phase method such as sputtering, pulse laser deposition, or electron beam deposition. However, the method is not limited thereto.

Active layer 18 includes an amorphous oxide semiconductor. This material can be formed into a film at low temperature, and is thus suitably used for forming an active layer on a flexible substrate.

Preferred amorphous oxide semiconductors for active layer 18 include those including at least one element selected from the group consisting of In, Sn, Zn and Cd; more preferably those including at least one element selected from the group consisting of In, Sn and Zn; and still more preferably those including at least one element selected from the group consisting of In and Zn.

Specific examples of the amorphous oxide for active layer 18 include In ₂ O ₃ , ZnO, SnO ₂ , CdO, indium-zinc-oxide (IZO), indium-tin-oxide (ITO), gallium-zinc-oxide (GZO), indium-gallium-oxide (IGO), and indium-gallium-zinc-oxide (IGZO).

In the present exemplary embodiment, active layer 18 has a band gap that is greater than that of protection layer 24 (described later).

The band gap is defined as a value of energy difference between the valence band (highest energy band occupied by electrons) and the conduction band (lowest energy band unoccupied by electrons), and is determined by an optical method (light-absorption spectrum). The light-absorption spectrum can be obtained by attaching an integrating sphere to a visible-ultraviolet spectrophotometer, and then measuring diffuse-reflectance spectra. In this exemplary embodiment, since light having a greater energy than the band gap is absorbed, the measurement is conducted by using the energy of light at the end of absorbance, i.e., the point at which the absorption starts, as the band gap.

As described above, active layer 18 has a band gap that is greater than that of protection layer 24, which is preferably from 2.5 eV to 4.0 eV, more preferably from 2.8 eV to 3.8 eV, particularly preferably from 3.0 eV to 3.5 eV. The band gap of active layer 18 can be adjusted by selecting the material that forms active layer 18. For example, the band gap of active layer formed from IGZO can be controlled by performing co-evaporation OfIn ₂ O ₃ (2.5 eV), ZnO (3.3 eV) and Ga ₂ O ₃ (4.6 eV). Specifically, the band gap of active layer 18 can be increased by increasing the ratio of Ga ₂ θ ₃ having the highest band gap (4.6 eV); and can be reduced by increasing the ratio OfIn ₂ O ₃ having the lowest band gap (2.5 eV).

The carrier concentration of active layer 18 is preferably equal to or greater than that of protection layer 24, from the viewpoint of supplying a sufficient amount of on-current that is necessary when active layer 18 is used in field effect transistor 10, and controlling the amount of the threshold- voltage shift. The carrier concentration of active layer 18 is not particularly limited, but is preferably as high as 1 x 10 ¹⁵ /cm ³ or more, more preferably from 1 x10 ¹⁵ /cm ³ to l ^χ lO ²¹ /cm ³ .

The methods of controlling the carrier concentration of active layer 18 include the following methods (1) to (4).

(1) Controlling the amount of oxygen defects

It is known that the conductivity of amorphous oxygen semiconductors is increased as the carrier concentration thereof is increased due to the presence of oxygen defects. Therefore, the carrier concentration of active layer 18 can be controlled by controlling the amount of oxygen defects in active layer 18. Specific methods of controlling the amount of oxygen defects of active layer 18 include a method of controlling the oxygen partial pressure during the formation of active layer 18, controlling the concentration of oxygen during a post-treatment after the formation of the layer, or controlling the time for the post-treatment. The post treatment may be conducted by using heat, oxygen plasma, UV ozone, or the like. Among these methods, a method of controlling the oxygen partial pressure during the formation of active layer 18 is preferred from the viewpoint of productivity.

(2) Controlling the composition ratio

The carrier concentration of active layer 18 can be changed by changing the metal composition ratio of the amorphous oxide semiconductor in active layer 18. For example, when IGZO is used for active layer 18, the carrier concentration thereof can be increased by increasing the ratio of In, or can be reduced by increasing the ratio of Ga.

Specific methods of changing the composition of active layer 18 include, in the case of employing a sputtering method, adjusting the composition ratio of active layer 18 by using targets having different composition ratios, or by performing co-sputtering using two or more kinds of target while adjusting the sputtering rate of each target.

(3) Controlling using impurities The carrier concentration of active layer 18 can be decreased by adding a substance such as Li, Na, Mn, Ni, Pd, Cu, Cd, C, N or P to the amorphous oxide semiconductor as an impurity. Methods of adding an impurity include a method of performing co-evaporation of an amorphous oxide semiconductor and an impurity, and a method of doping ions of an element used as an impurity to active layer 18 formed from an amorphous oxide semiconductor.

(4) Selecting the type of oxide semiconductor material

The carrier concentration of active layer 18 can be controlled by selecting the type of amorphous oxide semiconductor material used for active layer 18.

The above methods (1) to (4) may be used alone or in combination.

The formation of active layer 18 is preferably performed by a gas-phase method using a polycrystal sintered body of an oxide semiconductor. Preferable gas-phase methods include a sputtering method and a pulse laser deposition (PLD) method. From the viewpoint of mass production, a sputtering method is preferred. For example, active layer 18 may be formed by an RF magnetron sputtering deposition method while controlling the degree of vacuum or the flow rate of oxygen.

Whether or not the thus formed active layer 18 is an amorphous film can be determined by a known X-ray diffraction method. The composition ratio of active layer 18 can be determined by Rutherford back scattering (RBS) analysis.

The conductivity of active layer 18 is preferably from 10 ^"4 Scm ^"1 to less than 10 ² Scm ^"1 , more preferably from 10 ^"1 Scm ^"1 to less than 10 ² Scm ^"1 . The conductivity of active layer 18 can be adjusted by the aforementioned methods (1) to (4) alone or in combination thereof.

The thickness of active layer 18 is preferably from 0.1 nm to 100 nm, more preferably from 1 nm to 80 nm, further preferably from 10 nm to 50 nm, from the viewpoint that active layer 18 can function in a proper manner. When active layer 18 is too thick, the amount of threshold-voltage shift may increase.

Exemplary materials for source electrode 2OA and drain electrode 2OB include metals such as Al, Mo, Cr, Ta, Ti, Au and Ag, alloys such as Al-Nd and APC, metal oxide conductive films of tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), indium zinc oxide (IZO) and the like, organic conductive compounds such as polyaniline, polythiophene and polypyrrole, and mixtures thereof.

The thickness of source electrode 2OA and drain electrode 2OB is preferably from 10 nm to 1000 nm, more preferably from 20 nm to 500 nm, further preferably from 40 nm to 400 nm, from the viewpoint of securing a sufficiently low level of resistance. When these electrodes are too thick, it may be difficult to form a further device on the TFT device.

The methods of forming source electrode 2OA and drain electrode 2OB are not particularly limited, but may be selected as appropriate according to the compatibility with the material for the electrodes, from a wet method such as printing and coating, a physical method such as vacuum evaporation, sputtering, and ion plating, a chemical method such as CVD and plasma CVD, and the like. For example, when ITO is used as the material, the electrodes are preferably formed by a direct-current or high-frequency sputtering method, a vaccum deposition method, an ion plating method, or the like.

Fig. 2 is a schematic view of field effect transistor 10 viewed from the side of protection layer 24 (opposite to substrate 12), i.e., from direction A shown in Fig. 1.

Protection layer 24 is formed from an amorphous inorganic material and has at least a function of protecting active layer 18 from moisture or oxygen. Protection layer 24 is provided so as to cover at least a portion of active layer 18 that corresponds to an area between source electrode 2OA and drain electrode 2OB (see Fig. 2).

Further, in field effect transistor 10 according to the present exemplary embodiment, protection layer 24 has a band gap that is greater than that of active layer 18.

As mentioned above, in field effect transistor 10, protection layer 24 formed from an amorphous inorganic material is provided so as to cover at least a portion of active layer 18 that corresponds to an area between source electrode 2OA and drain electrode 2OB. Therefore, injection of electrons from source electrode 2OA into protection layer 24 and running of the electrons from protection layer 24 into drain electrode 2OB can be suppressed. Accordingly, the gate voltage applied at the time a drain current rises (Von) can remain at a certain level without significantly decreasing. As a result, in field effect transistor 10, the current tends to run to the side of active layer 18 in an area between source electrode 2OA and drain electrode 2OB, thereby suppressing the threshold-voltage shift and improving the operation stability.

The value of the band gap of protection layer 24 is not particularly limited as long as it is greater than that of active layer 18, but is preferably greater than the band gap of active layer 18 by 0.1 eV or more, more preferably by 1.0 eV or more.

When source electrode 2OA and drain electrode 2OB are directly in contact with active layer 18, the "portion of active layer 18 that corresponds to an area between source electrode 2OA and drain electrode 2OB" refers to an exposed portion of active layer 18 between source electrode 2OA and drain electrode 2OB.

When source electrode 2OA and drain electrode 2OB are formed on active layer 18 via a further layer, the "portion of active layer 18 that corresponds to an area between source electrode 20A and drain electrode 2OB" refers to an exposed portion of the further layer between source electrode 2OA and drain electrode 20B that corresponds to active layer 18 (when viewed from the direction A in Fig. 1). Further, protection layer 24 preferably at least partially contacts source electrode 2OA and drain electrode 2OB, as well as covering the portion of active layer 18 that corresponds to an area between source electrode 2OA and drain electrode 2OB, in order to fully cover a channel portion between source electrode 2OA and drain electrode 2OB.

Moreover, protection layer 24 may be positioned so that at least a portion thereof directly contacts active layer 18, or may be positioned via a further layer.

The amorphous inorganic material for protection layer 24 preferably satisfies the above relationship of the band gap, as well as having a function of suppressing the entering of a substance that promotes degradation of active layer 18, such as moisture or oxygen, into active layer 18, as mentioned above.

Specifically, the material for protection layer 24 is preferably at least one oxide selected from the group consisting of Ga, Mg and Ca, or a nitride of Al; more preferably at least one oxide selected from the group consisting of Ga and Mg, or a nitride of Al.

Exemplary materials for protection layer 24 include Ga ₂ O ₃ , AlN, MgO, and CaO. Among these, Ga ₂ O ₃ , MgO and CaO are preferable since protection layer 24 can be produced using an oxygen gas that is the same as that used for the production of active layer 18.

As mentioned above, protection layer 24 needs to have a band gap that is greater than that of active layer 18.

The value of the band gap of protection layer 24 is not particularly limited as long as it is greater than that of active layer 18, but is preferably from 4.0 eV to less than 8.0 eV, more preferably from 4.2 eV to 6.0 eV, particularly preferably from 4.5 eV to 5.0 eV.

The band gap of protection layer 24 can be adjusted by selecting the type of material for protection layer 24.

Further, as mentioned above, the carrier concentration of protection layer 24 is preferably less than the carrier concentration of active layer 18. The carrier concentration of protection layer 24 is not particularly limited, but is preferably 1 ^χ lO ¹⁴ /cm ³ or less, more preferably l ^χ lO ¹³ /cm ³ or less, further preferably l ^χ lO ^I2 /cm ³ or less.

The adjustment of carrier concentration of protection layer 24 can be conducted by adjusting the flow rate of oxygen or nitrogen during the process of forming a layer by performing sputtering or CVD.

The method of forming protection layer 24 is not particularly limited, and may be conducted by a known method. Examples of the method include a vacuum evaporation method, a sputtering method, a reactive sputtering method, an MBE (molecular beam epitaxy) method, a cluster ion beam method, an ion plating method, a plasma polymerization (high-frequency ion plating) method, a plasma CVD method, a laser CVD method, a thermal CVD method, a gas source CVD method, a coating method, a printing method, and a transfer method. Among these, a sputtering method is preferred in view of the formation rate of a film or the quality of the obtained film. Further, in order to secure the stability of protection layer 24, an annealing treatment may be performed after the formation thereof.

When protection layer 24 is formed by a sputtering method using a mixture gas of oxygen and argon, the volume ratio of O ₂ to Ar may be 0% to less than 20%, preferably less than 15%, more preferably 10% or less, in view of improving the formation rate of the film.

Typically, SiO ₂ is used for protection layer 24 since this material has a function of blocking moisture or oxygen. However, when protection layer 24 is formed using SiO ₂ by performing sputtering with a mixture gas with a mixture ratio as mentioned above, active layer 18 may be damaged. Therefore, the sputtering conditions need to be adjusted by reducing the sputtering rate to an extremely low level, or the like.

On the other hand, protection layer 24 according to the present exemplary embodiment, which satisfies the aforementioned requirements when used in field effect transistor 10, can be formed without the need of particular adjustments such as the above, and can be formed by a typical method without damaging active layer 18, in a simple manner. Specifically, as mentioned above, it is possible to form protection layer 24 using a mixture gas with an ordinary mixture ratio of oxygen and argon, without damaging active layer 18.

Other sputtering conditions than those concerning a sputtering gas as mentioned above (such as the level of RP power or pressure) may be selected as appropriate according to the type of the target.

The thickness of protection layer 24 is preferably from 10 nm to 1000 nm, more preferably from 20 nm to 500 nm, further preferably from 10 nm to 100 nm, from the viewpoint of preventing entering of moisture or oxygen to some extent, and readily forming vertical holes from which wirings are taken out to the upper side.

As mentioned above, in field effect transistor 10 according to the present exemplary embodiment, protection layer 24 is provided so as to cover at least a portion of active layer 18 that corresponds to an area between source electrode 2OA and drain electrode 2OB, and protection layer 24 has a band gap that is greater than that of active layer 18. Therefore, a field effect transistor that is less susceptible to the effects of moisture or oxygen, and has an improved threshold- voltage shift can be provided.

In the present exemplary embodiment, as shown in Fig. 1 , field effect transistor 10 has a structure that includes source electrode 2OA and drain electrode 2OB formed on active layer 18, and protection 24 formed on these electrodes. In this structure, a portion of active layer 18 including an interface that faces source electrode 2OA and drain electrode 2OB may function as a resistance layer (described later) or an interlay er (described later).

Specifically, as shown in Fig. 3, resistance layer 19 that may function as part of active layer 18 may be provided between active layer 18 and source and drain electrodes 2OA and 2OB. A further interlayer (not shown) that may function as part of active layer 18 may be provided between resistance layer 19 and active layer 18.

Resistance layer 19 has a lower conductivity than that of active layer 18.

Specifically, the ratio of conductivity of active layer 18 to resistance layer 19 (conductivity of active layer 18 / conductivity of resistance layer 19) is from 10 ¹ to 10 ¹⁰ , more preferably from 10 ² to 10 ¹⁰ , further preferably from 10 ² to 10 ⁸ .

The conductivity of active layer 18 is from 10 ^"4 Son ^"1 to less than 10 ² Scm ^"1 , more preferably from 10 ^'1 Scm ^"1 to less than 10 ² Scm ^"1 . The conductivity of resistance layer 19 is preferably 10 ^"2 Scm ^"1 or less, more preferably from 10 ^"9 Scm ^'1 to 10 ^"3 Scm ^"1 .

When resistance layer 19 is provided, the thickness of active layer 18 is preferably greater than that of resistance layer 19. Specifically, the ratio of thickness of active layer 18 to resistance layer 19 (thickness of active layer 18 / thickness of resistance layer 19) is preferably greater than 1 but 100 or less, more preferably greater than 1 but 10 or less. When the above ratio is 1 or less, a favorable durability upon application of a current may not be obtained since the thickness of active layer 18, through which the current runs, is less than that of resistance layer 19. When the above ratio is greater than 100, it is not favorable since the effects of providing resistance layer 19 may not be sufficient, and the value of ON/OFF ratio may be small.

The material for the interlayer is not particularly limited, as long as it includes an oxide including an element species that has a stronger binding force with oxygen than that of the amorphous oxide semiconductor included in active layer 18. The binding force of a metal element with oxygen is a physical value clearly defined as a binding energy with oxygen, as described on page 100 of Techniques of Transparent Conductive Films (edited by Japan Society for the Promotion of Science); Transparent Oxides (edited by the 166th Committee on Photonic and Electronic Oxide); page 104 of Transparent Oxide Functional Materials and Applications Thereof (authored by Masahiro Hirano, edited by Hideo Hosono, published by CMC Publishing Co., Ltd.); and the like.

As described above, the interlayer is provided between active layer 18 and resistance layer 19. Since the interlayer includes an oxide including an element species having a strong binding force with oxygen, the interlayer is less susceptible to the effects of the sputtering process due to the strong binding force with oxygen, and maintains a stable state of binding with oxygen. As a result, the underlying active layer 18 can be saved from damage during the sputtering process, and the semiconductor characteristics of active layer 18 can be stably maintained.

The oxide including an element species having a stronger binding force with oxygen than that of the amorphous oxide semiconductor used in active layer 18 is preferably an oxide including at least one element selected from the group consisting of Ba, Ca, Ti, Fe, Ga, Mg, Al, Ge and Si, more preferably from the group consisting of Ga, Mg, Al and Si, further preferably from a group consisting of Ga and Mg.

Specific examples of the oxide including an element species having a stronger binding force with oxygen than that of the amorphous oxide semiconductor used in active layer 18 include, but not limited thereto, BaO, CaO, TiO ₂ , Fe ₂ O ₃ , Ga ₂ O ₃ , MgO, Al ₂ O ₃ , SiO ₂ , GeO and SiO.

Other examples of the oxide including an element species having a stronger binding force with oxygen than that of the amorphous oxide semiconductor used in active layer 18 include those described in Techniques of Transparent Conductive Films (edited by Japan Society for the Promotion of Science); Transparent Oxides (edited by the 166th Committee on Photonic and Electronic Oxide); Transparent Oxide Functional Materials and Applications Thereof (authored by Masahiro Hirano, edited by Hideo Hosono, published by CMC Publishing Co., Ltd.); and the like.

The method of forming the resistance layer or the interlayer may be selected from the methods of forming active layer 18 as mentioned above.

In the present exemplary embodiment, protection layer 24 is described as a single layer. However, protection layer 24 may be formed from plural layers, as shown in field effect transistor 1OB in Fig. 4, which has protection layer 24 formed by layering protection layer 24A and protection layer 24B.

In this case, from the viewpoint of controlling the threshold value and the threshold- voltage shift, the band gap of protection layer 24 A, which is positioned closer to active layer 18 than protection layer 24B, is preferably smaller than that of protection layer 24B.

Further, from the viewpoint of controlling the threshold- voltage shift or reducing the amount of off-current, the carrier concentration of protection layer 24 A, which is positioned closer to active layer 18 than protection layer 24B, is preferably greater than that of protection layer 24B.

In the above exemplary embodiment, field effect transistor 10 has a structure including, on substrate 12, gate electrode 14, gate insulation film 16, active layer 18, source electrode 2OA and drain electrode 2OB, and protection layer 24, in this order (top-contact type). However, the structure is not limited to the above and may be a structure in which active layer 18 and protection layer 24 are formed in this order on source electrode 2OA and drain electrode 2OB (bottom-contact type).

Specifically, as shown in field effect transistor 1OC of Fig. 5, it is possible to form, on substrate 12, gate electrode 14, gate insulation film 16, source electrode 2OA and drain electrode 2OB, active layer 18, and protection layer 24, in this order.

The field effect transistor according to the present exemplary embodiment may be used as a switching device or a driving device for an image display apparatus (such as an FPD) that employs a liquid crystal device or an EL device.

In particular, the field effect transistor according to the present exemplary embodiment is suitably used as a switching device or a driving device for a flexible FPD. Further, the display device using the field effect transistor according to the present exemplary embodiment is applicable to a wide range of usages including cellular phone displays, personal digital assistants (PDAs), computer displays, information displays for automobiles, TV monitors, and illumination devices. Moreover, the field effect transistor according to the present exemplary embodiment can be widely used in other applications than these display devices, such as IC cards and ID tags, by forming field effect transistor 10 on a flexible substrate such as an organic plastic film.

The following are exemplary embodiments of the present invention. However, the invention is not limited to these embodiments.

<1> A field effect transistor comprising a substrate, a gate electrode, a gate insulation film, an active layer comprising an amorphous oxide, a source electrode, a drain electrode, and a protection layer comprising an amorphous inorganic material, the protection layer being provided so as to cover at least a portion of the active layer that corresponds to an area between the source electrode and the drain electrode, and the protection layer having a band gap that is greater than the band gap of the active layer. <2> The field effect transistor according to <1>, wherein the band gap of the active layer is from 2.5 eV to less than 4.0 eV.

<3> The field effect transistor according to <1>, wherein the band gap of the protection layer is from 4.0 eV to less than 8.0 eV.

<4> The field effect transistor according to <1>, wherein the active layer comprises an amorphous oxide that comprises at least one element selected from the group consisting of In, Sn, Zn and Cd.

<5> The field effect transistor according to <1>, wherein the protection layer comprises at least one oxide selected from the group consisting of Ga, Mg and Ca, or a nitride of Al. <6> The field effect transistor according to <1>, further comprising a resistance layer between the active layer and the source and drain electrodes, the resistance layer having a conductivity that is lower than that of the active layer. <7> The field effect transistor according to <6>, further comprising an interlayer between the resistance layer and the protection layer, the interlayer comprising an oxide that comprises an element having a stronger binding force with oxygen than that of the amorphous oxide in the active layer. <8> A method of producing a field effect transistor, the field effect transistor comprising a substrate, a gate electrode, a gate insulation film, an active layer comprising an amorphous oxide, a source electrode, a drain electrode, and a protection layer comprising an amorphous inorganic material, the protection layer being formed by a sputtering method using a mixed gas of oxygen and argon with a volume ratio of oxygen to argon ((VAr) is from 0% to less than 20%. <9> The method of producing a field effect transistor according to <8>, wherein the protection layer is formed so as to cover at least a portion of the active layer that corresponds to an area between the source electrode and the drain electrode, and the protection layer having a band gap that is greater than the band gap of the active layer. <10> The method of producing a field effect transistor according to <8>, wherein the band gap of the active layer is from 2.5 eV to less than 4.0 eV.

<11> The method of producing a field effect transistor according to <8>, wherein the band gap of the protection layer is from 4.0 eV to less than 8.0 eV.

<12> The method of producing a field effect transistor according to <8>, wherein the active layer comprises an amorphous oxide that comprises at least one element selected from the group consisting of In, Sn, Zn and Cd.

<13> The method of producing a field effect transistor according to <8>, wherein the protection layer comprises at least one oxide selected from the group consisting of Ga, Mg and Ca, or a nitride of Al.

<14> The method of producing a field effect transistor according to <8>, further comprising a resistance layer between the active layer and the source and drain electrodes, the resistance layer having a conductivity that is lower than that of the active layer. <15> The method of producing a field effect transistor according to <14>, further comprising an interlayer between the resistance layer and the protection layer, the interlayer comprising an oxide that comprises an element having a stronger binding force with oxygen than that of the amorphous oxide in the active layer. Examples

In the following, the field effect transistor of the present invention is described with reference to the following examples. However, the invention is not limited to these examples.

Table 1 shows the values of band gap (optically-measured energy gap) of the materials used for the active layer and the protection layer prepared in the following Examples and the Comparative Examples.

The value of band gap was obtained in the following manner.

The absorbance of the protection layer or the active layer as prepared from the material shown in Table 1 was measured by using a spectrophotometer (product type: U3010, manufactured by Hitachi, Ltd.), while changing the wavelength of the light used for irradiation. Then, the relationship between the absorbance and the wavelength was obtained as shown in diagram 50 of Fig. 6. As shown in Fig. 6, after the absorbance rapidly decreases as the wavelength shifts to the side of longer wavelength (line 50A), the pace of the decrease of the absorbance decreases (line 50B). Then, the wavelength B (nm) at an intersection formed by line A, which is a line extended from line 50A showing a rapid decrease in the absorbance, and line C, which shows an absorbance of 0%, is obtained. The band gap (eV) that corresponds to wavelength B (nm) is determined as the band gap (eV) of each material.

Table 1

(Example 1)

Preparation of field effect transistor 1

A field effect transistor having a structure shown in Fig. 1 was prepared in the following manner. A gate electrode of aluminum (Al) having a thickness of 400 nm was formed by resistant heating evaporation (temperature: 25 °C) on an N-type Si substrate having a thickness of 0.5 mm (resistivity: 1 Ωcm to 3.5 Ωcm, manufactured by Jemco, Co., Ltd.)

Subsequently, a gate insulation film of SiO ₂ having a thickness of 100 nm was formed on the gate electrode by an RF magnetron sputtering vacuum evaporation method (target: SiO ₂ , temperature: 54 °C, sputtering gas: Ar/O ₂ =12/2 seem, RF power: 400W, pressure: 0.4 Pa). The patterning of the gate insulation film was performed by using a shadow mask during the sputtering.

An active layer having a thickness of 50 nm was formed on the gate insulation layer using a polycrystal sintered body having a composition OfInGaZnO ₄ as a target, by an RF magnetron sputtering vacuum evaporation method (Ar flow rate: 97 seem, O ₂ flow rate: 2.0 seem, RF power: 200W, total pressure: 0.38 Pa).

A source electrode and a drain electrode each having a thickness of 400 nm were formed from aluminum (Al) on the active layer by a resistance heating evaporation method (temperature: 25 ⁰ C). The patterning of the source electrode and the drain electrode was performed by a photo resist method. The distance between the thus formed source electrode and the drain electrode was 200 μm.

A protection layer was formed from gallium oxide (Ga ₂ O ₃ ) by sputtering so as to contact both the source and drain electrodes and cover an exposed region of the active layer between these electrodes. The thickness of the thus formed protection layer was 10 nm. The sputtering was performed by an RF magnetron sputtering method using a mixed gas with a mixed ratio O ₂ / Ar of 5% (target: Ga ₂ O ₃ , Ar flow rate: 97.0 seem, O ₂ flow rate: 5.0 seem, RF power: 10OW, total pressure: 0.4Pa).

Subsequently, an annealing treatment was performed at 180 °C, and field effect transistor 1 was thus obtained.

(Example 2)

Field effect transistor 2 was produced in a similar manner to Example 1, except that the protection layer was formed from MgO instead Of Ga ₂ O ₃ .

Specifically, a gate electrode, a gate insulation film, an active layer, and a source and drain electrodes were formed on a substrate in a similar manner to Example 1.

Then, a protection layer of MgO was formed by sputtering so as to contact both of the source and drain electrodes, and cover an exposed region of the active layer between the electrodes. The thickness of the thus formed protection layer was 10 nm. The sputtering was performed by an RF magnetron sputtering method using a mixed gas with a mixed ratio O ₂ / Ar of 5% (target: MgO, Ar flow rate: 97.0 seem, O ₂ flow rate: 5.0 seem, RF power: 10OW, total pressure: 0.4 Pa).

Subsequently, an annealing treatment was performed at 180 ⁰ C, and field effect transistor 2 was thus obtained.

(Example 3)

Field effect transistor 3 was prepared in a similar manner to Example 1, except that the active layer includes a portion that functions as an interlayer and a resistance layer, by forming an interlayer and a resistance layer to a portion of the active layer between the source and drain electrodes.

Specifically, a gate electrode, a gate insulation film and an active layer were formed on a substrate in a similar manner to Example 1.

Then, an interlayer having a thickness of 10 nm was formed so that the volume ratio InGaZnO ₄ :Ga ₂ O ₃ was 15:2, on the active layer by sputtering.

Further, a resistance layer of Ga ₂ O ₃ having a thickness of 10 nm was formed by sputtering.

The sputtering OfInGaZnO ₄ for the interlayer was performed under the conditions of target: InGaZnO ₄ , Ar flow rate: 97.0 seem, O ₂ flow rate: 5.0 seem, RF power: 200W and total pressure: 0.4Pa.

The sputtering OfGa ₂ O ₃ for the interlayer was performed under the conditions of target: Ga ₂ O ₃ , Ar flow rate: 97.0 seem, O ₂ flow rate: 5.0 seem, RF power: IOOW and total pressure: 0.4Pa.

The sputtering of the resistance layer was performed under the conditions of target: Ga ₂ O ₃ , Ar flow rate: 97.0 seem, O ₂ flow rate: 5.0 seem, RF power: IOOW and total pressure: 0.4Pa.

Then, a source electrode and a drain electrode each having a thickness of 400 nm were formed from aluminum (Al) by a resistance heating evaporation (temperature: 25 ⁰ C) in a similar manner to Example 1.

Thereafter, a protection layer of gallium oxide (Ga ₂ O ₃ ) was formed by sputtering so as to contact both the source and drain electrodes and cover an exposed region of the active layer between these electrodes. The thickness of the thus formed protection layer was 10 nm. The sputtering was performed under the same conditions as that for the formation of protection layer of Example 1.

Subsequently, an annealing treatment was performed at 180 °C, and field effect transistor 3 was thus obtained.

(Example 4)

Field effect transistor 4 was formed in a similar manner to Example 1 , except that the protection layer was formed from two layers of gallium oxide (Ga ₂ O ₃ ).

Specifically, a gate electrode, a gate insulation film, an active layer, a source electrode and a drain electrode were formed on a substrate in a similar manner to Example 1.

Then, a first protection layer was formed from gallium oxide (Ga ₂ Oa) by sputtering so as to contact both the source and drain electrodes and cover an exposed portion of the active layer between these electrodes. The thickness of the first protection layer was 10 nm. The sputtering conditions were the same as that for forming the protection layer in Example 1. Subsequently, a second protection layer was formed from SiO ₂ on the first protection layer by sputtering. The thickness of the second protection layer was 1 nm.

The sputtering of the second protection layer was performed by an RF magnetron sputtering method using a mixed gas at a mixed ratio CVAr of 5% (target: SiO ₂ , Ar flow rate: 97.0 seem, O ₂ flow rate: 5.0 seem, RF power: 10OW, total pressure: 0.4 Pa).

Subsequently, an annealing treatment was performed at 180 °C, and field effect transistor 4 was thus obtained.

(Comparative Example 1)

Comparative field effect transistor 1 was prepared in a similar manner to Example 1, except that the protection layer was not provided.

(Comparative Example 2)

Comparative field effect transistor 2 was formed in a similar manner to Example 1, except that the protection layer was formed from In ₂ O ₃ instead Of Ga ₂ O ₃ .

Specifically, a gate electrode, a gate insulation film, an active layer, a source electrode and a drain electrode were formed on a substrate in a similar manner to Example 1.

Then, a protection layer was formed from In ₂ O ₃ by sputtering so as to contact both of the source and drain electrodes and cover an exposed portion of the active layer between these electrodes. The thickness of the first protection layer was 10 nm.

The sputtering of the protection layer was performed by an RF magnetron sputtering method using a mixed gas at a mixed ratio O ₂ / Ar of 5% (target: In ₂ O ₃ , Ar flow rate: 97.0 seem, O ₂ flow rate: 5.0 seem, RF power: 10OW, total pressure: 0.4 Pa).

Subsequently, an annealing treatment was performed at 180 °C, and comparative field effect transistor 2 was thus obtained.

(Comparative Example 3)

Comparative field effect transistor 3 was prepared in a similar manner to Example 3, except that the protection layer was formed from IGZO instead OfGa ₂ O ₃ .

Specifically, a gate electrode, a gate insulation film, an active layer, a source electrode and a drain electrode were formed on a substrate in a similar manner to Example 3.

Then, a protection layer was formed from IGZO by sputtering so as to contact both the source and drain electrodes and cover an exposed portion of the active layer between these electrodes. The thickness of the first protection layer was 10 nm.

The sputtering of the protection layer was performed by an RF magnetron sputtering method using a mixed gas at a mixed ratio O ₂ /Ar of 5% (target: IGZO, Ar flow rate: 97.0 seem, O ₂ flow rate: 2.0 seem, RF power: 200W, total pressure: 0.38 Pa).

Subsequently, an annealing treatment was performed at 180 °C, and comparative field effect transistor 3 was thus obtained.

<Evaluation>

The voltage at which a current of a minimum value is generated (Von) and the amount of threshold- voltage shift of the field effect transistor as prepared in the Examples 1 to 4 and the Comparative Examples 1 to 3 were measured in the following manner.

Voltage at which a minimum current is generated (Von)

Fig. 7 shows the current- voltage characteristic curves of the field effect transistors and the comparative field effect transistors (curves 60 to 62). The horizontal axis represents a gate voltage (Vg) and the vertical axis represents a drain current (Id). Von represents a voltage at which a minimum current is generated.

In this evaluation, the voltage at which a minimum current is generated (Von) was calculated from a current- voltage characteristic curve obtained by measuring the transmittance characteristics of the field effect transistors and the comparative field effect transistors as prepared in the Examples 1 to 4 and the Comparative Examples 1 to 4, at a drain voltage in a saturated region Vd=I 5V (the range of gate voltage (Vg): from -10V to 15V).

The measurement of the transmittance characteristics was conducted by using a semiconductor parameter analyzer (product number: 4165C, manufactured by Agilent Technologies).

Measurement of threshold- voltage shift amount (ΔVth)

-Threshold- voltage shift amount A-

The field effect transistors and the comparative field effect transistors as prepared in the Examples 1 to 4 and the Comparative Examples 1 to 3 were driven four times in a consecutive manner, respectively, at a source-drain voltage (Vsd) of +10 V and a gate voltage (Vg) of from -10 V to +15 V. The value of the threshold- voltage shift (Vth) of the field effect transistor was measured at each time the field effect transistor was. driven, and the amount of change of Vth during the four times of driving was determined as the threshold- voltage shift amount A.

-Threshold-voltage shift amount B-

A stress was applied to the field effect transistors and the comparative field effect transistors as prepared in the Examples 1 to 4 and the Comparative Examples 1 to 3, via a diode connection for 14 hours so that the stress current (IDS) was 3 μA, while short-circuiting the source electrode and the drain electrode. The amount of change of the threshold value between before and after the application of stress was determined as the threshold-voltage shift amount B.

The results are shown in the following Table 2. Table 2

O

As shown in Table 2, lowering of the voltage at which the minimum current is generated (Von) in field effect transistors 1 to 4 (Examples 1 to 4) was suppressed as compared with comparative field effect transistors 2 and 3 (Comparative Examples 2 and 3).

Further, field effect transistors 1 to 4 (Examples 1 to 4) exhibited a suppressed threshold- voltage shift amount A as compared with comparative field effect transistors 1 and 3 (Comparative Examples 1 and 3). This effect of suppressing the threshold- voltage shift was even more remarkable in the case of threshold- voltage shift amount B.

Accordingly, the field effect transistors prepared in the Examples are less susceptible to damage to the active layer due to moisture or oxygen, and have an improved threshold- voltage shift, as compared with the comparative field effect transistors prepared in the Comparative Examples.

All publications, patent applications, and technical standards mentioned in this specification are herein incorporated by reference to the same extent as if each individual publication, patent application, or technical standard was specifically and individually indicated to be incorporated by reference.