FIRST LAYER INTERCONNECT FIRST ON CARRIER APPROACH FOR EMIB PATCH

Title:

FIRST LAYER INTERCONNECT FIRST ON CARRIER APPROACH FOR EMIB PATCH

Document Type and Number:

WIPO Patent Application WO/2019/139625

Kind Code:

A1

Abstract:

A patch structure of an integrated circuit package comprises a core having a first side facing downwards and a second side facing upwards. Forming a first solder resist (SR) layer on the first side of the core, wherein the first SR layer comprises a first layer interconnect (FLI) and has a first set of one or more microbumps thereon to bond to one or more logic die. Forming a second solder resist (SR) layer on the second side of the core, wherein the second SR layer has a second set of one or more microbumps thereon to bond with a substrate. One or more bridge dies includes a respective sets of bumps, wherein the one or more bridge dies is disposed flipped over within the core such that the respective sets of bumps face downward and connect to the first set of one or more microbumps in the FLI.

Inventors:

LIU CHANGHUA (US)
GUO XIAOYING (US)
ALEKSOV ALEKSANDAR (US)
CHO STEVE S (US)
ARANA LEONEL (US)
MAY ROBERT (US)
DUAN GANG (US)

Application Number:

PCT/US2018/013620

Publication Date:

July 18, 2019

Filing Date:

January 12, 2018

Export Citation:

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Assignee:

INTEL CORP (US)
LIU CHANGHUA (US)
GUO XIAOYING (US)
ALEKSOV ALEKSANDAR (US)
CHO STEVE S (US)
ARANA LEONEL (US)
MAY ROBERT (US)
DUAN GANG (US)

International Classes:

H01L25/065; H01L21/027; H01L21/56; H01L23/00; H01L23/48; H01L23/498

Foreign References:

US20140102772A1	2014-04-17
US20170250150A1	2017-08-31
US20130270230A1	2013-10-17
US20160044786A1	2016-02-11
US20150262958A1	2015-09-17

Other References: