VERTICAL FIELD EFFECT TRANSISTORS HAVING EXTENDED DRAIN REGIONS AND METHODS OF MANUFACTURING THE SAME

Title:

VERTICAL FIELD EFFECT TRANSISTORS HAVING EXTENDED DRAIN REGIONS AND METHODS OF MANUFACTURING THE SAME

Document Type and Number:

WIPO Patent Application WO/2019/139624

Kind Code:

A1

Abstract:

Vertical field effect transistors having extended drain regions and methods of manufacturing the same are disclosed. An example field effect transistor includes a drain including at least one of gallium, nitrogen, or indium, and a source. A semiconductor body is positioned between the drain and the source. The semiconductor body having a first portion and a second portion. The first portion includes a first semiconductor material and the second portion includes a second semiconductor material different than the first semiconductor material. The second semiconductor material includes at least one of aluminum, gallium, or nitrogen.

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Inventors:

DASGUPTA SANSAPTAK (US)
THEN HAN WUI (US)
RADOSAVLJEVIC MARKO (US)

Application Number:

PCT/US2018/013614

Publication Date:

July 18, 2019

Filing Date:

January 12, 2018

Export Citation:

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Assignee:

INTEL CORP (US)

International Classes:

H01L29/732; H01L29/423; H01L29/66; H01L29/78

Foreign References:

US20110018058A1	2011-01-27
US20130341702A1	2013-12-26
US20100142294A1	2010-06-10
US20170288056A1	2017-10-05
US20160064541A1	2016-03-03

Attorney, Agent or Firm:

GREEN, Blayne, D. (US)

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