Title:
FLIP-FLOP CIRCUIT, AND METHOD OF HOLDING AND SYNCHRONIZING DATA USING CLOCK SIGNAL
Document Type and Number:
WIPO Patent Application WO/2001/018962
Kind Code:
A1
Abstract:
A low-power, high-speed flip-flop circuit is provided that has a simplified, smaller circuit configuration. A flip-flop comprises two latch hold circuits composed of transistors (B1-B4) and transistors (B5-B8), respectively; and a clock-input differential circuit composed of transistors (B9-B12). With clock inputs (CP) and (CN) being high and low, respectively, transistors (B9, B10) turn on, and the current from a constant current source (12) turns transistor (B2, B3) off. Similarly, transistors (B5, B8) are also turned off, causing the second latch hold circuit to be in hold state. With clock inputs (CP) and (CN) being low and high, respectively, the states of the first and second latch hold circuits are switched, resulting in flip-flop operation.
Inventors:
KIMURA HIROYUKI (JP)
Application Number:
PCT/JP2000/005924
Publication Date:
March 15, 2001
Filing Date:
August 31, 2000
Export Citation:
Assignee:
LUCENT TECHNOLOGIES INC (US)
KIMURA HIROYUKI (JP)
KIMURA HIROYUKI (JP)
International Classes:
H03K19/086; H03K3/286; H03K3/2885; H03K3/289; (IPC1-7): H03K3/289; H03K3/286
Foreign References:
| JPH09266435A | 1997-10-07 |
Attorney, Agent or Firm:
Mitsumata, Hirofumi (Roppongi Minato-ku, Tokyo, JP)
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