FPGA UPGRADING METHOD BASED ON PCIE INTERFACE

Title:

FPGA UPGRADING METHOD BASED ON PCIE INTERFACE

Document Type and Number:

WIPO Patent Application WO/2020/114431

Kind Code:

A1

Abstract:

An FPGA upgrading method, comprising: a host issuing an upgrade instruction to an FPGA; the host unloading a PCIe driving program corresponding to the FPGA, so that a state of a PCIe link is changed to a disconnection state; the host continuously detecting, in a first timeout time period, whether the state of the PCIe link is changed to a connection state; and if so, re-loading the PCIe driving program. The method further comprises: after the FPGA receives the upgrade instruction, the FPGA continuously detecting, in a second timeout time period, whether the state of the PCIe link is changed to the disconnection state, wherein the disconnection state is the state of the PCIe link after the host unloads the PCIe driving program corresponding to the FPGA; if so, the FPGA loading, from a configuration memory of the FPGA, configuration data to perform upgrading; and after the upgrading is completed, the FPGA restoring, by means of negotiating with the host, the state of the PCIe link to the connection state for re-loading the PCIe driving program after the connection state is detected by the host.

Inventors:

XIANG JIANBO (CN)
ZHANG BO (CN)

Application Number:

PCT/CN2019/123069

Publication Date:

June 11, 2020

Filing Date:

December 04, 2019

Export Citation:

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Assignee:

HUAWEI TECH CO LTD (CN)

International Classes:

G06F8/65

Foreign References:

CN107038040A	2017-08-11
CN107656776A	2018-02-02
CN102053850A	2011-05-11
CN108400899A	2018-08-14
CN107797816A	2018-03-13
US20090119659A1	2009-05-07
CN201811480823A	2018-12-05

Other References: