Title:
HIGH OUTPUT POWER AMPLIFIER
Document Type and Number:
WIPO Patent Application WO/2013/088635
Kind Code:
A1
Abstract:
In order to reliably prevent breakage of an FET due to an overcurrent, this high output power amplifier using a depression-type FET is provided with: a drain voltage supply unit (120, 220, 320), which generates a positive voltage to be applied to a drain terminal of the depression-type FET; and a gate bias voltage supply unit (130, 230, 330), which generates a negative voltage to be applied to a gate terminal of the depression-type FET. The drain voltage supply unit uses an external commercial power supply as a power supply, and the gate bias voltage supply unit uses a battery as a power supply.
Inventors:
OKAJIMA TOSHIYUKI
Application Number:
PCT/JP2012/007200
Publication Date:
June 20, 2013
Filing Date:
November 09, 2012
Export Citation:
Assignee:
PANASONIC CORP (JP)
International Classes:
H03F1/52; H03F3/24
Foreign References:
JPH09181534A | 1997-07-11 | |||
JPH05175750A | 1993-07-13 | |||
JPH0326028A | 1991-02-04 | |||
JPS58127706U | 1983-08-30 | |||
JPH09238030A | 1997-09-09 | |||
JP2000068756A | 2000-03-03 |
Other References:
See also references of EP 2793394A4
Attorney, Agent or Firm:
SAMEJIMA, Mutsumi et al. (JP)
Mutsumi Sameshima (JP)
Mutsumi Sameshima (JP)
Download PDF:
Claims:
Previous Patent: SOLID-STATE IMAGING DEVICE AND IMAGING DEVICE
Next Patent: SOI WAFER FABRICATION METHOD
Next Patent: SOI WAFER FABRICATION METHOD