Technical Field

[0001 ] The present invention is concerned with a high voltage series MOSFET switching circuit. More specifically, the present invention is concerned with a circuit design utilising multiple, series connected MOSFETs to switch voltages in the order of kV.

Background Art

[0002] Metal oxide semiconductor field effect transistors (MOSFETs) are well known in the field of power electronics. They allow a low voltage input to switch a high voltage signal. For example, a typical SiC MOSFET can be switched with a voltage between gate and source (V _GS ) of a few volts, and can accept a switched voltage between drain and source (V _DS ) of 1 .2kV.

[0003] The most common type of MOSFETs used in power electronics is the n-channel enhancement mode MOSFET. Historically, silicon has been the semiconductor of choice for MOSFETs.

[0004] In recent years, wide-bandgap semiconductors devices have enabled improvements in the power electronics fields applications. At the time when silicon devices are close to the limitation of the material, silicon carbide (SiC) materials offer high switching speed, high breakdown voltage and high thermal conductivity, making it a superior material to silicon. SiC MOSFETs are a promising alternative to Si in medium and high voltage power electronics applications. Gallium nitride (GaN) MOSFETs are also a potential alternative to Si for high current applications due to its low on-state resistance.

[0005] The adoption of high voltages in various applications such as electric vehicles, renewable energy and energy storage systems is increasing. Unfortunately, power electronics switches incorporating SiC MOSFETs are lagging. SiC MOSFETs have high switching capabilities and lower power dissipation. The existing commercial SiC MOSFETs are rated at either 1 .2 and 1 .7kV at the most. Some higher voltage SiC switches are in the development stage and, even if available commercially, would be costly.

[0006] The aim of the present invention is to achieve a commercially and technically feasible power electronics switching circuit for MOSFETs at voltages in the order of kVs. [0007] Solutions proposed in the prior art include the idea of utilising multiple isolated- driven series MOSFETs to handle the increased voltage. One drawback with such systems is the need to provide a gate driver for each MOSFET. This can make it far from compact, as is required by most applications.

[0008] Another concern while driving series MOSFET devices is the off-state voltage balancing during both steady state and dynamic transition. The uneven leakage current between series MOSFETs is the main reason behind the unbalanced voltage distribution. Equal parallel resistors across series MOSFETs will not always guarantee a balanced voltage if the leakage current is significant.

[0009] A still further concern is the potential for false turn-on, particularly when the temperature of the MOSFET increases. This is because increased temperature tends to reduce the threshold voltage of the MOSFET. This is particularly true for SiC MOSFETs which tend to have a lower gate capacitance compared to Si.

[0010] Prior art systems have attempted to utilise a single gate driver to drive a plurality of series-connected MOSFETs.

[001 1 ] For example, the paper "A Compact Gate Control and Voltage-Balancing Circuit for Series-Connected SiC MOSFETs and Its Application in a DC Breaker" Y. Ren et al, IEEE Trans. Industrial Electron., vol. 64, no. 10, pp. 8299-8309, Oct. 2017 discloses a compact circuit combining function of gate control and voltage balancing for series-connected silicon carbide (SiC) MOSFETs.

[0012] A signal is initiated by the activation of the gate driver, using the change of voltage levels across the capacitor terminals. The level of generated signal by the capacitor is sufficient to reach the threshold voltage of the next MOSFET, which is thereby activated and so on.

[0013] A problem with this approach, known as capacitive coupling, is that the capacitor will generate a current based on , so current is proportional to the change in voltage. By cascading this to several MOSFETs, dV/dt will eventually fade out because of the non-ideal capacitor which exhibits losses in the form of small resistances dropping voltages. [0014] The paper "A Single Gate Driver Based Solid-State Circuit Breaker Using Series Connected SiC MOSFETs", Y. Ren, et al, IEEE Trans. Power Electron., vol. 34, no. 3, pp. 2002-2006, Mar. 2019 describes a circuit breaker arrangement in which two series connected MOSFETs are provided in order to withstand high dc-bus voltages. The paper itself states that a problem with such arrangements is that "The balanced voltage distribution across these series connected devices is the most challenging technical issue.". A drawback with this device is that it is not truly modular- each of the MOSFET devices has a different driving circuit.

[0015] The paper "A Compact Series-Connected SiC MOSFETs Module and Its Application in High Voltage Nanosecond Pulse Generator", L Pang et al, IEEE Trans. Industrial Electron., vol. 66, no. 12, pp. 9238-9247, Dec. 2019 describes a pulse generator featuring series connected MOSFETs having a single gate driver. The paper proposes capacitive coupling between the respective MOSFETs. A problem with this approach is that the driving signal becomes attenuated as more MOSFETs are added.

[0016] It is an aim of the present invention to overcome, or at least mitigate, the aforementioned problems in the prior art.

Summary of Invention

[0017] According to a first aspect of the present invention there is provided a switching circuit comprising: a plurality of n MOSFET cells (n ≥ 2), each MOSFET cell comprising: a gate terminal, a source terminal, a drain terminal and a cascading terminal; a MOSFET (MN) having a gate node (GN), source node (SN) and drain node (DN) connected to the gate, source and drain terminals respectively; a gate resistor (RG) between the gate node and a gate terminal; a balance capacitor (CB) between the source node and the cascading terminal; a balance resistor (RB) in parallel with the balance capacitor; a gate driver connected to drive the gate node (G1 ) of the first MOSFET cell; wherein: the drain terminal of each of the MOSFET cells (N=1 ...(n-1 )) is connected to the source terminal of an adjacent, MOSFET cell (N=2.... n); the cascading terminal of each of the MOSFET cells (N=1 ... (n-1 )) is connected to the gate terminal of an adjacent, MOSFET cell (N=2.... n); and, the drain terminal and cascading terminal of the nth MOSFET cell (N=n) is connected to a supply voltage (VS); such that: in an off state, the supply voltage (VS) provided across the cascading terminal of the nth cell and the source terminal of the first cell charges the balance capacitor CB of each cell; and, upon provision of a gate driving voltage to the gate terminal of the first cell (N= 1 ) to activate the MOSFET (M1 ) of the first cell, the balance capacitor (C1 ) discharges to the gate terminal of the adjacent cell to switch on the MOSFET (M2) thereof.

[0018] Advantageously the present invention utilises a switched capacitor, in which the balance capacitor of each cell is charged during the off state, and subsequently discharged through the gate-source of the next cell MOSFET M _N+1 via the cascading terminal when the cell MOSFET M _N 's drain-source current path is closed. Similarly, this happens to each cell in series. Unlike the prior art capacitive coupling concept, it is not the gate driver signal that is passed from capacitor to capacitor (cell to cell), rather each cell provides the required gate driving voltage via its own capacitor charged by the supply voltage.

[0019] In particular, the present invention:

• Provides bipolar driving for all MOSFETs in series;

• Achieves balanced voltages across all MOSFETs when they are turned off;

• Achieves switching for all MOSFETs less than 100ns;

• Is a modular design so can be duplicated for different number of series MOSFETs;

• All components are passive low cost which facilitate compact and robust design. [0020] Unlike some prior art devices, the present invention does not require separate power supplied for each of the MOSFET cells. The entire system is powered by the load current, and switched by a single gate driver at the lowest module.

[0021 ] Preferably, n ≥ 2, and upon activation of the MOSFET (M ₂ ) of the second cell, the balance capacitor (C ₂ ) discharges to the gate terminal of the adjacent cell to switch the MOSFET (M3) thereof

[0022] Preferably each MOSFET cell comprises a first diode directed from the source node (S _N ) to the gate node (G _N ). Preferably each MOSFET cell comprises a second, Zener diode directed from the gate node (G _N ) to the source node (S _N ). The first diode may be a Zener diode.

[0023] Advantageously, the provision of two back-to back Zener diodes between the gate and source nodes of the MOSFET achieves a robust negative bias for MOSFETS in 'off' state, reducing the tendency to falsely turn on.

[0024] Preferably each MOSFET cell comprises a supply diode D _s directed from the gate terminal to the cascading terminal. Preferably the supply diode D _s can be selectively disconnected in the final cell (N=n). Each MOSFET cell from N=1 to N=(n-1 ) may comprise a supply diode D _s directed from the gate terminal to the cascading terminal. The final cell N-n (a "capping cell") does not require such a diode.

[0025] In one embodiment the balance capacitor of the MOSFET cell N=n has a capacitance at least twice as high as the balance capacitors of the MOSFET cells N=1 to N=(n-1 ). Preferably the capacitance of the balance capacitors of the MOSFET cells N=1 to N=(n-1 ) are identical.

[0026] Preferably each MOSFET cell comprises a balance diode DB in series with the balance resistor RB, the balance diode directed from the cascading terminal to the source node.

[0027] Preferably each MOSFET cell comprises a second balance resistor DBd, and a second balance diode DBd in series with the balance resistor RBd, the second balance diode DBd being directed from the source node to the cascading terminal, wherein the balancing resistors have different resistances.

[0028] Preferably the MOSFETs are SiC or GaN MOSFETs. [0029] Preferably the MOSFETs are enhancement mode n-channel MOSFETs.

[0030] Preferably the supply voltage VS > 2kV.

[0031 ] According to a second aspect of the invention there is provided a switching circuit cell comprising: a gate terminal, a source terminal, a drain terminal and a cascading terminal; a MOSFET (MN) having a gate node (GN), source node (SN) and drain node (DN) connected to the gate, source and drain terminals respectively; a gate resistor (RG) between the gate node and a gate terminal; a balance capacitor (CB) between the source node and the cascading terminal; a balance resistor (RB) in parallel with the balance capacitor; a gate driver connected to drive the gate node (G1 ) of the first MOSFET cell; wherein the switching circuit cell is configured to be connected with a gate driver and at least one like cell in series to provide a high voltage switching circuit.

Brief Description of Drawings

[0032] An embodiment of the present invention will now be described with reference to the following figure in which:

FIGURE 1 a is a diagram of a first embodiment of a switching circuit according to the present invention;

FIGURE 1 b is a detail view of a part of the circuit of Figure 1 a;

FIGURE 2 is a diagram of part of a second embodiment of a switching circuit according to the present invention;

FIGURE 3 is a diagram of part of a third embodiment of a switching circuit according to the present invention;

FIGURE 4a is a diagram of a fourth embodiment of a switching circuit according to the present invention;

FIGURE 4b is a detail view of a part of the circuit of Figure 4a; FIGURES 4c to 4g are operation diagrams;

FIGURE 4h is a series of graphs of the operating characteristics of the circuit of Figure 4a;

FIGURES 4i to 4I are operation diagrams;

FIGURE 5 is a diagram of a part of a fifth embodiment of a switching circuit according to the present invention;

FIGURE 6 is a diagram of a sixth embodiment of a switching circuit according to the present invention;

FIGURE 7 is a diagram of a sixth embodiment of a switching circuit according to the present invention; and,

FIGURE 8 is a diagram of an eighth embodiment of a switching circuit according to the present invention.

Description of the first embodiment

[0033] The first embodiment is shown in Figures 1 a and 1 b.

Configuration

[0034] Referring to Figure 1 a, there is shown a diagram of a first switching circuit 100 in accordance with the present invention. The circuit 100 comprises a MOSFET gate driver 102, first driving cell 104 _N and a second driving cell 104 _N+1 .

[0035] The MOSFET gate driver 102 is known in the art and will not be described in detail here, except to say that it is a circuit configured to create or deliver a pulse / square wave input to the first cell 104 _N at V _on _ _arive to turn on (positive voltage) and Vo//-drive (negative voltage) to turn off.

[0036] The cells 104 _N , 104N+I ... 104 _n are identical (i.e. are interconnectable modules) and cell 104 _N is shown in more detail in Figure 1 b. Each cell circuit 104 _N has four terminals:

• Cell gate terminal 106;

• Cell drain terminal 108;

• Cell source terminal 110; and, • Cascading terminal 112.

[0037] The cell 104 _N comprises a SiC n-channel enhancement mode MOSFET MN 114 having gate node G, drain node D and source node S. The MOSFET gate terminal G is connected to the cell gate terminal 106 via a gate resistor RG. The MOSFET drain and source terminals D, S are connected to the cell drain and source terminals 108, 110 respectively. The MOSFET source terminal S is also connected to the cell cascading terminal 112 via a balance resistor RB and a balance capacitor CB in parallel.

[0038] A diode Do pointing towards the gate G (i.e. with a lower resistance towards the gate G) is connected between a first position between the balance capacitor / resistor and the MOSFET source terminal S, and a second position between the gate resistor RG and the MOSFET gate terminal G.

[0039] It will be noted that the cell 104 _N (aside from the MOSFET 114) is constructed from basic passive components (two resistors, one diode and one capacitor). This provides reliability to the design against variations in temperature, frequency and voltages spikes and doesn't include magnetic components that might produce EMI issues and add complexity.

[0040] The footprint and selection of these components can be optimized to achieve a compact design. Each cell can provide bipolar driving, gate protection and ON and OFF - state voltage balancing.

Operation

OFF - steady state operation

[0041 ] All MOSFET switches are off and sharing the supply voltage as Vs/n (note that n=2 in this embodiment). In the steady state, the supply voltage Vs acts to charge the balance capacitors CB.

TURN ON TRANSITION

[0042] The explained analysis in this section for the voltage and current waveforms and switching transitions are based on a clamped inductive load in the commonly used double pulse testing. The turn-on transition is divided into two main stages. [0043] It is assumed that before this stage starts, all switches are off and sharing the supply voltage as ^/ _n (note that n=2 in this embodiment) and the V _GS is at off driving voltage i.e. sub-threshold.

[0044] It will be noted that each capacitor CB is initially in a charged state from the supply voltage Vs.

[0045] A turn-on signal V _on _ _drtve is given by the gate driver 102 to the first MOSFET, M _N . The gate voltage starts rising passing the threshold voltage and the MOSFETs are still in the off state. The voltage across the MOSFET M _N , V _DS M(N) is at high level and the current I _{D M} (N) is zero. The gate current is dominated by the current through the resistor R _{G M} (Ny

Stage 2

[0046] At the beginning of stage 2, the current I _D starts to rise while the voltage V _{DS M} Q _N ^ of MOSFET M _N starts to fall bringing the source node of MOSFET M _N+1 to a lower voltage than its drain node.

[0047] At the same time, the capacitor C _{B M} Q _N ^ will have a new current path to discharge through the gate to source capacitance of M _N+1 allowing the 7 _GS MQV+I) ^to rise followed by a rise in its current I _D M(N+I) ^an d ^a fall in its voltage The discharging current of the capacitor C _{B M} (N) is determined by the change in voltage at the source node of M _N+1 , i.e. caused by the Rascon) M(N) ^an d the gate capacitance charge of M _N+1 , in addition, to the value of /? _{G M(JV+1)} .

ON - steady state operation

[0048] At steady state and when all MOSFETs are on, all of the MOSFETs are represented by their respective on-state resistances.

TURN OFF TRANSITION

[0049] Turn-off is divided into two stages.

Stage 3

[0050] Before this stage, it is assumed that all MOSFETs are in on-steady state and they are conducting the current from the top drain node to the bottom source node through their on-state resistances. At this stage, a negative driving voltage is generated by the driver, Voff-arive . and discharging the gate capacitance C _{GS MW} through R _{G M} (N>

Stage 4

[0051 ] The gate voltage VGSMQV) dropped to a level below the threshold voltage and the voltage V _{DS M} Q _N ^ starts rising while the current ID M(N) starts dropping turning off the MOSFET M(N) completely. The I _D through MOSFET M _N is commutated through the diode D _o , the gate resistance R _G M(N+I) ^an d the balance resistance RB M(N) to the source. The voltage drop across the diode Z>O (M+I) will start turning off the M _N+1 MOSFET.

Description of the second embodiment

Configuration

[0052] Referring to Figure 2 a cell circuit 204N is shown. All reference numerals are per the circuit 104 _N but 100 greater.

[0053] As an alternative embodiment to 1 04N. In this instance, the diode Do is supported with a Zener diode DZL having a forward direction from the gate G of MOSFET MN towards the source S of MOSFET MN.

Operation

[0054] It is known that higher junction temperature of the SiC MOSFETs leads to lower gate threshold voltage and a small voltage on the gate might turn on the MOSFET and causes a false turn on, in particular, SiC MOSFETs have less gate capacitance than Si. A negative gate drive voltage is recommended to achieve a stable and reliable off-state of the SiC MOSFETs. In this embodiment, the supply voltage reverse biases the Zener diode DZL, which results in a significant negative voltage (for example -5V) at the gate.

Description of the third embodiment

Configuration

[0055] Referring to Figure 3 a cell circuit 304N is shown. All reference numerals are per the circuit 204N but 100 greater. [0056] In this instance, the diode Do is replaced with a Zener diode DZH between the Zener diode DZL and the gate G. This Zener diode has a forward direction from the cascading terminal 212 towards the gate G of MOSFET MM.

Operation

[0057] The advantage of such an arrangement is that it provides protection forthe MOSFET gate from overvoltage while driving. The additional Zener diode will clip spikes or higher voltages. More than 20V for Si or SiC MOSFETs might damage them.

[0058] It will be noted that the additional Zener DZH provides a voltage drop from source to gate in the off-state (i.e. when forward biased with the supply current). The drop is typically around 0.5V to 0.7V. To reliably avoid false turn-on, the Zener DZL is employed to maintain the off-state voltage at below -3V (and preferably at -5V to -6V). Therefore if the diode DZH is utilised to avoid overvoltage, it is advantageous to pair it with Zener DZL to avoid false turn on in the off state.

Description of the fourth embodiment

[0059] The fourth embodiment is shown in Figures 4a and 4b.

Configuration

[0060] Referring to Figure 4a, there is shown a diagram of a fourth switching circuit 400 in accordance with the present invention. The circuit 400 comprises a MOSFET gate driver 402, first driving cell 404N, a second driving cell 404N+I and a third driving cell 404N+2.

[0061 ] It will be noted that each capacitor CB is initially in a charged state from the supply voltage Vs.

[0062] The MOSFET driver 402 is known in the art and will not be described in detail here, except to say that it is a circuit configured to provide pulse between V _on _ _arive and Vo//-drive

[0063] The cells 404 are almost identical and shown in more detail in Figure 4b. The final cell 404N+2 in this case may be different making it a "capping cell" which will be discussed below.

[0064] Each cell circuit 404N has four terminals: • Cell gate terminal 406;

• Cell drain terminal 408;

• Cell source terminal 410; and,

• Cascading terminal 412.

[0065] The cell 404N comprises an SiC n-channel enhancement mode MOSFET MN having gate node G, drain node D and source node S. The MOSFET gate terminal G is connected to the cell gate terminal 406 via a gate resistor RG. The MOSFET drain and source terminals D, S are connected to the cell drain and source terminals 408, 410 respectively. The MOSFET source terminal S is also connected to the cell cascading terminal 412 via a balance resistor RB and a balance capacitor CB in parallel.

[0066] A pair of Zener diodes DZL and DZH with opposed biases are connected in series (back-to-back) from a first position between the module capacitor / resistor and the MOSFET source terminal S, and a second position between the gate resistor RG and the MOSFET gate terminal G.

[0067] The cells 404 are similar to the cell 304N with the exception of the addition of a supply diode Ds connecting the gate terminal 406 to the cascading terminal 412, being biased towards the cascading terminal 412.

[0068] It will be noted that the cell 404 (aside from the MOSFET MN) is constructed from basic passive components (two resistors, two Zener diodes, one diode and one capacitor). This provides reliability to the design against variations in temperature, frequency and voltages spikes and doesn't include magnetic components that might produce EMI issues and add complexity.

[0069] The footprint and selection of these components can be optimized to achieve a compact design. Each cell can provide bipolar driving, gate protection and ON and OFF - state voltage balancing.

Operation

OFF - steady state operation (Fig. 4c) [0070] It is known that higher junction temperature of the SiC MOSFETs leads to lower gate threshold voltage and a small voltage on the gate might turn on the MOSFET and causes a false turn on, in particular, SiC MOSFETs have less gate capacitance than Si. A negative gate drive voltage is recommended to achieve a stable and reliable off-state of the SiC MOSFETs.

[0071 ] In the present embodiment the supply voltage is used to bias the Zener diodes which will result in a negative voltage which is in this case -5V. Fig. 4c shows the driving cell during the off state.

[0072] To bias the Zener diodes, I _z(min) should pass through the network (the path of which is shown in dotted line). Each cell 404 _N , 404 _N+1 etc., has two resistors (R _B ,R _G ) and two Zener diodes (D _ZL ,D _ZH ). In a proper steady state, one will be forward biased while the other is reversed resulting a negative gate-source.

TURN ON TRANSITION

[0073] The explained analysis in this section for the voltage and current waveforms and switching transitions are based on a clamped inductive load in the commonly used double pulse testing. The turn-on transition is divided into three main stages. Figs. 4d - 4f show the current paths during the turn-on transition stages for the three MOSFETs. Fig. 4h illustrates the gate to source voltage (V _GS ), the drain to source voltage (V _DS ) the drain currents (I _D ) and the gate resistance current (I _RG ) during the transition.

Stage 1 (Fig, 4d)

[0074] it is assumed that before this stage starts, all switches are off and the MOSFETSs are sharing the supply voltage as (where n is the total number of MOSFETs) and the V _GS is at a negative value (as explained above).

[0075] A turn-on signal V _on-drive is given by the gate driver 402 to the first MOSFET, M _N . The gate voltage starts rising passing the threshold voltage and the MOSFETs are still in off state. The voltage across the MOSFET M _N , V _{DS M(N)} is at high voltage and the current I _{D M(N)} is zero. The gate current is dominated by the current through the resistor R _{G M(N)} and 4h shows the current I _{RG M(N)} . The diode D _{S M(N)} is in off state as the voltage across the capacitor C _{B M(N )} is still higher than the drive voltage. The Zener diodes also will not operate as the drive voltage is lower than the protection threshold (+22V). Stage 2 (Fig, 4e)

[0076] at the beginning of stage 2, the current I _{D M(N)} through the MOSFET MN starts to rise while voltage V _{DS M(N)} of MOSFET M _N starts to fall bringing the source node of MOSFET M _N+1 to a lower voltage than the drain node which is illustrated by an overshoot of its voltage V _{DS M(N+1).}

[0077] At the same time, the capacitor C _{B M(N)} will have a new current path to discharge through the gate to source capacitance of M _N+1 allowing the V _{GS M(N+ 1)} to rise followed by a rise in its current I _{D M(N+1)} and a fall in its voltage V _{DS M(N+1)} . The discharging current of the capacitor C _{B M(N)} is determined by the change in voltage at the source node of M _N+1 , caused by the R _{ds(on) M(N)} and the gate capacitance charge of M _N+1 , in addition, to the value of R _{G M (N+1 )} . A basic illustration of the discharging circuit is in Fig. 4i.

[0078] Obviously, larger C _B produces higher peak current which is required for charging C _GS in a fast manner. However, large capacitance leads to longer time to balance the voltages at off-state and reach the steady state. Furthermore, it increases the switching loss when its cell MOSFET is on through its R _ds(on) .

Stage 3 (Fig, 4f)

[0079] similar to stage 2, when MOSFET M _N+1 is turned on, the voltage at the source node of M _{N +2} , idrops. Consequently, the capacitor C _{B M(N+1)} discharges and the time constant are determined by the value of the path capacitances, R _{G M(N+2)} and R _{B M(N+1)} . Larger values of R _G and R _B increase the time of discharge and keeps V _GS steadier and dissipate less power but it will disturb the turn-off operation dynamics.

ON - steady state operation (Fig. 4g)

[0080] At steady state and when all MOSFETs are on, Diode D _{s M(N)} is used to prevent V _{GS M(N+1)} to drop because its gate capacitances will discharge through R _{G M(N+1)} and R _{B M(N)} .T herefore, D _{s M(N)} keeps supplying minimal steady state current. Similar case for D _{s M(N+1 )} to keep V _{GS M(N+2)} at sufficient gate voltage level. Larger C _{B M(N)} capacitance provides steadier V _{GS M(N+1)} but it will deteriorate the turn-off time, which is critical in some applications, i.e. high voltage circuit breakers. [0081 ] As it is shown in Fig. 4g, the last driving cell for M _N+2 has no supply diode D _s because it will create a current path from the driver through D _{S M(N,N+1,..)} to the top drain node which has a low voltage due to the MOSFETs being on. This will draw a significant current and decrease the capability of the driver to keep all MOSFETs at on-state properly. For this reason, a "capping cell" is proposed which has the same structure but with no supply diode.

[0082] In an alternative embodiment, this diode may be provided, but simply disconnected from the cascading terminal 412 (Figure 4g shows this).

TURN OFF TRANSITION

[0083] Figs. 4j - 41 show the transition during the turn-off and it is divided into three stages.

Stage 4 (Fig, 4j)

[0084] Before this stage, it is assumed that all MOSFETs are in on-steady state and they are conducting the current IDS from the top drain node to the bottom source node through their on-state resistances. At this stage, a negative driving voltage is generated by the driver 402, V _off-drive , and discharging the gate capacitance C _{GS M(N)} through R _{G M(N)} as shown in Fig. 4h, the gate voltage drops.

Stage 5 (Fig, 4k)

[0085] The gate voltage V _{GS M(N)} drop s to a level below the threshold voltage and the voltage V _{DS M(N)} starts rising while the current I _{D M(N)} starts dropping turning off the MOSFET M(N) completely. The I _D through MOSFETs M (N + 1) and M (N + 2) is commutated through the Zener diodes D _{Z M(N+1)} , the gate resistance R _{G M(N+1)} and the balance resistance R _{B M(N)} to the source terminal as shown in 4k. This current will bias the Zener diode to produce a negative voltage equal to across C _{GS M(N+1)} . The applied voltage will start turning off the M(N + 1) MOSFET. It is worth mentioning here that R _{B M(N+1)} should be selected to pass the minimum Zener current, I _z(min) It is important to keep the switching time as short as possible to avoid higher dissipation when I _D flows through the Zener diodes.

Stage 6 (Fig, 41)

[0086] Similar to S5, after turning off M(N + 1) MOSFET, the current I _D will pass through a series of Zener diodes, R _G s and R _B s to the source node as shown in 41. This will bias the Zener diode D _{ZL M(N+2)} to turn off the (N + 2) MOSFET. Here the combination of R _B s should be able to pass the I _z(min) through all Zener diodes as we revert to the steady state off condition.

Description of the fifth embodiment

[0087] Referring to Figure 5, a driving cell 504 _N is shown. The cell 504 _N is identical to the cell 404 _N with the exception that a diode D _B is added in series with the resistor R _B . The diode D _B is added to reduce the impact of RB during turn on time.

Description of the sixth embodiment

[0088] Referring to Figure 6, a driving cell 604 _N is shown. The cell 604 _N is identical to the cell 504 _N with the exception that a further series diode-resistor pair D _Bd / R _Bd is added in parallel to the existing diode-resistor pair D _B / R _B .

[0089] The second pair is added to provide more controllability of the dynamics of balancing the voltage during the transient of turn-off state. R _Bd can be selected independently from R _B and adjusted to the desired settling time and overshoot.

Description of the seventh embodiment

[0090] Referring to Figure 7, a driving cell 704 _N is shown. The cell 704 _N is identical to the cell 604 _N with the exception that a photovoltaic driver PVD 730 has been added.

[0091 ] The PVD 730 comprises on a first side an LED 732 between the cell gate terminal 706 and a negative terminal 707. On a second side, a photovoltaic device 736 is provided between the gate terminal branch (between the gate terminal and the gate resistor 716) and a balance capacitor 720. The LED 732 is arranged such that when a current passes through it (i.e., with a positive or "on" voltage from the gate driver), it emits light to be received by the device 736 and converted into electric current from the gate terminal to the balance capacitor.

[0092] An LED resistor 734 is provided between the gate terminal 706 and the LED 732, and a diode 738 provided between the PV device 736 and the gate terminal. The diode 738 only permits current flow from the source terminal S to the gate terminal 706. Operation

[0093] An gate voltage V _G(N) (for example V _on-drive , or the voltage from the adjacent module) applied across terminals 706, 707 will activate the LED 732. The LED then emits light which produces a small voltage and current across the PV device 736. The resistor 734 limits the current flowing through the LED as a protection element. The diode 738 protects the PV device 736 from high reverse voltage which might damage it.

[0094] The device 736 will maintain the gate terminal voltage higher than the source terminal to ensure a stable on-state for extended periods of time. This is beneficial for very low switching frequency operation or steady state operation, for example in solid-state circuit breakers, modular multilevel converters and configurable batteries.

[0095] In another embodiment, several PV devices can be stacked in series and/or parallel to provide higher voltage or current to the gate.

Description of the eighth embodiment

[0096] The eighth embodiment is shown in Figure 8.

Configuration

[0097] The eighth embodiment is a switching circuit 800 in accordance with the present invention. The circuit 800 is substantially identical to the circuit 400. The main difference is that instead of each of the capacitors 802, 802', 802" having identical capacitance, the "top" balance capacitor (the one immediately adjacent the load) has a capacitance C _B ' higher than the others (which are generally identical). For example, if there are M modules, where N=1 , 2... n, then the nth module (the capping cell) will have a balance capacitor with a higher capacitance (and the absent diode as mentioned above). In the example of Figure 8, n=3 and therefore the capacitance of the balance capacitor of 804 ₁ = that of 804 ₂ =C _B , but that of 804 ₃ has a higher capacitance C _B '.

[0098] Capacitor 802 of 804 ₃ therefore carries a higher charge than those below, from the supply voltage V _s .

Operation

[0099] In once embodiment, C _B ' is 3-5 times the capacitance of C _B . This enables "soft switching" moving to the off state. [0100] The first MOSFET at 804 ₁ at the lower point will switch off first (as described above) bringing higher voltage at its terminal. As the MOSFETs switch off, the capacitor 802" will tend to absorb the bulk of the current meaning that the MOSFETs will be switching at close to zero current.

Variations

[0101 ] The above embodiments focus on SiC MOSFETS, although it will be understood that the invention may be applied to MOSFETs using other semiconductor materials, such as Si, and GaN.

[0102] The above embodiments also feature n-channel enhancement mode MOSFETs. It will be understood that other types of MOSFETs (p-channel and / or depletion mode) may be employed to suit the application.