Related Applications

[0001] This application claims the benefit of U.S. provisional patent application serial number 63/305,829, filed on February 2, 2022, the disclosure of which is hereby incorporated herein by reference in its entirety.

Field of the Disclosure

[0002] The technology of the disclosure relates generally to a power amplifier circuit in a power management circuit.

Background

[0003] The fifth generation (5G) system has been widely regarded as the next generation wireless communication system beyond the current third generation (3G) and fourth generation (4G) systems. In this regard, a 5G-capable wireless communication device is expected to achieve higher data rates, improved coverage range, enhanced signaling efficiency, and reduced latency.

[0004] The 5G-capable wireless communication device typically includes multiple transmitters to simultaneously transmit multiple 5G radio frequency (RF) signals under such schemes as Carrier Aggregation (CA) and Evolved-Universal Terrestrial Radio Access (E-UTRA) New Radio (NR) Dual Connectivity (DC) (ENDC). Since the transmitters typically transmit the 5G RF signals in a millimeter wave spectrum, the RF signals can be more susceptible to propagation attenuation and interference. To help mitigate propagation attenuation and maintain desirable data throughput, the 5G-capable wireless communication device typically employs multiple power amplifiers to amplify the RF signals to desired power levels before transmitting the RF signals from the transmitters. As such, it is desirable to ensure that the power amplifiers can operate with optimal efficiency, especially when the RF signals are transmitted with different peak-to-average ratios (PARs).

[0005] Embodiments of the disclosure relate to a hybrid power amplifier circuit. The hybrid power amplifier circuit includes a carrier amplifier and a peak amplifier coupled in parallel between a signal input and a signal output of the hybrid power amplifier circuit. In examples disclosed herein, the carrier amplifier and the peak amplifier are configured to collectively amplify a radio frequency (RF) signal from a time-variant input power to a time-variant output power based on an envelope tracking (ET) modulated voltage. A control circuit is provided in the hybrid power amplifier circuit to bias the peak amplifier based on a reference voltage (e.g., a battery voltage) to present a modulated load impedance to the carrier amplifier to thereby cause the carrier amplifier to operate in compression in response to an average of the ET modulated voltage being substantially equal to the reference voltage. By using the ET modulated voltage to cause the carrier amplifier to operate in compression, it is possible to improve efficiency of the carrier amplifier and the hybrid power amplifier circuit as a whole.

[0006] In one aspect, a hybrid power amplifier circuit is provided. The hybrid power amplifier circuit includes a signal input that receives an RF signal having a time-variant input power. The hybrid power amplifier circuit also includes a signal output that outputs the RF signal having a time-variant output power to a load circuit having an inherent load impedance. The hybrid power amplifier circuit also includes a carrier amplifier and a peak amplifier coupled in parallel between the signal input and the signal output. The carrier amplifier and the peak amplifier are configured to collectively amplify the RF signal from the time-variant input power to the time-variant output power based on an ET modulated voltage. The hybrid power amplifier circuit also includes a control circuit. The control circuit is configured to bias the peak amplifier based on a reference voltage to present a modulated load impedance to the carrier amplifier to thereby cause the carrier amplifier to operate in compression in response to an average of the ET modulated voltage being substantially equal to the reference voltage.

[0007] In another aspect, a power management circuit is provided. The power management circuit includes an ET integrated circuit (ETIC). The ETIC includes a switcher circuit. The switcher circuit is configured to generate a low- frequency current as a function of a battery voltage. The ETIC also includes a voltage circuit. The voltage circuit is configured to generate an ET modulated voltage based on an ET target voltage and the low-frequency current. The power management circuit also includes a hybrid power amplifier circuit. The hybrid power amplifier circuit includes a signal input that receives an RF signal having a time-variant input power. The hybrid power amplifier circuit also includes a signal output that outputs the RF signal having a time-variant output power to a load circuit having an inherent load impedance. The hybrid power amplifier circuit also includes a carrier amplifier and a peak amplifier coupled in parallel between the signal input and the signal output. The carrier amplifier and the peak amplifier are configured to collectively amplify the RF signal from the time-variant input power to the time-variant output power based on the ET modulated voltage. The hybrid power amplifier circuit also includes a control circuit. The control circuit is configured to bias the peak amplifier based on a reference voltage that corresponds to a reading of the battery voltage to present a modulated load impedance to the carrier amplifier to thereby cause the carrier amplifier to operate in compression in response to an average of the ET modulated voltage being substantially equal to the reference voltage.

[0008] Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures.

Brief Description of the Drawing Figures

[0009] The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

[0010] Figure 1 A is a schematic diagram of an exemplary power amplifier configured to amplify a radio frequency (RF) signal from an input power to an output power based on a modulated voltage; [0011] Figure 1 B is a graphic diagram of an exemplary power curve that illustrates a relationship between the output power and the modulated voltage in Figure 1 A;

[0012] Figure 2A is a schematic diagram of an exemplary hybrid power amplifier circuit configured according to an embodiment of the present disclosure to amplify an RF signal from a time-variant input voltage to a time-variant output power based on an envelope tracking (ET) modulated voltage and a modulated load impedance;

[0013] Figure 2B is a graphic diagram of an exemplary power curve that illustrates a relationship between the time-variant output power and the modulated voltage in Figure 2A;

[0014] Figure 3 is a schematic diagram illustrating an exemplary equivalent electrical model of the hybrid power amplifier circuit in Figure 2A;

[0015] Figure 4 is a schematic diagram of an exemplary power management circuit that incorporates the hybrid power amplifier circuit in Figure 2A; and [0016] Figure 5 is a schematic diagram of an exemplary user element wherein the power management circuit of Figure 4 can be provided.

Detailed Description

[0017] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

[0018] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. [0019] It will be understood that when an element such as a layer, region, or substrate is referred to as being "on" or extending "onto" another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being "over" or extending "over" another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly over" or extending "directly over" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0020] Relative terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical" may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

[0021] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and/or "including" when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

[0022] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0023] Embodiments of the disclosure relate to a hybrid power amplifier circuit. The hybrid power amplifier circuit includes a carrier amplifier and a peak amplifier coupled in parallel between a signal input and a signal output of the hybrid power amplifier circuit. In examples disclosed herein, the carrier amplifier and the peak amplifier are configured to collectively amplify a radio frequency (RF) signal from a time-variant input power to a time-variant output power based on an envelope tracking (ET) modulated voltage. A control circuit is provided in the hybrid power amplifier circuit to bias the peak amplifier based on a reference voltage (e.g., a battery voltage) to present a modulated load impedance to the carrier amplifier to thereby cause the carrier amplifier to operate in compression in response to an average of the ET modulated voltage being substantially equal to the reference voltage. By using the ET modulated voltage to cause the carrier amplifier to operate in compression, it is possible to improve efficiency of the carrier amplifier and the hybrid power amplifier circuit as a whole.

[0024] Before discussing the hybrid power amplifier circuit according to the present disclosure, starting at Figure 2A, an overview of an exemplary power amplifier circuit is first provided to help understand various factors that may affect operating efficiency of the power amplifier.

[0025] Figure 1 A is a schematic diagram of an exemplary power amplifier 10 configured to amplify an RF signal 12 from an input power PIN to an output power POUT based on a modulated voltage Vcc. The power amplifier 10 includes an output stage 14, which can include at least one transistor 16, as a non-limiting example. The transistor 16 includes a first electrode E1 , a second electrode E2, and a third electrode E3, which may be named differently depending on a type of the transistor 16. For example, if the transistor 16 is a bipolar junction transistor (BJT), then the first electrode E1 , the second electrode E2, and the third electrode E3 will be referred to as a base electrode, a collector electrode, and an emitter electrode, respectively. In contrast, if the transistor 16 is a complementary metal-oxide semiconductor (CMOS) transistor, the first electrode E1 , the second electrode E2, and the third electrode E3 will be referred to as a gate electrode, a source electrode, and a drain electrode, respectively.

[0026] Herein, the first electrode E1 is configured to receive a bias voltage VBIAS, the second electrode E2 is configured to receive the modulated voltage Vcc, and the third electrode E3 is configured to output the amplified RF signal 12 to a load circuit 18 (e.g., a transmitter circuit) at the output power POUT, which can be expressed in the equation (Eq. 1 ) below.

POUT = VOUT ² I ZLOAD (Eq. 1 )

[0027] In the equation (Eq. 1 ) above, VOUT represents an output voltage of the amplified RF signal 12 and ZLOAD represents a load impedance of the load circuit 18. The output voltage VOUT, on the other hand, is proportionally related to the modulated voltage Vcc, as illustrated in the equation (Eq. 2) below.

VOUT = Vcc - VE2-E3 (Eq. 2)

[0028] In the equation (Eq. 2), VE2-E3 represents a voltage drop between the second electrode E2 and the third electrode E3. From equation (Eq. 2), it can be seen that the output voltage VOUT will be substantially equal to the modulated voltage Vcc if the voltage drop VE2-E3 is reduced to, for example, a saturation voltage (e.g., 0.3 V) of the transistor 16. Under such condition, the power amplifier 10 will operate in compression with an improved efficiency. Based on the equations (Eq. 1 and Eq. 2) and given that the output voltage VOUT is substantially equal to the modulated voltage Vcc during compression, the output power POUT can be further expressed in the equation (Eq. 3) below.

POUT = (Vcc - VE2-E3) ² / ZLOAD ~ Vcc ² / ZLOAD (Eq. 3)

[0029] The modulated voltage Vcc is associated with a time-variant modulated voltage envelope 20, which varies over time between a maximum modulated voltage VCC-MAX and a minimum modulated voltage VCC-MIN. The difference between the maximum modulated voltage VCC-MAX and the minimum modulated voltage VCC-MIN is known as a peak-to-peak modulated voltage VCC-PKPK.

Similarly, the output voltage VOUT is associated with a time-variant output voltage envelope 22, which varies over time between a maximum output voltage VOUT-MAX and a minimum output voltage VOUT-MIN. The difference between the maximum output voltage VOUT-MAX and the minimum output voltage VOUT-MIN is known as a peak-to-peak output voltage VOUT-PKPK. When the power amplifier 10 operates in compression, the time-variant output voltage envelope 22 will be substantially similar to the time-variant modulated voltage envelope 20. Accordingly, the peak-to-peak output voltage VOUT-PKPK will be substantially equal to the peak-to- peak modulated voltage VCC-PKPK.

[0030] In a conventional linear power amplifier, the load impedance ZLOAD is kept constant. As such, based on the equation (Eq. 3), the output power POUT is primarily driven by the modulated voltage Vcc. Figure 1 B is a graphic diagram of an exemplary power curve 24 that illustrates a relationship between the output power POUT and the modulated voltage Vcc as expressed in the equation (Eq. 3). As shown in Figure 1 B, a magnitude of the peak-to-peak modulated voltage Vcc- PKPK is a function of peak-to-average ratio (PAR) of the RF signal 12. In other words, the peak-to-peak modulated voltage VCC-PKPK must be sufficiently large to avoid amplitude distortion when the output power POUT peaks. For example, the peak-to-peak modulated voltage VCC-PKPK is 3.9 V when the PAR is 10 dB and 2.8 V when the PAR is 6 dB. However, a larger peak-to-peak modulated voltage VCC-PKPK can reduce the efficiency of the power amplifier 10, especially when the output power POUT is off-peak. In this regard, it is desirable to reduce the peak- to-peak modulated voltage VCC-PKPK to help improve the efficiency of the power amplifier 10.

[0031] In this regard, Figure 2A is a schematic diagram of an exemplary hybrid power amplifier circuit 26 configured according to embodiments of the present disclosure to amplify an RF signal 28 from a time-variant input power PIN to a time-variant output power POUT based on an ET modulated voltage Vcc and a modulated load impedance ZM. AS described in detail below, the hybrid power amplifier circuit 26 is configured not only to operate in compression based on the ET modulated voltage Vcc, but also to reduce a peak-to-peak range of the ET modulated voltage Vcc based on the modulated load impedance ZM. AS an example, according to the equation (Eq. 3), the hybrid power amplifier circuit 26 can handle a larger peak of the time-variant output power POUT by reducing both the ET modulated voltage Vcc and the modulated load impedance ZM. In one aspect, by reducing the modulated load impedance ZM, it is possible to reduce the peak-to-peak range of the ET modulated voltage Vcc. In another aspect, by reducing the ET modulated voltage Vcc, it is possible to cause the hybrid power amplifier circuit 26 to operate in compression. As a result, the hybrid power amplifier circuit 26 can amplify the RF signal 28 to the time-variant output power POUT with an improved efficiency.

[0032] Figure 2B is a graphic diagram of an exemplary power curve 30 that illustrates a relationship between the time-variant output power POUT and the modulated voltage Vcc in Figure 2A. As shown by the power curve 30, when the PAR of the RF signal 28 is at 6 dB, for example, the peak-to-peak range (denoted as “V’CC-PKPK”) is lower than the peak-to-peak modulated voltage VCC- PKPK as previously shown in the power curve 24 of Figure 1 B.

[0033] With reference back to Figure 2A, the hybrid power amplifier circuit 26 includes a signal input 32 that receives the RF signal 28. The hybrid power amplifier circuit 26 also includes a signal output 34 that outputs the amplified RF signal 28 to a load circuit 36 (e.g., a transmitter circuit). [0034] In an embodiment, the hybrid power amplifier circuit 26 includes a carrier amplifier 38 (denoted as “carrier PA”) and a peak amplifier 40 (denoted as “peak PA”). The carrier amplifier 38 and the peak amplifier 40, which are coupled in parallel between the signal input 32 and the signal output 34, are configured to collectively amplify the RF signal 28 from the time-variant input power PIN to the time-variant output power POUT.

[0035] In a non-limiting example, each of the carrier amplifier 38 and the peak amplifier 40 can be identical or functionally equivalent to the power amplifier 10 in Figure 1 A. In this regard, the carrier amplifier 38 and the peak amplifier 40 can each include the output stage 14 in Figure 1 A. Accordingly, the carrier amplifier 38 receives the ET modulated voltage Vcc via the second electrode E2 in the respective output stage 14 and outputs a carrier output voltage VOUT-C via the third electrode E3 in the respective output stage 14. Likewise, the peak amplifier 40 receives the ET modulated voltage Vcc via the second electrode E2 in the respective output stage 14 and outputs a peak output voltage VOUT-P via the third electrode E3 in the respective output stage 14.

[0036] The hybrid power amplifier circuit 26 includes a carrier load-line transfer function (TF) circuit 42 (denoted as “TF-C”) and a peak load-line TF circuit 44 (denoted as “TF-P”). The carrier load-line TF circuit 42 is coupled to an output 46 (e.g., the third electrode E3 in the respective output stage 14) of the carrier amplifier 38 and the peak load-line TF circuit 44 is coupled to an output 48 (e.g., the third electrode E3 in the respective output stage 14) of the peak amplifier 40.

[0037] The hybrid power amplifier circuit 26 also includes an impedance inverter circuit 50 that is coupled between the carrier load-line TF circuit 42 and the peak load-line TF circuit 44. The impedance inverter circuit 50 is configured to create the modulated load impedance ZM based on an equivalent load impedance ZL-EQ. Herein, the equivalent load impedance ZL-EQ represents a total impedance presented to the impedance inverter circuit 50 by the load circuit 36, the peak load-line TF circuit 44, and the peak amplifier 40. [0038] In an embodiment, the carrier amplifier 38 is always active regardless of the time-variant output power POUT. In contrast, the peak amplifier 40 is only activated when the time-variant output power POUT is above a certain level. In the embodiment herein, the peak amplifier 40 is activated before the carrier amplifier 38 runs into compression. In this regard, the hybrid power amplifier circuit 26 is different from a conventional Doherty power amplifier, wherein a peak amplifier is not activated until a carrier amplifier runs into compression. [0039] The operational theory and principle behind the hybrid power amplifier circuit 26 can be better explained based on an equivalent electrical model. In this regard, Figure 3 is a schematic diagram illustrating an exemplary equivalent electrical model 52 of the hybrid power amplifier circuit 26 in Figure 2A.

Common elements between Figures 2A and 3 are shown therein with common element numbers and will not be re-described herein.

[0040] In addition to the carrier output voltage VOUT-C, the carrier amplifier 38 also produces a carrier output current IOUT-C. Likewise, the peak amplifier 40 also produces a peak output current /*IOUT-P in addition to the peak output voltage VOUT-P. As shown in the equations (Eq. 4 and Eq. 5), the carrier load-line TF circuit 42 transforms the carrier output voltage VOUT-C and the carrier output current IOUT-C into a time-variant carrier voltage envelope VM and a time-variant carrier current envelope IM, respectively. Further, as shown in the equations (Eq. 6 and Eq. 7), the peak load-line TF circuit 44 transforms the carrier output voltage VOUT-P and the carrier output current /*IOUT-P into a time-variant peak voltage envelope Vp and a time-variant peak current envelope /*lp, respectively.

VM = VOUT-C * TFC (Eq. 4) IM = IOUT-C I TFC (Eq. 5)

V = VOUT-P * TFP (Eq. 6) /*lp = /IOUT-P / TFP (Eq. 7)

[0041] In the equations above, TFC represents a carrier load-line transfer function implemented by the carrier load-line TF circuit 42 and TFP represents a peak load-line transfer function implemented by the peak load-line TF circuit 44. A relationship between the time-variant peak voltage envelope Vp and the timevariant carrier current envelope IM can be expressed in the equation (Eq. 8) below.

Vp = Ka * IM (Eq. 8)

[0042] In the equation (Eq. 8), K _a represents a coefficient of the impedance inverter circuit 50. The equivalent load impedance ZL-EQ, which represents the total impedance of the load circuit 36, the peak load-line TF circuit 44, and the peak amplifier 40, can be expressed as in the equation (Eq. 9) below.

ZL-EQ = ZLOAD / (1 - /*lp / ILOAD) (Eq. 9)

[0043] In the above equation (Eq. 9), ZLOAD represents an inherent load impedance ZLOAD of the load circuit 36 and LOAD represents a load current in the load circuit 36. From the equation (Eq. 9), it can be seen that when /*lp = 0, which is an indication that the peak amplifier 40 is deactivated, the equivalent load impedance ZL-EQ will only include the inherent load impedance ZLOAD.

However, when /*lp = ¹ /2 ZLOAD, for example, the equivalent load impedance ZL-EQ will change to 2*ZLOAD. In this regard, the equivalent load impedance ZL-EQ will increase when the peak amplifier 40 is activated.

[0044] The impedance inverter circuit 50 is configured to convert the equivalent load impedance ZL-EQ into the modulated load impedance ZM in accordance with the equation (Eq. 10) below.

[0045] From the equation (Eq. 10), it can be seen that the modulated load impedance ZM will decrease when the equivalent load impedance ZL-EQ increases. In this regard, it is possible to reduce the modulated load impedance ZM by activating the peak amplifier 40.

[0046] The time-variant carrier voltage envelope VM can be determined based on the equation (Eq. 1 1 ) below.

VM = 4 * ZLOAD * (IM - ¹ /2lp) (Eq. 11 )

[0047] A pair of derivative equations can be derived from the equation (Eq. 1 1 ), which are expressed below in equations (Eq. 12 and Eq. 13).

AVM = 4 * ZLOAD * (AIM - ¹ /2AIP) (Eq. 12) avg(VM) = 4 * ZLOAD * (avg(lM) - ¹ /2avg(lp)) (Eq. 13)

[0048] In the equation (Eq. 12), AVM, AIM, and Alp represent a change in the time-variant carrier voltage envelope VM, a change in the time-variant carrier current envelope IM, and a change in the time-variant peak current envelope Ip, respectively. In the equation (Eq. 13), avg(VM), avg(lM), and avg(lp) represent an average of the time-variant carrier voltage envelope VM, an average of the timevariant carrier current envelope IM, and an average of the time-variant peak current envelope Ip, respectively.

[0049] When Alp < 2AIM, AVM will be greater than zero. In this regard, the time-variant carrier voltage envelope VM is increasing, but at a lower rate (as illustrated by the power curve 30 in Figure 2B). According to previous discussions in Figure 1 A, when the carrier amplifier 38 operates in compression, the ET modulated voltage Vcc will be substantially equal to the carrier output voltage VOUT-C (Vcc « VOUT-C). Thus, the ET modulated voltage Vcc can be related to the time-variant carrier voltage envelope VM in the equation (Eq. 14) below based on the equations (Eq. 2 and Eq. 4).

Vcc = VOUT-C + VE2-E3 = VM / TFC (Eq. 14) [0050] Further, a set of relationships between the ET modulated voltage Vcc and the time-variant carrier voltage envelope VM can be established in the equations (Eq. 15 and 16) below based on the equations (Eq. 12-14). Accordingly, the ET modulated voltage Vcc can be generated to track the timevariant carrier voltage envelope VM with a reduced peak-to-peak range to drive the carrier amplifier 38 into compression.

AVcc = 4 * ZLOAD * (AIM - ¹ /2AIP) I TFC (Eq. 15) avg(Vcc) = 4 * ZLOAD * (avg(lM) - ¹ /2avg(lp)) I TFC (Eq. 16)

[0051] With reference back to Figure 2A, the hybrid power amplifier circuit 26, can be a field-programmable gate array (FPGA), as an example. In an embodiment, the control circuit 54 can be configured to bias the peak amplifier 40 based on a reference voltage VREF that may be provided (e.g., by a transceiver circuit) in a voltage indication signal 56. Accordingly, the control circuit 54 can determine a bias voltage VBIAS to bias the peak amplifier to generate the peak output current /*IOUT-P at an appropriate level to thereby present the modulated load impedance ZM to the carrier amplifier 38 and cause the carrier amplifier 38 to operate in compression in response to the average of the ET modulated voltage avg(Vcc) being substantially equal to the reference voltage VREF. Herein, the average of the ET modulated voltage avg(Vcc) is said to be substantially equal to the reference voltage VREF when VREF - avg(Vcc) ± 0.05 V.

[0052] In an embodiment, the hybrid power amplifier circuit 26 can include a bias lookup table (LUT) 58 that correlates different levels of the reference voltage VREF with different levels of the bias voltage VBIAS. In this regard, the control circuit 54 may retrieve an appropriate bias voltage VBIAS based on the reference voltage VREF received via the voltage indication signal 56 and apply the retrieved bias voltage VBIAS to the peak amplifier 40.

[0053] The hybrid power amplifier circuit 26 can include a splitter circuit 59 that is coupled to the signal input 32. In an embodiment, the splitter circuit 59 splits the RF signal 28 into a carrier RF signal 28C and a peak RF signal 28P. The carrier RF signal 28C and the peak RF signal 28P are amplified respectively by the carrier amplifier 38 and the peak amplifier 40 and then recombined into the RF signal 28 at the signal output 34.

[0054] In an embodiment, the ET modulated voltage Vcc can be generated in an ET integrated circuit (ETIC) based on a battery voltage and the reference voltage VREF can correspond to a reading of the battery voltage. In this regard, Figure 4 is a schematic diagram of an exemplary power management circuit 60 that incorporates the hybrid power amplifier circuit 26 in Figure 2A. Common elements between Figures 2A and 4 are shown therein with common element numbers and will not be re-described herein.

[0055] The power management circuit 60 includes an ETIC 62. The ETIC 62 includes a voltage circuit 64 and a switcher circuit 66. The voltage circuit 64 includes a voltage amplifier 68 (denoted as “VA”) coupled in series with an offset capacitor COFF. The voltage amplifier 68 is configured to generate an initial ET modulated voltage VAMP based on an ET target voltage VTGT and a supply voltage VSUP. In an embodiment, the ET target voltage VTGT tracks the time-variant carrier voltage envelope VM in the hybrid power amplifier circuit 26. Accordingly, the voltage amplifier 68 can generate the initial ET modulated voltage VAMP to also track the time-variant carrier voltage envelope VM. The offset capacitor COFF is configured to raise the initial ET modulated voltage VAMP by an offset voltage VOFF to generate the ET modulated voltage Vcc (Vcc = VAMP + VOFF). In this embodiment, the offset voltage VOFF is a constant voltage (e.g., 0.8 V). As a result, the ET modulated voltage Vcc also tracks the time-variant carrier voltage envelope VM.

[0056] The switcher circuit 66 includes a multi-level charge pump (MCP) 70, which can be a direct-current (DC)-to-DC (DC-DC) buck-boost converter, as an example. The MCP 70 is configured to generate a low-frequency voltage VDC at multiple levels based on a battery voltage VBAT. In a non-limiting example, the MCP 70 can operate in a buck mode to generate the low-frequency voltage VDC at OXVBAT or 1 XVBAT, or in a boost mode to generate the low-frequency voltage VDC at 2XVBAT. The MCP 70 is coupled in series to a power inductor Lp, which is configured to induce a low-frequency current IDC based on the low-frequency voltage VDC. In an embodiment, the low-frequency current IDC can be used to modulate the offset voltage VOFF across the offset capacitor COFF.

[0057] In an embodiment, the control circuit 54 in the hybrid power amplifier circuit 26 receives the voltage indication signal 56 that indicates a reading of the battery voltage VBAT. Accordingly, the control circuit 54 retrieves an appropriate bias voltage VBIAS from the bias LUT 58 to bias the peak amplifier 40. As such, the carrier amplifier 38 will operate in compression, and therefore with a higher efficiency, when the average of the ET modulated voltage avg (Vcc) is substantially equal to the battery voltage VBAT. Further, the MCP 70 can operate in the buck mode to generate the low-frequency voltage VDC at the battery voltage VBAT, thus making it possible to improve the efficiency of the switcher circuit 66 as well.

[0058] The power management circuit 60 of Figure 4 can be provided in a user element to enable memory distortion neutralization according to embodiments described above. In this regard, Figure 5 is a schematic diagram of an exemplary user element 100 wherein the power management circuit 60 of Figure 4 can be provided.

[0059] Herein, the user element 100 can be any type of user elements, such as mobile terminals, smart watches, tablets, computers, navigation devices, access points, and like wireless communication devices that support wireless communications, such as cellular, wireless local area network (WLAN), Bluetooth, and near field communications. The user element 100 will generally include a control system 102, a baseband processor 104, transmit circuitry 106, receive circuitry 108, antenna switching circuitry 110, multiple antennas 112, and user interface circuitry 114. In a non-limiting example, the control system 102 can be a field-programmable gate array (FPGA), as an example. In this regard, the control system 102 can include at least a microprocessor(s), an embedded memory circuit(s), and a communication bus interface(s). The receive circuitry 108 receives radio frequency signals via the antennas 112 and through the antenna switching circuitry 110 from one or more base stations. A low noise amplifier and a filter cooperate to amplify and remove broadband interference from the received signal for processing. Downconversion and digitization circuitry (not shown) will then downconvert the filtered, received signal to an intermediate or baseband frequency signal, which is then digitized into one or more digital streams using analog-to-digital converter(s) (ADC).

[0060] The baseband processor 104 processes the digitized received signal to extract the information or data bits conveyed in the received signal. This processing typically comprises demodulation, decoding, and error correction operations, as will be discussed in greater detail below. The baseband processor 104 is generally implemented in one or more digital signal processors (DSPs) and application specific integrated circuits (ASICs).

[0061] For transmission, the baseband processor 104 receives digitized data, which may represent voice, data, or control information, from the control system 102, which it encodes for transmission. The encoded data is output to the transmit circuitry 106, where a digital-to-analog converter(s) (DAC) converts the digitally encoded data into an analog signal and a modulator modulates the analog signal onto a carrier signal that is at a desired transmit frequency or frequencies. A power amplifier will amplify the modulated carrier signal to a level appropriate for transmission, and deliver the modulated carrier signal to the antennas 112 through the antenna switching circuitry 110. The multiple antennas 112 and the replicated transmit and receive circuitries 106, 108 may provide spatial diversity. Modulation and processing details will be understood by those skilled in the art.

[0062] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.