The present invention relates to electronic devices including ferroelectric polymers and to the use of ferroelectric materials in dielectric layers in electronic devices.

More particularly, the invention relates to a method for depositing a conductive polymer layer onto a hydrophobic layer and the devices thus obtained.

In the past years, much effort has been put in development of all-polymer technology. Functional electronic circuit devices such as transistors, inverters and code generators have been studied. All-polymer electromechanical systems for sensing or actuation are also being developed.

Semi-crystalline polymers with an asymmetric unit cell in their crystalline part are pyroelectric, piezoelectric and often ferroelectric, i. e. they are active polymers. The most frequently encountered polymers within this context are based on (partly) fluorinated monomers such as for example vinylidenedifluoride (VDF) and trifluoroethylene (TrFE).

While the pyroelectric and piezoelectric properties make them suitable for use in sensor and actuator devices of all sorts, the ferroelectric property is suited for non-volatile memory devices that may find use in either high-end Si-based technology or low-end high volume polymer electronics.

Ferroelectric materials are characterized by a spontaneous polarization in the absence of an electric field, that can be reversed by application of an electric field lower than the materials breakdown field. Spontaneous polarization in a ferroelectric material arises from a non-centrosymmetric arrangement of ions or molecular dipoles in its unit cell that produces a net electric dipole moment. Generally, a temperature lower than the melting temperature or decomposition temperature, a so-called Curie temperature exists above which the ferroelectric phase is transformed into a paraelectric phase resulting in loss of the ferroelectric properties. The upper temperature limit determines the applicability of the material with respect to specification.

When an alternating electric field is applied to a ferroelectric material the polarization shows a hysteresis behavior with the applied field. In an initial stage, ferroelectric domains that are oriented favorably with respect to the applied field direction grow at the expense of other domains. This continues until total domain growth and reorientation have occurred. At this stage, the material has reached its saturation polarization (Ps). If the electric field is then removed, some of the domains do not return to their random configurations and orientations. The polarization at this stage is called the remnant polarization (Pr). The strength of the electric field required to return the polarization to zero is the coercive field (Ec).

A typical ferroelectric hysteresis loop is illustrated in Fig. 1, showing surface charge density D in function of applied electric field E. At zero applied field E=0, there are two states of polarization, Pr. Furthermore, these two states of polarization are equally stable. Either of these two states could be encoded as a Boolean"1"or"0"of a memory and since no external field is required to maintain these states, the memory device is non-volatile.

To switch the state of the device, a threshold field with an absolute value larger than Ec is required. In order to reduce the threshold field Ec for a given ferroelectric material, the ferroelectric material needs to be processed in the form of thin films (preferably with a thickness less than 2 micron).

A variety of inorganic and organic ferroelectric materials exists. Among the organic ones, ferroelectric polymers are most well known. Ferroelectric polymers or oligomers may for example be odd numbered nylons, polyvinylidene cyanide p (VCN) or polyvinylidenefluoride p (VDF). From the polymers known to date, especially a group of fluorine containing materials, to which p (VDF) having the chemical structure (CH2-CF2) n belongs, is preferred due to advantageous properties, such as: high remnant polarization and relatively low coercive field in films obtained directly form spincoating. Also their ferroelectric behavior meets temperature specifications, i. e. the ferroelectricity is retained at temperatures in between-20 and 150 C. Especially materials with combinations of VDF (CH2-CF2), with TrFE (CHF-CF2) and/or TFE (CF2-CF2) such as for example the random copolymers (CH2-CF2) n-(CHF-CF2) m or (CH2-CF2) n- (CF2-CF2) m have excellent ferroelectric and film forming properties. It is further noted here that in general any material that has a crystalline phase with a crystal structure belonging to an asymmetric space group could possess ferroelectric properties as long as the electrical breakdown field is higher than the required polarization reversal or switching field (related to coercive field).

Although ferroelectric liquid crystalline polymers can be used for non-volatile display manufacture, the remnant polarization Pr is generally low (-5-10 mC/m2), being dependent on a dipole moment from a large molecule. This may be too low for memory applications. In addition, operating conditions will be very temperature sensitive due to the liquid crystal properties. For memory application one likes to have stable properties at temperatures in between approximately-20 to 150 C. Therefore, in case of non-volatile memory cells, organic ferroelectric materials, for example as mentioned above, are preferably used as a ferroelectric layer.

For plastic electronics, it is proposed that a combination of such active polymers and polymer electrodes that can carry a relatively high current density (such as PANI/CSA or PEDOT/PSS), will yield an all-polymer ferroelectric memory function that is non-volatile and electrically erasable (re) programmable.

However, it is not trivial to incorporate these materials into an all-polymer device. The active polymers have excellent solubility in common polar organic solvents such as for example acetone, possess poor wetting properties and have low adhesion to other materials and are rather inert towards chemicals and radiation. Hence, addition and patterning of an electrode layer on top of an active polymer layer will pose problems that have to be overcome.

In WO 02/43071 a ferroelectric memory circuit comprising a ferroelectric memory cell in the form of a ferroelectric polymer thin film and first and second electrodes, contacting the ferroelectric polymer thin film at opposite surfaces thereof, is described. In a specific example of the method in WO 02/43071, a conducting polymer electrode layer is deposited on top of a ferroelectric thin film by spin coating from a H. C. Starck Baytron-P solution. A certain amount of surfactant must be added to the H. C. Starck Baytron-P solution to allow a uniform and smooth PEDOT/PSS film formation, because the ferroelectric thin film shows only poor wetting properties. The deposition process is followed by a heat treatment at 100°C for 2-10 minutes for increasing the conductivity of PEDOT/PSS.

However, the certain amount of surfactant, and its nature with respect to non- ionic character, to be added to the spincoating solution in WO 02/43071 is not specified and no solution is provided for solving the problem of the poor wetting properties of ferroelectric polymers.

Therefore, a solution is needed by which a conductive polymer layer can be deposited from high surface energy solutions, such as for example aqueous spincoating solutions, onto a hydrophobic or low surface energy layer or substrate such as for example a

ferroelectric polymer layer, and which does not suffer from the disadvantage of poor wetting and low adhesion.

It is an object of the present invention to provide a method for applying a conductive polymer layer onto a hydrophobic polymer layer which does not show the disadvantages of the method of the prior art.

The above objective is accomplished by a method and device according to the present invention.

The present invention provides a method for depositing a polymer layer onto a hydrophobic surface from an aqueous solution comprising the polymer and a surface tension reducing co-solvent, the method comprising: depositing said polymer layer onto the hydrophobic surface from the aqueous solution, and -allowing the water and the surface tension reducing solvent to evaporate from the aqueous solution, whereby the surface tension reducing solvent is selected so that it evaporates slower than water from the aqueous solution. The present invention includes an active evaporation step, i. e. the application of heat to evaporate the water of the aqueous solution as well as the surface tension reducing solvent.

The polymer layer may for example be a conductive polymer layer and may for example be a PEDOT/PSS layer.

The hydrophobic organic surface may for example be a hydrophobic organic surface and may for example be a ferroelectric polymer layer such as e. g. a VDF/TrFe layer.

The surface tension reducing solvent may comprise n-butanol. n-butanol may have a concentration below the concentration at which it does not fully dissolve in order to obtain a solution with one phase only. The concentration may be lower than 3%. The concentration may be higher than 0. 1 %, higher than 0.2%, higher than 0.5, higher than 1%, preferably be 3% n-butanol, but the n-butanol solution may also have another concentration such as e. g. 2.5% n-butanol. The surface tension reducing agent may be a surfactant.

The method of the present invention may furthermore comprise : adding a cross linking agent to the conductive polymer solution exposing at least part of the conductive polymer after deposition to radiation with UV light for cross linking at least said part of the conductive polymer.

The cross linking agent may for example be a diazonium salt.

The present invention furthermore provides an electronic device comprising a ferroelectric polymer layer and a conductive polymer layer on top of the ferroelectric polymer layer. The conductive polymer layer on top of the ferroelectric polymer layer can be obtained by the method according to the present invention.

The electronic device according to the present invention may for example comprise a control electrode and a first and second main electrode. The device may for example be an all-polymer transistor comprising a gate electrode, a source and a drain. In one embodiment of the invention the device may be an all-polymer capacitor comprising a first and second electrode. In another embodiment, the device may comprise an ! T-IC cell.

These and other characteristics, features and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, which illustrate, by way of example, the principles of the invention. This description is given for the sake of example only, without limiting the scope of the invention. The reference figures quoted below refer to the attached drawings.

Fig. 1 shows a graph illustrating surface charge density D on a capacitor versus an applied electric field E. (M. E. Lines and A. M. Glass in'Principles and Applications of Ferroelectrics and Related Materials) Fig. 2-8 illustrate subsequent steps in the processing of an all-polymer device according to an embodiment of the present invention.

Fig. 9 shows ferroelectric hysteresis curves of a PEDOT/PSS-VDF/TrFE- PEDOT/PSS stack before and after annealing.

Fig. 10 shows a device comprising a ferroelectric transistor and a via contact between top and bottom electrode layer according to an embodiment of the present invention.

In the different figures, the same reference figures refer to the same or analogous elements.

The present invention will be described with respect to particular embodiments and with reference to certain drawings but the invention is not limited thereto but only by the claims. The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn on scale for illustrative purposes. Where the term"comprising"is used in the present description and claims, it does not exclude other elements or steps. Where an indefinite or definite article is

used when referring to a singular noun e. g."a"or"an","the", this includes a plural of that noun unless something else is specifically stated.

Furthermore, the terms first, second, third and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the invention described herein are capable of operation in other sequences than described or illustrated herein.

Moreover, the terms top, bottom, over, under and the like in the description and the claims are used for descriptive purposes and not necessarily for describing relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the invention described herein are capable of operation in other orientations than described or illustrated herein.

The present invention proposes a method for the incorporation of pyroelectric, piezoelectric and/or ferroelectric polymers in all-polymer electronic technology with the aim of producing electroactive devices. In particular, ferroelectric capacitors or transistors are envisaged because this will result in a memory function within existing polymer electronics technology. However, the method of this invention may also be used for processing other all- polymer devices. Thus, the method of the invention may be used to process devices where a polymer layer has to be deposited onto a hydrophobic organic layer.

The examples and embodiments that will be described hereinafter are only for the ease of explaining and are not limiting for the present invention.

In a first embodiment, the subsequent process steps of the manufacturing of an all-polymer transistor, comprising a gate electrode 4 and a source 8 and drain 9 electrode (see Fig. 8), according to the present invention are discussed. First, a substrate 1 is provided. In embodiments of the present invention, the term"substrate"may include any underlying material or materials that may be used, or upon which a device, a circuit or an epitaxial layer may be formed. In other alternative embodiments, this"substrate"may include a semiconductor substrate such as e. g. a doped silicon, a gallium arsenide (GaAs), a gallium arsenide phosphide (GaAsP), an indium phosphide (InP), a germanium (Ge), or a silicon germanium (SiGe) substrate. The"substrate"may include for example, an insulating layer such as a Si02 or an Si3N4 layer in addition to a semiconductor substrate portion. Thus, the term substrate also includes silicon-on-glass, silicon-on sapphire substrates. The term "substrate"is thus used to define generally the elements for layers that underlie a layer or

portions of interest. Also, the"substrate"may be any other base on which a layer is formed, for example a glass or metal layer. The substrate I may optionally be planarized. This may be done by for example depositing a planarization layer 2 of a photoresist, which may for example be an epoxy-or novolac-based polymer, onto the substrate 1.

Next, a first conductive layer 3 is deposited on top of the planarization layer 2 (see Fig. 2), or in case the substrate 1 is not planarized, on top of the substrate 1. Deposition of the first conductive layer 3 may be performed by means of for example spincoating, dropcasting, doctor blade, lamination of a prefabricated composite film, etc. The first conductive layer 3 may for example be a polymer, e. g. a conductive polymer layer such as e. g. polyaniline doped with camphor sulfonic acid (PANI/CSA), poly (3,4- etylenedioxythiophene) doped with poly (4-styrenesulfonat) (PEDOT/PSS) or any other suitable conductive polymer, or may be a metal such as for example copper, ITO (indium tin oxide), or may be any suitable conductive material. The thickness of the first conductive layer 3 depends on the properties of the material that is used, such as for example the sheet resistance, and may for example be 100 nm.

Then, the first conductive layer 3 may be patterned to form a bottom (gate) electrode 4 (Fig. 3). Patterning may be performed by means of for example standard photolithography.

The photolithography process comprises the following subsequent steps. First, a photoresist layer is applied on top of the first conductive layer 3, e. g. by means of spincoating. The photoresist layer may for example have a thickness of a few urn and may be made of any suitable polymer that can be used as a photoresist, such as for example poly (vinylcinnamate) or novolak-based polymers. Thereafter, a mask is applied to align a pattern onto the substrate 1. The photoresist layer is then illuminated through the mask e. g. by means of UV light. After illumination the photoresist is developed by which either the illuminated parts of the photoresist (positive resist) or the non-illuminated parts of the photoresist (negative resist) are removed, depending on which type of photoresist has been used. Patterning of the first conductive layer 3 is then performed using the developed photoresist layer as a mask, after which the remaining parts of the photoresist layer are removed, typically by using an organic solvent. The result is shown in Fig. 3.

However, in the specific case the first conductive layer 3 is a conductive polymer layer, patterning may preferably be performed by using methods as described in W0200120691 (e. g. PEDOT) and US6429450B1 (e. g. PANI-initiator).

In a subsequent step, a ferroelectric layer 5 is deposited on top of the control electrode 4 (Fig. 4). The ferroelectric layer 5 may be deposited by means of for example spincoating from a solution. The ferroelectric layer 5 may for example be a ferroelectric polymer layer and may for example be based on fluorinated polyolefins such as for instance random copolymers of vinylidenedifluoride (VDF) with trifluoroethylene (TrFE), tetrafluoroethylene or chlorotrifluoroethylene or it may be based on other (partly) fluorinated polymers. However, other ferroelectric polymers, such as for example nylons, cyanopolymers (polyacrylonitriles), poly (vinylidene cyanide) and other polymers with a cyano group in the side chain), polyureas, polythioureas and polyurethanes, may also be used. Other suitable deposition techniques may also be used, such as for example drop casting, Doctor Blade, lamination of a prefabricated composite film, spraying or printing.

Ferroelectric materials are discussed in"Principles and Applications of Ferroelectrics and related materials", M. E. Lines and A. M. Glass, Oxford Press, 2001 and in "Ferroelectric polymers, chemistry, physics and applications", edited by Hari Singh Nalwa, Marcel Dekker, Inc 1995. For a general list of ferroelectric materials see the Landolt- Bernstein series, Springer-Verlag Heidelberg Group III ; Condensed Matter; Volume 16 : Ferroelectrics and related substances (1982) and Volume 36: Ferroelectrics and related substances (2002).

The ferroelectric layer 5 may have a thickness of for example 2000 nm or lower. Preferably, the thickness of the ferroelectric layer 5 is in between 30 and 500 nm. The ferroelectric layer 5 may optionally be patterned to form contact holes 6 to the first conductive layer 3 where necessary (see Fig. 5). If possible, and this depends on the kind of material used for the ferroelectric layer 14, the patterning may be carried out by means of standard photolithography as described in case of patterning of the first conductive polymer layer 3.

In the specific case the device is intended for use in memory applications it is important that the remnant polarization Pr of the ferroelectric polymer layer 5 is as high as possible. Hence, one must turn to materials having a high density of large dipole groups such as is the case in fluorine containing polymers, which have a remnant polarization > 10 mC/m2, for example 100 mC/m2. The upper limit may be determined by the exact application.

Another important reason for Pr not to be too low is that the stability of the stored states (polarisations) will be at least partly dependent on it. In this respect also the coercive field is important. A too high Ec results in high switching voltages (generally 2 x Ec

x layer thickness for polarization saturation). However, a too low Ee may result in manifestation of detrimental polarization fields within the capacitors when connected to other circuitry having parasitic capacitance.

Thus, although other ferroelectric polymers or molecules exist, fluorine containing materials seem to have the most beneficial properties in case of memory applications, because they show high remnant polarization. Examples of fluorinated polymers may for example be (CH2-CF2) n, (CHF-CF2) n (CF2-CF2) n or combinations thereof to form (random) copolymers such as for example: (CH2-CF2) n- (CHF-CF2) m or (CH2-CF2) n- (CF2- CF2) m- However, in case fluorinated polymers, or more in general haloginated polymers, are used for the ferroelectric polymer layer 5, application of normal photolithography for patterning is difficult, because a fluorinated polymer dissolves in the polar organic solvents commonly used to remove the photoresist, which results in a complete lift off of all layers on top. In this case, the ferroelectric polymer layer 5 may yet be patterned by means of photolithography by addition of a photosensitive cross linker, such as e. g. bisazide, to the fluorinated polymer spincoat solution. After spincoating of the ferroelectric polymer layer 5 with the cross linker, the ferroelectric polymer layer 5 is irradiated with UV light through a mask that leads to a partially non-soluble layer. Non-solubility of the ferroelectric polymer layer 5 is accomplished by means of cross linking of the polymer. The parts of the ferroelectric polymer layer 5 which are not illuminated, and which thus do not cross-link, may be subsequently removed by washing with for example acetone leaving a patterned film that may be annealed to increase the ferroelectric properties of the layer 5. The cross linking does not substantially alter the ferroelectric switching behavior whereas it greatly improves stack integrity, because upon further processing the cross linked ferroelectric polymer layer 5 will not dissolve. In the above described photolithography process, all cross linking materials may be used, on one condition that they do not fall apart into charged particles or species reactive towards the polymer during exposure. Examples are known where heat activated peroxides are used to cross link. These however result in charged side products, which is detrimental for the memory characteristics device that has been processed.

Although in this embodiment, ferroelectric polymers have been used, the method of the present invention may also apply other polymers like piezoelectric polymers or pyroelectric polymers. Furthermore, also inorganic ferroelectric polymers may be used as a dielectric layer in the devices according to the present invention.

In a next step, a second conductive layer 7, which may be a conductive polymer layer, is deposited on top of the ferroelectric layer 5 (Fig. 6). This may be performed by means of for example spincoating, dropcasting, doctor blade, lamination of a prefabricated composite film, etc. However, in case the ferroelectric layer 5 is hydrophobic and forms a surface with low surface energy, deposition of the second conductive polymer layer 7 onto the hydrophobic ferroelectric layer 5 may results in severe dewetting when deposition takes place from high surface energy (hydrophilic or aquous) solutions as is the case of the H. C.

Starck Baytron P PEDOT/PSS solutions. Therefore, the surface needs to be made hydrophilic (increased surface energy) or a surface energy lowering agent needs to be used during spincoating. Known methods for making a surface hydrophilic are for example implantation of ions in or oxidation of the hydrophobic surface E. T. Kang Y Zhang, Surface modification of fluoropolymers via molecular design, Adv. Mater. 2000,12 (20) 148 l-l 494.

However, this gives rise to damage of the surface or unwanted ionic contamination. Hence, this would lead to a changed interface between the ferroelectric polymer layer 5 and the second conductive polymer layer 7.

Therefore, the method of the present invention proposes modification of the solution, from which the second conductive polymer layer 7 is deposited, in order to overcome the disadvantage of the prior art methods. Wettability properties of the solution may be improved through addition of a surface tension reducing solvent which may be any solvent that is miscible with water, evaporates slower than water and does not attack the ferroelectric layer 5 within the time period of the processing of the device. Furthermore, the surface tension reducing solvent or also called co-solvent, must be polar enough to enhance the wettability of the hydrophobic surface but may not be too polar since then it will not mix with water in large enough quantities. The co-solvent may not form an azeotrope with water, otherwise water will result as the single solvent at the final stages of the deposition of the conductive polymer layer. Examples of co-solvents which may be used in the present invention are 3%. n-butanol or a soap like agent. However, n-butanol with other concentration percentages may also be used, such as e. g. 2,5% butanol.

The second conductive polymer layer 7 may have a thickness which is comparable to the thickness of the first conductive (polymer) layer 3 and which is also dependent on the material used and on the required resistance or velocity of the device. The second conductive polymer layer 7 may then be patterned to form source 8 and drain 9 by means of for example standard photolithography. However, the second conductive polymer layer 7 may also be patterned by means of photolithography in which a cross linking agent is

added to the solution from which the second conductive polymer layer 7 is deposited. The cross linking agent may for example be a diazonium salt. After depositing the second conductive polymer layer 7, the layer 7 is at least partially exposed, e. g. through a mask, to radiation with UV light. The exposed parts of the second conductive polymer layer 7 are hereby cross linked and hence made insoluble. The non-exposed parts of the second conductive layer 7 may then be removed by solving them in a suitable solvent. The result after patterning is illustrated in Fig. 7. Furthermore, patterning may be performed by using methods as described in W0200120691 (e. g. PEDOT) and US6429450B1 (e. g. PANI- initiator).

Finally, a semiconductor layer 10 may be deposited on top of the patterned second conductive polymer layer 7, according to the standard procedure known by a person skilled in the art. This step is illustrated in Fig. 8. An example of a semiconductor that may be used is pentacene. However, also other semiconductive materials may be used to form the semiconductive layer 10, such as for example polyacens, polyfluorens, polyphenylenevinylens, provided the maximum process temperature for processing them is less than 200°C.

In a specific embodiment of the invention, the semiconductor layer 10 may be an ambipolar semiconductor layer. The organic ambipolar semiconductor layer 10 may for example comprise a layer in which p-and n-type organic semiconductors are intimately mixed or may be a single polymeric semiconductor such as for example poly (3,9-di-tert- butylindeno [1, 2-b] fluorene) (PIF) ).

The semiconductive layer 10 may for example have a thickness of a few ten nm. The thickness of the semiconductive layer 10 may on one hand not be too small because in that case the layer may be discontinues. On the other hand, the thickness may not be too high because then the device will show background leakage. The semiconductive layer 10 does not require patterning. However, patterning may improve the properties of the device by reducing lateral leakage. The semiconductive layer 10 determines the electrical switching behavior of the transistor.

In a specific example of the above embodiment, the manufacturing of an all- polymer device is detailed, wherein the first 4 and the second 7 conductive polymer layers are PEDOT/PSS layers and wherein the ferroelectric polymer layer 5 is a VDF/TrFE layer.

The process steps of the manufacturing of the memory element of this example may be as follows. A first conductive PEDOT/PSS layer 4 is deposited onto the substrate I according to the following method. A composition of the PEDOT/PSS salt in

water is commercially available from H. C. starck as Baytron P. The concentration of PEDOT in this composition is 0.5% by weight and that of PSS is 0.8% by weight. To the composition apparently a colloidal solution about 0. 25% by weight is added. This colloidal solution may comprise a photocrosslinker which initiates cross linking after exposure with suitable light and which may for example be 4, 4'diazidodibenzalacetone-2, 2'-disulphonic acid disodium salt and 0.005% by weight of dodecylbenzenesulphonic acid sodium salt, which is a kind of soap to enhance the wetting properties. Alternatively a solution comprising H. C. Starck Baytron-P and 0.2 weight % of a diazonium cross linker like SCL-22S of Secant Chemicals Inc. MA USA (see W02003067333) After filtration through a filter preferably having pores with a diameter of 5 micron or less, the composition is spincoated onto the (optionally planarized) substrate 10. The layer thus obtained is dried for example at 30°C for 5 minutes.

The dried layer is then exposed through a mask to radiation with UV light (e. g. with a wavelength 365 nm) by means of for example an Hg lamp. Subsequently, the layer is washed by spraying with water. In this washing step, the non-irradiated areas of the layer are dissolved. After drying at 200°C, the average layer thickness of the remaining areas of the PEDOT/PSS layer is 80 nm. These areas have an electrical conductivity of 1 S/cm. The conduction of this layer can be increased by spin coating a 5wt % solution of sorbitol in water and heating the sample for 2 min at 200°C (see also W02003067333). This gives a conductivity of about 100 S/cm. Each continuous undissolved area functions as a conductive area such as for example a first interconnect line, a first electrode of the capacitor or a gate electrode of the transistor.

Subsequently a film of for example a random copolymer (CH2-CF2) n- (CHF- CF2) m wherein for example n=m (however, other m/n ratios may be used as well) is spincoated onto the PEDOT/PSS layer using a filtered (0.2 urn disposable) 5 weight percent solution of (CH2-CF2) n- (CHF-CF2) m random copolymer in VLSI grade 2-butanon and spinning for 10 seconds at 2000 rpm followed by 25 seconds at 250 rpm. This results in a layer with a thickness of approximately 400 nm, which has a highly hydrophobic water- resistant surface.

To deposit a second PEDOT/PSS layer onto the VDF/TrFE layer the same method is used as for deposition of the first PEDOT/PSS layer. However, modification of the spincoating solution is necessary, because spincoating of the second PEDOT/PSS layer from a watery solution results in severe dewetting. Therefore, in this specific embodiment of the present invention, the second PEDOT/PSS layer is deposited on top of the VDF/TrFE layer by the same method as in case of the first PEDOT/PSS layer, except for the fact that now 4%

n-butanol is added to the spincoating solution. Alternatively, a pre-coat of a solution containing 0.006wt% of SCL-22S and 4% of n-butanol in water may be used. After applying the standard patterning procedure to the second PEDOT/PSS layer, the conductivity of the layer is raised by spincoating 5% diethyleneglycol in water on top and heating e. g. to l l 0°C for 45 min. Next, annealing at 140°C for 2 hours in vacuum is conducted to increase crystallinity of the VDF layer. The hysteresis loop of a square I mm2 capacitor recorded at l Hz before and after annealing is shown in Fig. 9. It has been found that reducing the thickness of the VDF/TrFE layer leads to decreased switching voltages Vc. Layers of for example 250 nm lead to switching voltages of about 25 V while layers of 150 nm lead to switching voltages of about 15 V. In all cases the same remnant polarization (Pr) is obtained.

In a last step a semiconductor layer is added according to conventional deposition techniques known by a person skilled in the art in order to complete the transistor.

Hysteresis loops on capacitors were measured again before and after annealing. No significant differences were found.

In another embodiment of the present invention, an FRAM in a IT 1C (one transistor, one capacitor) cell 20, which is illustrated in Fig. 10, may be processed by using the method of the present invention.

The process steps are the same as in the first embodiment but in this second embodiment the first 4 and second 7 conductive polymer layer may differently be patterned with respect to the first 4 and second 7 conductive layer of the first embodiment.

A first conductive polymer layer 4 is deposited onto an optionally planarized substrate 1. This may be done as described in the first embodiment. The first conductive polymer layer 4 is then patterned to form a first interconnect line 11, a first electrode 12 of the capacitor 13 to be formed and a gate electrode 14 of a transistor 15 to be formed.

Patterning may be done by for example standard photolithography as described in the first embodiment.

Next, a ferroelectric polymer layer 5 is deposited onto the patterned first conductive polymer layer 4. The ferroelectric polymer layer 5 may be patterned to form contact holes 6 where necessary. Patterning of the ferroelectric polymer layer 5 may be achieved by means of photolithography whereby the solution, from which the ferroelectric polymer layer 5 is deposited, is modified by the addition of a cross linking agent, as described in the first embodiment.

Next, a second conductive polymer layer 7 is deposited by means of for example spincoating, dropcasting, doctor blade, lamination of a prefabricated composite film,

etc. The second conductive polymer layer 7 is then patterned to form a second interconnect line 16, a second electrode 17 of the capacitor 13, a source region 18 and drain region 19.

Patterning may be performed as described in the first embodiment of this invention.

A semiconductive layer 10 is then applied on top of the patterned second conductive layer. The semiconductive layer 10 may for example be precursor pentacene, spun from CH2CI2 and subsequently converted for 10 seconds at 180°C. Although the present invention is described by means of the processing of an all-polymer transistor and an FRAM in a IT 1C cell, other all-polymer device may be processed using the method of the present invention. Examples of all-polymer devices are for example all-polymer capacitors, metal semiconductor insulator (MIS) diodes and others.

Furthermore, the method of the present invention may also be used to deposit a polymer layer onto a hydrophobic piezoelectric layer, or more in general onto a hydrophobic dielectric layer.

It is to be understood that although preferred embodiments, specific constructions and configurations, as well as materials, have been discussed herein for devices according to the present invention, various changes or modifications in form and detail may be made without departing from the scope and spirit of this invention.

The present invention to a method for depositing a conductive polymer layer onto a hydrophobic polymer layer and the devices thus obtained. Deposition of a conductive polymer layer onto a hydrophobic polymer layer is not trivial, because the hydrophobic polymer possess poor wetting properties and have low adhesion to other materials. To overcome this problem, a surface tension reducing agent is added to the solution from which the conductive polymer layer is then deposited. The method of the present invention may be used for processing all-polymer devices such as all-polymer transistors, all-polymer capacitors, etc.