The present invention-relates to nductive elements, in particular for use as antennae, and also to resonant circuits which may incorporate such inductive elements. .More specifically but not exclusively, the present invention relates to the design, layout and structure of inductive elements and capacitive elements which together form resonant circuits. The present invention most specifically relates to the field of RF antennas.

The present invention also relates to the field of construction and fabrication of complete electronic circuits, in particular for use as transponders, identification devices or the like. Such electronic circuits may comprise inductive elements, capacitive elements, VLSI integrated circuit chips and other electronic components, in a complete assembly.

Transponders, identification devices or the like employ resonant circuits which comprise interconnected inductors and capacitors, and optionally include interconnected active circuitries embodied in VLSI integrated circuit chips. ^' The resonant circuits are adapted to receive electrical power from an external electromagnetic field generated by some interrogators or like apparatus. Optionally, the resonant circuits supply the power so received and collected to the active circuitries which may then generate the appropriate electrical signals as predetermined. Such signals may further be sent to other inductors, preferably the same power receiving inductors, functioning as antennae for transmission of the signals, to be received by some external receptors, preferably the same interrogators.

Accordingly, it is of significance that in the construction and fabrication of the complete electronic circuits of the transponders, identification devices or the like, the resonant circuits should be conveniently and

- 2 - easily interconnected with the active circuitries. Further, the inductors and the capacitors should also be conveniently interconnected without difficulties. In particular, the possible electrical configurations or designs of the complete electronic circuits should not be restricted by the structures or forms which the inductors or the capacitors happen to take. DESCRIPTION OF THE PRIOR ART

There have previously been described various techniques for producing simple resonant circuits at low cost. In U.S. 3,913,219, there is disclosed inductors- in the form of planar conductive spirals provided on one side of an insulative substrate and capacitors formed by ^" providing conductive areas aligned on opposite sides of the substrate of dielectric material. In ^' U.S. 4,369,557, similar planar spiral coil inductors are disclosed. . However, the capacitors may be formed ^' by providing conductive areas on only one side of the substrate which is folded to in part mutually align the conductive areas. In U.S. 4,658,254, the fold line is specifically defined by the configuration of the electrical conductive layer provided on one side of the substrate; in particular, the parallel straight sides of the conductive portions symmetrically positioned about the fold line. Further, the inductor may be formed.by planar spiral portions symmetrically positioned about the fold line.

It can be appreciated that planar spiral coils as disclosed above, and disclosed in U.S. 3,713,102 and 4,724,423, in which successive inner windings are of reducing diameters, each located within its predecessor, suffer from several disadvantages including :- (i) electrical tappings or connections to the planar spiral inductors cannot be easily and conveniently arranged; especially on the same side of the substrate as the spiral. (ii) the inner windings are necessarily of smaller diameters and hence cannot intercept as much magnetic flux as can the outer windings; therefore, the efficiency of the spiral inductors as energy collectors is reduced.

(iii) to provide a reasonable number of windings, without the overall spiral assembly being of excessive diameter, it necessitates closely wound narrow conductive strips resulting in high electrical resistances and thus reducing the efficiency of the resonant circuits.

Consequently, resonant circuits having planar spiral inductors are mostly not suitable for use in low frequency electromagnetic field which is preferable in many practical applications due to the reduced level of spurious electromagnetic radiation interference as compared to operating in higher frequencies. The planar spiral inductors are often considered as having a relatively poor electrical efficiency and an unsatisfactory Q-factor.

It has been proposed in U.S. 4,694,283 to arrange the windings of the inductors in superposed relationship by folding and to provide the capacitors by selective interposition of dielectric layers between conductor strip portions folded one onto the other.

The identification device according to U.S. 4,694,283 is essentially a parallel resonant circuit formed by four superposed layers, or necessarily a multiple of four superposed layers according to the particular planar conductor structure and method of folding. The planar conductor structure is either applied on a side of an electrically insulating carrier or provided with an insulating coating on both sides. Further, it requires a complex manufacturing process, including a method of interfolding the layers of the planar conductor structure and the use of several adhesives of differing strengths which may result in double layers of insulating material separating two layers of conductor material.

In the specifically described four-layer identification device, the planar conductor structure comprises windings of differing strip widths to allow for registration tolerances when folded. Each winding is substantially formed on a respective layer and adjacent windings have opposite directions of curvature.

Further, the peculiar method of interfolding necessarily results the windings in adjacent folded layers being electrically located at opposite ends of the induction coil. Such adjacent windings will necessarily experience high relative voltages and hence the stray capacitance between them will be of importance. In fact, such stray capacitances are used as primary tuning capacitances. This implies that variations in the stray capacitances caused by mechanical mis-registration of adjacent windings will cause significant changes in the electrical behaviour of the resonant circuit.

Consequently, the electrical behaviour of the - parallel resonant circuits represented by such complex identification devices is difficult to predict.- Further, interconnections between inductors and capacitors, and indeed optionally with active circuitries may not be conveniently and easily arranged in such complex identification devices. OBJECTS OF INVENTION

It is an object of the present invention to alleviate some of the disadvantages in the prior art resonant circuits, in particular the prior art inductors.

It is a further object of the present invention to provide an inductive element which improves the Q-factor and thus the electrical efficiency of a resonant circuit.

Yet a further object of the present invention is to allow interconnections to be conveniently and easily arranged between the inductive element and other electrical elements or electronic components in an electronic circuit.

It is a further object to provide the electronic circuit or a resonant circuit which has an inductive element according to the present invention and adapted to operate in a low frequency electromagnetic field.

Yet a further object of the invention is to provide a planar structure for an inductive element which can be mass produced economically and to provide a method for producing such an inductive element.

It is a further object of the present invention to provide a generally serpentine element disposed on a deformable substrate for alignment to receive impinging magnetic flux. SUMMARY OF INVENTION

The present invention is a cognate of. the inventions disclosed and described in detail with reference to preferred forms in the specifications accompanying Australian Patent Application Nos. PI 7198 and PJ 1693.

10 The present invention provides in one form an inductive element comprising: a deformable substrate and a conductive strip applied to said substrate to form a serpentine cc-Tiductive path on said substrate, _. _ the substrate being deformable in a predetermined manner such that the strip is oriented to form a coil structure suitable for use as an inductive element.

The coil is preferably an electrical loop. The strip is preferably generally elongate and may be disposed on one or both sides of the substrate (before the substrate

20 is deformed) . The coil is preferably a coil for receiving RF signals. The substrate may be a dielectric material, insulator or combination thereof.

The present invention also provides an inductive

25 element for use as an antenna in a transponder, comprising a generally serpentine conductive strip'arranged on one or both sides of an insulative substrate wherein said insulative substrate is folded about predetermined lines transverse to the longitudinal direction of said generally serpentine conductive strip into a

30 plurality of superposed layers and said generally serpentine conductive strip is so arranged that said generally serpentine conductive strip is ^" juxtaposed by said folding and formed into a coil like configuration.

The width of each generally serpentine conductive

35 strip being limited by the required electrical resistance of the coil, and by the provision of enough area in the 'loop'

for magnetic flux to pass therethrough, and by the overall physical dimensions required.

Alternatively, each conductor may take the form of a plurality of narrow, parallel conductors, separated one

₅ from another by narrow insulating gaps. When said parallel " conductors are joined together at each end (but not along their intermediate length), the effect is to reduce high-frequency electrical losses, in a manner analogous to the well-known "Litz" wire. (Litz wire consists of a

,« multitude of fine, insulated strands, and is used to wind conventional coils, such strands being connected only at their ends).

The length and/or configuration of each strip is = limited by the resistance and/or inductance required of each

, ₅ conductor, and the availability of space which is dependent - on each application of the present invention.

The conductors may be arranged on a dielectric and configured to minimise overlap of first and second conductors in order to reduce the capacitance therebetween.

2 _Q Alternatively, a high capacitance may be desirable, in which case overlap of first and second conductors is desirable.

The present invention may provide a relatively efficient signal receiver, in which the strip(s) of the receiver, being disposed on a substrate are arranged such

- _c that reception is substantially uniform throughout the entire length of the strip(s) of the receiver.

The strip(s) may be arranged such that upon folding, the conductors do not short circuit themselves or each other.

₃₀ In the manufacturing of the inductive element, the present invention provides an inductive element planar structure, comprising a generally serpentine conductive strip arranged on one or both sides of an insulative substrate, wherein said generally serpentine conductive

_-. strip is so arranged that, upon folding said insulative substrate about predetermined lines transverse to the longitudinal direction of said generally serpentine

conductive strip into a plurality of superposed layers, said generally serpentine conductive strip is juxtaposed by said folding and formed into a coil like configuration.

Further, there is also provided a method for

- producing the inductive element, comprising the steps of forming and arranging a generally serpentine conductive strip on one or both sides of an insulative substrate, said generally serpentine conductive strip being so arranged that, upon folding said insulative substrate about predetermined lines transverse to the longitudinal direction of said generally serpentine conductive strip into a plurality of superposed layers, said generally serpentine conductive strip is juxtaposed by said folding and formed into a coil like configuration; and folding said insulative

, _ substrate about said predetermined lines into said plurality 15 of superposed layers.

Conveniently, the plurality of superposed layers are represented by, in the unfolded substrate, a plurality of corresponding leaves adjacently connected to each other with folding zones therebetween. Each superposed layer or leaf may be of substantially constant dimension. The strip may be of substantially constant width throughout its length and each winding of the coil may be of substantially uniform curvature covering substantially uniform area of flux.

According to one embodiment of the present

_ 3 invention, each winding of the coil may be formed in at least one pair of adjacently connected layers whether adjacently superposed or not. Conveniently, there may be an even number of superposed layers.

According to a further embodiment of the present invention, the substrate may be folded into the plurality of superposed layers in a zig-zag manner, such that the folded layers form a "Z" pattern. In one form, the strip may be arranged from one side of the substrate to the other side thereof via a through hole therein.

According to an alternative embodiment of the present invention, the strip may be generally elongate and

arranged on one side of the substrate, the substrate being deformable to arrange the strip to form a coil for receiving magnetic flux. In practice, the strip may conveniently form a rectangular spiral when viewed from the path of impinging magnetic flux.

In accordance with a further aspect of the present invention, there is provided an electronic circuit for use as a transponder, identification device or the like, comprising at least one inductive element as described, wherein said at least one generally elongate or serpentine conductive strip is arranged on the one and same insulative substrate. The electronic circuit may further comprise at least one capacitive element, each capacitive element comprising a plurality of conductive members arranged on one or both sides of the one and same insulative substrate such that said plurality of conductive members superpose each other by the folding of the substrate to form at least one capacitor.

In the manufacturing of .the electronic circuit, there is provided an electronic circuit planar structure ^' comprising at least one inductive element planar structure as described, wherein said at least one generally serpentine conductive strip is arranged on the one and same insulative substrate. Further, the electronic circuit planar structure may comprise at least one capacitive element planar structure, each capacitive element planar structure comprising a plurality of conductive members arranged on one or both sides of the one and same insulative substrate such that said plurality of conductive members will superpose each other upon so folding the substrate to form at least one capacitor.

In the manufacturing of the antenna, there is also provided a method for producing an antenna comprising the steps of forming and arranging at least one generally serpentine conductive strip on one or both sides of an insulative substrate, said at least one generally serpentine conductive strip being so arranged that, upon folding said

insulative substrate about predetermined lines transverse to the longitudinal direction of said at least one generally serpentine conductive strip into a plurality of superposed layers, said at least one generally serpentine conductive strip is juxtaposed by said folding and formed into at least one coil like configuration respectively; and folding said insulative substrate about said predetermined lines into said plurality of superposed layers. Further, before so folding, at least one set of conductive members may be formed and arranged on one or both sides of said insulatiye substrate such that conductive members of each respective . set will superpose each other upon so folding the substrate.

In alternative methods, the folding of the substrate may be either in a zig-zag manner or in the case that the conductive materials are formed ^' 'and so_arranged only on one side of the substrate, substantialy in the form of a rectangular spiral.

According to a preferred embodiment of the present invention, the electronic circuit may further comprise at least one electronic component, for example a VLSI integrated circuit chip, disposed in respective bores formed by correspondingly superposed holes in the substrate. Conveniently, materials are provided in at least one of the bores to protect the respective electronic components therein.

In order to protect the electronic circuit in a transponder as a final product against electrical interference and physical manipulation, shielding elements and encapsulating elements are provided for such purposes. BRIEF DESCRIPTION OF THE DRAWINGS

Further advantages and features of the present invention will become apparent from the following description of several preferred embodiments of the invention with reference to the accompanying drawings in which :

Figure 1 is a schematic diagram of an electronic circuit of a transponder,

Figure 2 is a preferred planar structure equivalent of the electronic circuit of Figure 1.

Figure 3 s.hows a first folded assembly of the planar structure of Figure 2. _c Figure 4 shows a second folded assembly of the planar structure of Figure 2.

Figure 5 shows different stretched layouts of the folding zones provided in the folded assembly of Figure 4. -j. - Figure 6 is another preferred planar structure t I _Q . equivalent of the electronic circuit of Figure 1. -: . Figure 7 shows a zig-zag fold of the planar structure of Figure 6.

Figure 8 shows a preferred via connection, and - .: .--_- Figures 9A and 9B show a preferred arrangement for • _j . _Ef -tuning adjustment of a resonant circuit form with the inductive element of the present invention. DETAILED DESCRIPTION OF THE DRAWINGS

The basic circuitry of an electronic circuit in a transponder, identification device or the like is a resonant 2 ₀ circuit. The essential elements of the resonant circuit are the inductive elements and the capacitive elements. Various methods of manufacture of capacitors from a planar composite structure have previously been described. For example, in AU 159,958 the capacitor is formed by zig-zag folding of 2 strips of flexible dielectric sheet interposed between two flexible metal layers; in U.S. 2,470,826 the capacitor is formed by folding a similar composite layered material once along the centre line and then wound onto itself; and in U.S. 2,919,390 the capacitor is formed alternatively by ₃₀ winding two layered materials to avoid the opposite faces of the material contacting each other. In this respect, it can be seen that the nature of capacitors necessarily dictates the use of superposed layers of conductive and insulative materials. 35 The present invention utilises the concept of deformable, zig-zag or superposed layers and provides an inductive element in that form. In particular, the

preferred planar structure and preferred method of folding the structure enable such an inductive element to be incoporated into the manufacture of electronic circuits. Methods are described hereinafter for mass producing electronic circuits (called "transponders"), optionally including active circuitry; such active circuitry preferably being embodied in one or more VLSI integrated-circuit chips.

Such transponders may be fabricated, by forming patterns in an electrically conductive layer (called

"foil"), said foil being attached to one or both sides of a thin insulating substrate (called "dielectric"), to form a composite sheet of at least two dissimilar layers (called "laminate") which laminate is afterwards folded or rolled in one of a number of ways, to form the electronic circuits.

Practical transponders are usually completed by encasing in some suitable material for protection.

The methods described hereinafter offer significant advantages in terms of variety of possible electrical configurations, of electrical efficiency, and of simplicity of manufacture over other known methods.

According to one form of the invention, a transponder is constructed in two aspects namely, the design of the transponder, and the method of its manufacture. These will be described separately. (I) Design of the Transponder

For purposes of illustration, the production of an electronic circuit incorporating an inductive element according to the schematic diagram shown in Fig. 1 will be described. The method of the invention may, however, be adapted by suitably rearranging the inductive and capacitive elements, and the interconnections, to produce other schematic electrical configurations, as desired.

The electronic circuit shown in the schematic diagram of Figure 1 may be "expanded" into a planar structure as shown in Fig. 2. To fit on the page, the drawing has been broken into two sections as shown, however,

- 12 - it is to be understood as representing a single long web of laminate, having foil patterned as shown, deposited only on the top of the insulating dielectric substrate.

Comparison of Figs. 1 and 2 will show that the coil has been expanded into the generally "serpentine" conductive strip, while the capacitors Cl and C2 are implemented as the rectangular conductive members; P, Q, Y, X, connected in echelon as shown. The VLSI chip is located near the centre of the assembly, requiring only short, direct connections to.

10 the required points in the circuit. _ ς

The complete layout comprises a series of _ essentially similar zones (called "leaves"), each comprising a rectangular capacitive member, and an "L"-shaped element of the serpentine inductive strip. Fabrication. roceeds by..

,5 folding the lower right-hand leaf, about the line- A-A, under its left-hand neighbour. This folding process repeats, each time folding the right-hand leaf which now comprises a stack of previously-folded leaves, about a predetermined line transverse to the layout, under its immediate left-hand,

20 neighbour, until all leaves have been folded into. a plurality of superposed layers. It may be seen that adjacent "L"-shaped elements, upon so folding, will juxtapose and form substantially into respective windings of the coil. Conveniently, the total number of leaves or

25 superposed layers will be even. The folded assembly may be in the form of a substantially rectangular spiral.

It is apparent that, once such folding is complete, the successive "L"-shaped elements of the serpentine strip will collaborate to produce the coil, while the plate _Q members X/X align themselves adjacent to plate members Y/Y, to form capacitor C2. Similarly, plate members P/P align themselves adjacent to plate members Q/Q, to form capacitor Cl. Such capacitor plate members being separated by a single thickness only, of the dielectric material. 5 The central plate members YQ/YQ are seen to be common to both capacitors and, being connected to a point of zero potential, provide electrical shielding between said capacitors.

If required, additional inductive or capacitive elements could be provided, using additional similar structures.

The transponder as provided by the preferred embodiment exhibits certain particular properties as follows :

(a) Resistance to Dielectric fracture It will be seen that all folded layers may be produced with the foil on the outside, and the dielectric on 0 the inside. Hence the dielectric whose tensile strength is typically much less than that of the foil is placed in compression, not tension, by the folding process. This greatly reduces the risk of fracturing at the fold lines. Further, it will be seen as shown in Fig. 3 that the minimum _ bending radius applied to the foil in a folded assembly, is equal to the thickness of the dielectric, possibly compressed by the bending operation. Since the foil is thus never required to be sharply-folded upon itself, the risk of the foil fracturing at a fold line is greatly reduced. 0 (b) Tolerance to Dielectric fracture If nevertheless, the dielectric should fracture at a fold line, it may be seen that all electrically separate foil connections crossing fold lines, are arranged in echelon fr-om one leaf to the next, that is independently, at the fold lines on each side of the leaf. This may be seen 5 schematically in Fig. 2, both in the arrangement of the connections between the capacitive plate members, and in the

"staggered" connections employed where the serpentine strip passes from one leaf to the next at the fold lines. Hence foils crossing a fold-line, directly above each other, are 0 always separated by at least two layers of dielectric at this stressed point. This provides an additional margin of safety, should one of the dielectric layers fracture.

Fig. 3 also shows how the echelon connections appear when folded. b

(c) Improved Efficiency Coil Layout

As has been stated, coils produced according to prior art have been typically of a spiral form. Such signal coils are of limited electrical efficiency, due both to the limited area of the inner windings, and to the limited width possible of the conductors. The present invention by contrast, provides for coil windings to lie on top of each ^" other, so providing the maximum possible area for every winding. Further, it is now possible, without reducing the 0 enclosed flux area excessively, to employ much wider coil conductors than heretofore, so reducing the electrical resistance of said windings. This further improves the efficiency of the coil.

Naturally, such wider coil windings will exhibit 5 some mutual capacitance. It will, however, be apparent that such capacitance is significant only between any given coil winding and its immediate electrical neighbours, that is, pair of leaves. The relative voltage between such neighbours is relatively small, hence such stray capacitance 0 will be of little effect.

(d) Tolerance to Mechanical Mis-Registration Since there is only a single foil layer, the problem ^* of mis-registration between foil patterns on the two sides of the dielectric, does not arise in this preferred embodiment.

Mis-registration between the several leaves, when folded, will primarily affect circuit capacitances. As has been shown, this effect is only of significance in capacitive, not inductive, circuit elements. _Q The sensitivity of capacitive elements to mis-registration may be reduced by employing alternating large and small plates as shown. The effect is that the small plates are always fully covered or shadowed by the large plates. Hence the capacitive area is that of the _c smaller plate. A small variation in capacitance may still result from mis-registration causing a variable amount of the associated active connecting lead to be covered by the

larger plate. This may be compensated by extending a "dummy", connecting lead as shown, from the small plate in a direction opposite to the active connection. It may indeed be possible to utilise this second connecting lead as an active electrical connection. Any mis-registration will now result in equal and opposite changes in the capacitance attributable to each of the leads.

Alternatively, the effects of such mis-registration may be compensated for, by use of the tuning process hereinafter described. In such case, the capacitor plates will conveniently be made of equal dimensions, so achieving the maximum possible capacitance in a given physical space, (e) Protection of Active Components

Holes are punched in each leaf except those .carrying VLSI chips, or other active circuitry. ^" The holes are so positioned that as the folding proceeds, they will align one above the other, so forming a "bore" on either side of the leaf carrying the chip. ^" If more than one chip is required, several bores will be provided. The chip is installed at the bottom of one of these bores on the foil side of its connecting leaf, and the bores above and below the chip are afterwards filled with a suitable potting compound. This provides both environmental protection for the chip and also given a suitably rigid potting compound, protection from flexural stresses afterwards suffered by the completed transponder. (f) Minimised Stray Reactances

As has been shown, the effect of stray capacitance between coil windings is minimised, due to the minimal relative voltages present between such adjacent windings. Windings further apart electrically hence experiencing higher mutual voltages are also further apart mechanically, being separated by more layers of dielectric. Hence their mutual capacitance is also proportionately smaller.

It may be seen that, when the folding is completed, the leads connecting the several sets of capacitor plates, align themselves in a zig-zag pattern in a vertical plane.

that is, perpendicular to the plane of the drawing.

Currents in such leads are constrained to follow the zig-zag, so that the magnetic fields due to currents in successive leaves, are in opposition, and the net magnetic field is minimal. Hence the stray inductance of such leads is minimal.

It can be seen that further taps into the coil may be made as required, running the connections between the coil serpentine strip and the lead connecting the X/X capacitor plates. Similarly, further capacitors may be provided as needed, either by extending the length of the laminate web assembly, or by placing such capacitors between the existing row of capacitors, and the coil serpentine strip.

The VLSI chip and any other active components may likewise be located on any leaf desired, not at the mid-point nor end-points only.

(g) Electrical Screening of the Complete Assembly

Electrical screening may be achieved by including the two extreme left-hand leaves in the drawing. It will be seen that they provide the final pair of capacitor plates for the outermost capacitor, being themselves connected to a point of minimum potentials ^' Hence the capacitor assembly is self-screening.

The incomplete coil formed by the serpentine strip on these two final leaves aligns itself above the outer-most coil windings, so electrically screening them. The capacitance from this screen to the high voltage end of the coil will not be negligible, and must be deducted from the associated tuning capacitance. These outer screening - ^■ windings are purposely made wider than the active windings within both to maximise the screening effect and to minimise the variation in said stray capacitance due to mis-registration.

Other electrical schematics are possible, being so arranged that the outer end of the coil is the low potential end. Such layouts would be self-screening, and the above . outer screening would not be required.

>

- 17 - Conveniently, the deforming, folding or rolling of the substrate may proceed simultaneously from both ends of the substrate towards the centre so yielding two such rolled or folded assemblies, joined by a single thickness of laminate. The final fold, which unites these two assemblies, may be adapted to provide an adjustable degree of overlap between the said assemblies, such overlap serving to adjust the coil inductance, and hence the resonant frequency. Figures 9A and 9B show two rolled assemblies superimposed so as to provide adjustable tuning; (h) Tuning Adjustment

If desired, the resonant frequency of an embodied tuned circuit may now be adjusted, as follows. The patterned strips of Figures 2 or 6 may be folded from each end towards the centre. As this process completes, two folded assemblies result, joined by a single thickness of substrate. These assemblies are then superposed, as shown in Figures 9A and 9B and are moved relative to each other or slid thereby flexing the connecting section, to adjust tuning. The tuning process primarily proceeds by adjusting the coil inductance. The inductance of a coil is proportional to the square of the number of turns. If each half of the strip comprises N turns, and the inductance factor (determined by the coil dimensions) is K, then the inductance of each half will then be KN ² .

Where the two assemblies are placed, in effect, side by side with little or no overlap, magnetic coupling between the two coils is now minimal, and the combined inductance will be (to first order) 2KN ² . Figure 9A shows a first method of tuning adjustment and maximum mis-alignment. Figure 9B shows a second method of tuning adjustment and maximum alignment.

If, the two assemblies are brought into substantially complete superposition or overlapping relationship, coupling between the two coils will be very

- 18 «- close, so that there is essentially a single coil of 2N turns. The inductance of such a coil (again to first order) will be K(2N) ² = 4KN . The adjustment process can therefore provide up to a 2 to 1 change in the coil inductance. This

-. should be more than adequate to absorb normal manufacting tolerances.

If it is desired to combine this tuning adjustment with the electrical screening aforedescribed, this may conveniently be done by adding screening members (dummy coil _ιn turns and capacitor plates) to the central joining member.

These plates may be connected to the centre-tap of the coil, which then becomes, in effect, electrical ground. Since the entire transponder is not electrically, connected to any circuitry outside itself, it is functionally immaterial what

₁₅ point is termed "ground". The ends of the two half-coils are then connected to these dummy plates, which themselves provide the necessary interconnection.

It will be apparent from Figures 9A and 9B that, when the aforesaid tuning adjustment is employed, separate leaves must be employed to provide such encapsulation, as the ends of the original strip are no longer accessible, (i) Heat Dissipation

A semiconductor wafer or "chip" which is to be mounted on the substrate may. be provided with conductive

__ "bumps" (in a known process) in place of the usual recessed connections. These "bumps" may then be connected to a circuit pattern on the substrate and inductive element by use of the well-known Tape-Automated Bonding (TAB) process. Conveniently, the VLSI "chip" (or other _ heat-generating component) may be located adjacent to, or indeed above, capacitor plates provided on the substrate. Since the laminate typically comprises a much greater thickness of metal than of plastic, the capacitor assembly approximates a solid sheet of metal. The proximity of this _ sheet is used to conduct heat away from the "chip", and to dissipate it over the area of said capacitor plates.

- 19 -

If the tuning-adjustment technique aforesaid is used, it may be advantageous to attach the "chip" to one coil-half, then employ the other half (after bonding) to serve as a heat-sink as described. The second "half" may have a continuous metal layer under the "chip" to maximis'e heat removal. (j ) Final Encapsulation

To provide outer encapsulation for the completed transponder assembly, it is merely necessary to provide at least two additional leaves at the left-hand outermost end, following any screening leaves, formed of plain dielectric material with no conductive foil. When so folded, they enclose and protect the inner circuit assembly. Any VLSI chips or other active components, must of course have been attached and bores potted before this final encapsulating folding step can proceed.

In accordance with the spirit of the present invention, the inductive element as described and indeed the electronic circuit as described are not limited in their application' to transponders, identification devices or the like. Other electronic circuits whether resonant circuits or not may suitably utilise the present invention; in particular, the possible interconnections between electrical components and the provisions thereof. (k) An exemplary embodiment of the present invention will now be described.

The present invention is suitable for implementation using aluminium or copper or any other suitable conductive foil in the range 5μ-50μ thick { μ = micron), on a polyester or polythene or dielectric substrate of not more than 10μ thick and preferably 2μ or less. This substrate may advantageously be made as thin as is commercially available.

The various dimensions (thickness of material, width of traces, number of layers etc.) are highly inter-dependent, and will require to be optimised for each given application. Methods for performing this optimisation are generally known in the art of electric circuit and coil

design, for example [1] Fields & Waves in Communication Electronics: Ramo S, Whinnery J. R, Van Duzer T, John Wiley 1965.

For example, consider a transponder comprising, inter alia, a VLSI chip mounted on a substrate having an inductive element according to the present invention, where the transponder is required to operate at 132kHz, and to be of similar size to a standard credit card, i.e. 86 x 54 x 0.76mm. 0 Using 18.5 _/ / copper foil over 1.5,v polyester film, the total laminate thickness is 20 , permitting.38 layers - (0.76mm/20//) in the stated overall thickness. This represents 19 coil turns.

- - - - T e coil conductors may be 2mm wide, and the coil 5 may be a square form, with the conductor centre-line describing a square of 50mm side. The remaining 54 x 35mm space in the card is available for capacitors, etc. Inductance formula described in [1] above describes circular coils, however it is also valid for square coils of similar o area. For the given coil (50 x 50mm, 19 turns), the formula gives an inductance of 62/uH. At 132kHz, the reactance is then 51.4 Ohms.

The total length of the coil conductors is 19 x 50 x 4mm = 3800mm. Taking the resistivity of copper as given in [2] Tables of Physical & Chemical Constants: Kaye G. W. C, Laby T. H. , 13th edition, Longmans 1966, as 1.7 x 10 ^~6 Ohm-cm, the coil DC resistance is 1.75 Ohm. The Quality Factor (Q) (at 132kHz) is then 51.4/1.75 = 29. (This calculation is to first-order only, and assumes uniform current distribution across the conductor cross-section) .

Consider now, a prior-art flat spiral coil, of similar dimensions, as is known from the prior art documents previously noted. For a square spiral, of 50mm outside edge, with a 15mm square central void, using 30 copper foil ^' (i.e. standard "1-ounce" printed-circuit stock), the leading dimensions are:

radial depth, d = 1.95cm axial breadth, b = 0.003cm (copper foil thickness) means radius, r = 1.82cm

Stefan's formula as given in [3] Wireless Telegraphists Pocket Book: Fleming J. A., The Wireless Press 1915, for such a coil, reads

L = 4 π r N ² ((1 + 3b ^{2 +} d ² ) In 8r - Cl + b ² .C ₂ )

96r ² /(b ² +d ² ) 16r ²

The table in [3] above gives C _χ = 0.5, and C ₂ = 0.125. Solving the above yields an inductance factor (i.e. inductance of a single-turn coil) of 35cm, or 0.035 _/ tH.

To achieve the same inductance (62 H) as the present invention, would thus require /(62/0.035) = 42 turns. Allowing insulating gaps between the conductors equal to half the conductors own width, the conductor width becomes 1.95/(42 x 1.5) = 0.03cm. Total length of conductors = 4 x (1.5 + 5) x 21cm = 546cm, and its cross-sectional area = 0.003 x 0.03 = 9 x 10 ^~5 cm ² .

As previously, resistivity of copper = 1.7 x 10 ^~6 Ohm-cm. So coil series resistance = 10.3 Ohms, or almost 6 times that of an equivalent coil built according to the present invention, using the same first-order calculations. For the spiral coil, at 132kHz, Q = 51.4/10.3 = 5. The invention may therefore be expected to yield performance improvements of up to 6 times, relative to prior art.