Title:
INSULATING GATE-TYPE BIPOLAR TRANSISTOR
Document Type and Number:
WIPO Patent Application WO/2013/179379
Kind Code:
A1
Abstract:
The purpose of the present invention is to provide a trench-gate-type IGBT that is capable of both maintaining voltage resistance and reducing the on-voltage and that has a large current density range in which unipolar operation is performed, and a method for manufacturing the same. This IGBT is an SJ-RC-IGBT having a drift layer formed by a superjunction structure and being provided with an IGBT region and an FWD region on the reverse surface, the IGBT being characterized in that the first drift layer has an impurity concentration of 1 × 1015 atms/cm3 to less than 2 × 1016 atms/cm3 and a thickness of 10 μm to less than 50 μm, and the buffer layer has an impurity concentration of 1 × 1015 atms/cm3 to less than 2 × 1016 atms/cm3 and a thickness of 2 μm to less than 15 μm.
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Inventors:
AONO SHINJI (JP)
MINATO TADAHARU (JP)
MINATO TADAHARU (JP)
Application Number:
PCT/JP2012/063687
Publication Date:
December 05, 2013
Filing Date:
May 29, 2012
Export Citation:
Assignee:
MITSUBISHI ELECTRIC CORP (JP)
AONO SHINJI (JP)
MINATO TADAHARU (JP)
AONO SHINJI (JP)
MINATO TADAHARU (JP)
International Classes:
H01L27/04; H01L29/78; H01L29/739
Foreign References:
| JP2006287127A | 2006-10-19 | |||
| JPH10223896A | 1998-08-21 | |||
| JP2003303965A | 2003-10-24 | |||
| JP2000260984A | 2000-09-22 | |||
| JP2008053648A | 2008-03-06 |
Attorney, Agent or Firm:
YOSHITAKE Hidetoshi et al. (JP)
Hidetoshi Yoshitake (JP)
Hidetoshi Yoshitake (JP)
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