Title:
INTEGRAL STRESS ISOLATION APPARATUS AND TECHNIQUE FOR SEMICONDUCTOR DEVICES
Document Type and Number:
WIPO Patent Application WO2000029824
Kind Code:
A9
Abstract:
A semiconductor device die comprising one or more stress-isolated regions is described. In one embodiment, stress isolation is achieved by providing a nominally rigid rim region which form part of the stress isolated region. The rim region is attached to a nominally rigid periphery or frame region by a flexible, spring-like stress-isolation region such that displacements and twisting of the frame region due to mounting and packaging stresses are mitigated, do not propagate to the stress-isolated region, and do not effect the output signal. The stress isolation flexible region includes first and second members etched from the semiconductor device material to mechanically isolate the diaphragm from its periphery. The first member is formed by etching a first deep trench. The combination of the first deep trench etch and a second deep trench etch define the second member.
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Inventors:
BRYZEK JANUSZ
BURNS DAVID W
NASIRI STEVEN S
BURNS DAVID W
NASIRI STEVEN S
Application Number:
PCT/US1999/025168
Publication Date:
January 04, 2001
Filing Date:
October 27, 1999
Export Citation:
Assignee:
MAXIM INTEGRATED PRODUCTS (US)
International Classes:
G01L9/00; G01P15/12; G01L9/04; H01L29/84; (IPC1-7): G01L9/00
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