TECHNICAL FIELD

[0001] This disclosure generally relates to integrated circuit structures, such as transistors.

BACKGROUND

[0002] Transistors can refer to semiconductor devices used to amplify or switch electronic signals and electrical power. Planar transistors can have a transistor density that can be increased, for example, by decreasing the pitch between transistor gate elements. However, with planar transistors, the ability to decrease gate pitch may be limited by the required gate length and/or spacer thickness.

BRIEF DESCRIPTION OF THE FIGURES

[0003] Reference will now be made to the accompanying drawings, which are not necessarily drawn to scale, and wherein:

[0004] FIG. 1 shows an example diagram of a device, in accordance with one or more example embodiments of the disclosure.

[0005] FIG. 2 shows an example diagram of a partial structure of a device, in accordance with one or more example embodiments of the disclosure.

[0006] FIG. 3 shows an example diagram of a partial structure of a device, in accordance with one or more example embodiments of the disclosure.

[0007] FIG. 4 shows an example diagram of a partial structure of a device, in accordance with one or more example embodiments of the disclosure.

[0008] FIG. 5 shows an example diagram of a partial structure of a device, in accordance with one or more example embodiments of the disclosure.

[0009] FIGs. 6A and 6B shows example diagrams of a flow for fabricating a transistor, in accordance with one or more example embodiments of the disclosure.

[0010] FIG. 7 shows an example system, in accordance with example embodiments of the disclosure.

DETAILED DESCRIPTION

[0011] Embodiments of the disclosure are described more fully hereinafter with reference to the accompanying drawings, in which example embodiments of the disclosure are shown. This disclosure may, however, be embodied in many different forms and should not be construed as limited to the example embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Like numbers refer to like, but not necessarily the same or identical, elements throughout.

[0012] The following embodiments are described in sufficient detail to enable at least those skilled in the art to understand and use the disclosure. It is to be understood that other embodiments would be evident based on the present disclosure and that process, mechanical, material, dimensional, process equipment, and parametric changes may be made without departing from the scope of the present disclosure.

[0013] In the following description, numerous specific details are given to provide a thorough understanding of various embodiments of the disclosure. However, it will be apparent that the disclosure may be practiced without these specific details. In order to avoid obscuring the present disclosure, some well-known system configurations and process steps may not be disclosed in full detail. Likewise, the drawings showing embodiments of the disclosure are semi-diagrammatic and not to scale and, particularly, some of the dimensions are for the clarity of presentation and may be exaggerated in the drawings. In addition, where multiple embodiments are disclosed and described as having some features in common, for clarity and ease of illustration, description, and comprehension thereof, similar and like features will ordinarily be described with like reference numerals even if the features are not identical.

[0014] The term“horizontal” as used herein may be defined as a direction parallel to a plane or surface (for example, surface of a substrate), regardless of its orientation. The term “vertical,” as used herein, may refer to a direction orthogonal to the horizontal direction as just described. Terms, such as“on,”“above,”“below,”“bottom,”“top,”� �side” (as in“sidewall”), “higher,”“lower,”“upper,”“over,” and“under,” may be referenced with respect to a horizontal plane, where the horizontal plane can include an x-y plane, a x-z plane, or a y-z plane, as the case may be. The term“processing” as used herein includes deposition of material or photoresist, patterning, exposure, development, etching, cleaning, ablating, polishing, and/or removal of the material or photoresist as required in formation a described structure.

[0015]“An embodiment”,“various embodiments” and the like indicate embodiment(s) so described may include particular features, structures, or characteristics, but not every embodiment necessarily includes the particular features, structures, or characteristics. Some embodiments may have some, all, or none of the features described for other embodiments. “First”,“second”,“third” and the like describe a common object and indicate different instances of like objects are being referred to. Such adjectives do not imply objects so described must be in a given sequence, either temporally, spatially, in ranking, or in any other manner. “Connected” may indicate elements are in direct physical or electrical contact with each other and“coupled” may indicate elements co-operate or interact with each other, but they may or may not be in direct physical or electrical contact. Also, while similar or same numbers may be used to designate same or similar parts in different figures, doing so does not mean all figures including similar or same numbers constitute a single or same embodiment.

[0016] In an embodiment, described herein are systems, methods, and apparatuses for vertical transistors for use in connection with memory devices. In an embodiment, in such a vertical transistor, the direction of current flow can be in a direction that is substantially perpendicular to the substrate on which the transistor is fabricated. In an embodiment, the current can flow from a source located at the top of the vertical transistor to a drain located at the bottom of the device, where the bottom of the vertical transistor is in proximity to the substrate on which the vertical transistor is fabricated. In another embodiment, the current can flow from a source located at the bottom of the vertical transistor to a drain located at the top of the device, where the bottom of the vertical transistor is in proximity to the substrate on which the vertical transistor is fabricated.

[0017] In an embodiment, the transistors can be used in connection with random access memory, for example, dynamic random access memory (DRAM). In an embodiment, the transistors can be used in connection with embedded DRAM (eDRAM). In an embodiment, the transistors described herein can be used in connection with a capacitor. In an embodiment, the capacitor can be used to store a charge (for example, a charge that signifies a“1” or a 0” for the memory device), for example, when the transistor is in an off state. In an embodiment, the transistor and capacitor can be used as a memory element, as part of a memory array for a memory device. In an embodiment, the capacitor can be fabricated in a via that is in turn fabricated in an insulator that at least partially encapsulates the vertical transistor. In an embodiment, the capacitor can include a first capacitive material (such as a metal or a doped semiconductor) that acts as a capacitor plate, a dielectric material, and a second capacitive material (such as a metal or a doped semiconductor) that acts as a second capacitor plate.

[0018] In an embodiment, the vertical transistor described herein can be used in connection with a bitline and a wordline, as a portion of a memory array. In an embodiment, the bitline can be positioned at the bottom of the vertical transistor, where the bottom of the vertical transistor is in proximity to the substrate on which the vertical transistor is fabricated. In an embodiment, the gate of the vertical transistor can serve as the word line for the portion of the memory array that is electrically integrated with the vertical transistor. In an embodiment, the bitline and the wordline can be approximately perpendicular to one another. In an embodiment, the bitlines can be shared between different vertical transistors in an array of memory elements, as a portion of the memory array.

[0019] In an embodiment, the transistors can include thin film transistor (TFT) materials. In an embodiment, the TFT materials can include either n-type or p-type material. In an embodiment, the TFT materials can include, but not be limited to, indium gallium zinc oxide (IGZO). In an embodiment, the IGZO can be doped with nitrogen. In an embodiment, the IGZO can include a material composition where the ratio of In:Ga:Zn can go from 1 : 1 : 1 to any combination of In, Zn, Ga content. In an embodiment, indium enrichment can result in an increase in mobility in the semiconductor. In an embodiment, the semiconductor can include indium zinc oxide (IZO), indium tin oxide (ITO), molybdenum sulfide (M0S2), black phosphorus, amorphous silicon (a-Si), amorphous germanium (a-Ge), polymorphous silicon (poly-Si), polymorphous germanium (poly-Ge), amorphous zinc oxide (AZO), tin oxides (SnO and Sn0 ₂ ), copper oxides (for example, Cu ₂ 0 and CuO).

[0020] In an embodiment, the disclosed systems, methods, and apparatuses can lead memory elements including the vertical transistor and corresponding capacitor having areas that can be reduced in comparison with memory elements having lateral transistors. In an embodiment, the critical dimension of the vertical transistor as described herein can be defined by the dimensions of the gate, for example, a printed metal gate. In an embodiment, the channel length of the disclosed vertical transistors can be more easily reduced in comparison with lateral transistors. In an embodiment, the disclosed vertical transistors can have lower short channel leakage effects in comparison with lateral transistors. In an embodiment, a misalignment the between one or more contacts to the vertical transistor may not lead to an increase in a bitline to capacitor coupling, which would otherwise increase noise in the memory element. In an embodiment, the source and the drain of the vertical transistor can be fabricated in different steps, which can allow for differential treatment of the source and drain. In contrast, the source and drain of a lateral transistor may need to be fabricated in the same fabrication step. In an embodiment, the channel length (Lg) of the vertical transistor as described herein can be independent of a patterning process, allowing the channel length to be less than the channel length of a lateral transistor. [0021] In an embodiment, lateral transistors and corresponding capacitors can have a 1.5-2 poly-pitch. In an embodiment, the vertical transistor can include a thin film transistor (TFT) material. In an embodiment, the TFT material may be deposited using a conformal technique, for example, using Atomic layer deposition (ALD). In an embodiment, the TFT material can include hafnium oxide.

[0022] Various types of memory, for example, EDRAM can be limited by transistor cell areas and/or capacitor areas of the memory structures. In some cases, the memory structures may require specific metal layer thicknesses in order to accommodate such smaller transistor and/or capacitor areas. Other types of memory, for example, L3 and/or L4 static random access memory (SRAMS) can be formed in the frontend, that is, in the silicon. However, they may be formed in the backend processing, for example, to improve array efficiency and/or area density in a memory array.

[0023] In an embodiment, lateral TFTs, for example, using a one transistor, one capacitor architecture may use a 1.5 to 2 poly pitch. In one embodiment, such lateral transistors may have misalignment induced shorting and/or bitline capacitor coupling in the transistor structures which can lead to increased noise in the device. In some cases, such transistor devices may necessitate self- alignment for one or more contacts used in the transistors in order, for example, to improve, that is, reduce contact resistance in the transistors. In some cases, such transistors may require an additional mask or masks, for example, to separate capacitor and/or via contacts from bitline metals in the transistor structures.

[0024] In an embodiment of the disclosure, the one transistor, one capacitor devices disclosed herein can have a reduced footprint with respect to lateral transistors. In one embodiment, for such vertical transistors a misalignment may not cause an increase in coupling capacitance in the device. In one embodiment, the channel length L _g can be decoupled from a patterning process used to fabricate the transistor. In one embodiment, the metal gate thickness can form the critical dimension of the transistor and can reduce short channel affects. In one embodiment, a vertical transistor structure such as that disclosed herein can enable capacitor scaling. In another embodiment, such a vertical transistor architecture, as disclosed herein, can enable independent fabrication of sources and/or drains.

[0025] In one embodiment, in the vertical transistor disclosed herein, a bitline can be formed at the bottom of the device and serve as a contact to the transistor, for example, a drain and/or a source contact for the transistor. In an embodiment, the gate for the transistor can be formed substantially perpendicular to the bitline and can serve as a wordline for the device. In an embodiment, the gate serving as a wordline can turn on and off the transistor. In an embodiment, in such a vertical transistor, as disclosed herein, current can flow in substantially vertical directions between a source contact and a drain contact in the transistor which can be alternatively referred to as bitlines herein. In an embodiment, the gate of the transistor and device can include a wraparound gate and be continuous between multiple transistors on the same or different die. In one embodiment, the vertical transistors, disclosed herein, can store the charge of the transistor in a capacitor that is coupled to the transistor in a storage node.

[0026] FIG. 1 shows an example diagram of a transistor 100 in accordance with one or more example embodiments of the disclosure. In one embodiment, the transistor 100 can include an insulator 102. In one embodiment, the insulator 102 can include an interlayer dielectric (ILD) material. In another embodiment, the insulator 102 can include an oxide. In an embodiment, the insulator 102 can include a silicon dioxide (S1O2), or a low-K material. In one embodiment, the insulator 102 can be deposited using PVD, CVD, MOCVD, and/or ALD, and the like.

[0027] In one embodiment, the transistor 100 can include a bitline 104. In another embodiment, the bitline 104 can serve as a transistor contact, for example, a drain contact. In another embodiment, the contact can comprise a source contact. In an embodiment, the bitline 104 can comprise a metallic, semi-metallic, or intermetallic material. In various embodiments, the bitline 104 can comprise a metallic material. Non-limiting examples include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the bitline 104 can comprise a semi -metallic material. Non-limiting examples include arsenic, antimony, bismuth, a-tin (gray tin) and graphite, and mercury telluride (HgTe). Semi-metallic materials may also be any mixtures of such materials. In various embodiments, the bitline 104 can comprise an intermetallic material. Non-limiting examples include gold and aluminum intermetallic s, copper and tin intermetallic s, tin and nickel intermetallics, tin and silver intermetallics, tin and zinc intermetallic s, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the contacts bitline 104 may be deposited by any suitable mechanism including, but not limited to, metal foil lamination, physical vapor deposition, chemical vapor deposition, sputtering, metal paste deposition, combinations thereof, or the like.

[0028] In one embodiment, the transistor 100 can include an insulator 106. In one embodiment, the insulator 106 can include an interlayer dielectric (ILD) material. In another embodiment, the insulator 106 can include an oxide. In an embodiment, the insulator 106 can include a silicon dioxide (SiCk), or a low-K material. In one embodiment, the insulator 106 can be deposited using PVD, CVD, MOCVD, and/or ALD, and the like.

[0029] In one embodiment, the transistor 100 can include a gate 110. In another embodiment, the gate 110 can serve as a wordline for a memory structure incorporating the transistor 100. In one embodiment, the wordline can serve to turn the transistor 100 on and off. In one embodiment, the gate 110 can be substantially perpendicular to the bitline 104. In another embodiment, the gate 110 can include a metal. In another embodiment, the gate 110 can include a transition metal. In one embodiment, the gate 110 can be used to tune the threshold voltage of the device. In one embodiment, gate 110 can include titanium nitride, cobalt, tungsten and/or platinum. In one embodiment, the gate 110 can be deposited using PVD, CVD, MOCVD, MBE and/or ALD, and the like. In one embodiment, the gate 110 can have a thickness of approximately 30 nm to approximately 100 nm, with an example thickness of approximately 40 nm to approximately 60 nm.

[0030] In one embodiment, the transistor 100 can include an insulator 112. In one embodiment, the insulator 112 can include an interlayer dielectric (ILD) material. In another embodiment, the insulator 112 can include an oxide. In an embodiment, the insulator 112 can include a silicon dioxide (SiCk), or a low-K material. In one embodiment, the insulator 112 can be deposited using PVD, CVD, MOCVD, and/or ALD, and the like.

[0031] In one embodiment, the transistor 100 can include gate dielectrics 114. In another embodiment, the gate dielectrics 114 can be disposed substantially on sidewalls of the insulator 106, the gate 110, and the insulator 112. In one embodiment, the gate dielectric 114 can include a dielectric material. In another embodiment, the gate dielectric 114 can include silicon oxide. In another embodiment, the gate dielectric 114 can include a high-K dielectric material. In another embodiment, the high-K material, for example, hafnium oxide, tantalum oxide, titanium oxide, aluminum oxide, silicon dioxide, silicon nitride and the like. In one embodiment, an electroglass (EG) can be used as the gate dielectric 114. In one embodiment, the gate dielectric 114 can include hexagonal boron nitride (HBN). In one embodiment, the gate material can be deposited using PVD, CVD, and/or ALD, and the like. In one embodiment, the gate dielectric 114 can have a thickness of approximately 1 nm to approximately 10 nm, with an example thickness of approximately 2 nm to approximately 4 nm.

[0032] In one embodiment, the transistor 100 can include a semiconductor 116. In another embodiment, the semiconductor 116 can include a thin film transistor material. In one embodiment, the semiconductor 116 may not necessarily be continuous between transistors such as multiple transistors, each transistor similar to transistor 100.

[0033] In one embodiment, the transistor 100 can include barriers 118. In another embodiment, the barriers 118 can serve as buffer or passivation layers. In another embodiment, the barriers 118 can serve to reduce the effects of an insulator layer, for example, insulator 122 to be shown and discussed below.

[0034] In one embodiment, the transistor 100 can include a bitline 120. In another embodiment, the bitline 120 can serve as a contact to the transistor 100. In another embodiment, the bitline 120 can serve as a source contact. In another embodiment, the bitline 120 can serve as a drain contact. In one embodiment, the bitline 120 can be substantially perpendicular to the gate 110. In an embodiment, the bitline 120 can comprise a metallic, semi- metallic, or intermetallic material. In various embodiments, the bitline 120 can comprise a metallic material. Non-limiting examples include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the bitline 120 can comprise a semi-metallic material. Non- limiting examples include arsenic, antimony, bismuth, a-tin (gray tin) and graphite, and mercury telluride (HgTe). Semi-metallic materials may also be any mixtures of such materials. In various embodiments, the bitline 120 can comprise an intermetallic material. Non-limiting examples include gold and aluminum intermetallics, copper and tin intermetallics, tin and nickel intermetallics, tin and silver intermetallics, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the bitline 120 may be deposited by any suitable mechanism including, but not limited to, metal foil lamination, physical vapor deposition, chemical vapor deposition, sputtering, metal paste deposition, combinations thereof, or the like.

[0035] In one embodiment, the transistor 100 can include an insulator 122. In one embodiment, the insulator 122 can include an interlayer dielectric (ILD) material. In another embodiment, the insulator 122 can include an oxide. In an embodiment, the insulator 122 can include a silicon dioxide (S1O2), or a low-K material. In one embodiment, the insulator 122 can be deposited using PVD, CVD, MOCVD, and/or ALD, and the like.

[0036] In one embodiment, the transistor 100 can include via (also referred to as vertical interconnect access) 124 that may be formed, at least partially, in the insulator 122. In various embodiments, the via can represent an electrical connection between layers in the transistor that goes through a plane (for example, an x-y plane) of one or more adjacent layers. [0037] In one embodiment, the transistor 100 can include a first capacitor material 126. In an embodiment, the first capacitor material 126 can comprise a metallic, semi-metallic, or intermetallic material. In various embodiments, the first capacitor material 126 can comprise a metallic material. Non-limiting examples include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the first capacitor material 126 can comprise a semi-metallic material. Non-limiting examples include arsenic, antimony, bismuth, a-tin (gray tin) and graphite, and mercury telluride (HgTe). Semi-metallic materials may also be any mixtures of such materials. In various embodiments, the first capacitor material 126 can comprise an intermetallic material. Non-limiting examples include gold and aluminum intermetallic s, copper and tin intermetallic s, tin and nickel intermetallics, tin and silver intermetallics, tin and zinc intermetallic s, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the first capacitor material 126 may be deposited by any suitable mechanism including, but not limited to, metal foil lamination, physical vapor deposition, chemical vapor deposition, sputtering, metal paste deposition, combinations thereof, or the like.

[0038] In one embodiment, the transistor 100 can include a dielectric 128. In one embodiment, the dielectric 128 can include an oxide. In an embodiment, the dielectric 128 can include a silicon dioxide (SiCk), a hafnium oxide, or a low-K material. In one embodiment, the dielectric l28can be deposited using PVD, CVD, MOCVD, and/or ALD, and the like.

[0039] In one embodiment, the transistor 100 can include a second capacitor material 130. In an embodiment, the second capacitor material 130 can comprise a metallic, semi-metallic, or intermetallic material. In various embodiments, the second capacitor material 130 can comprise a metallic material. Non-limiting examples include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the second capacitor material 130 can comprise a semi- metallic material. Non-limiting examples include arsenic, antimony, bismuth, a-tin (gray tin) and graphite, and mercury telluride (HgTe). Semi-metallic materials may also be any mixtures of such materials. In various embodiments, the second capacitor material 130 can comprise an intermetallic material. Non-limiting examples include gold and aluminum intermetallics, copper and tin intermetallics, tin and nickel intermetallics, tin and silver intermetallics, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the second capacitor material 130 may be deposited by any suitable mechanism including, but not limited to, metal foil lamination, physical vapor deposition, chemical vapor deposition, sputtering, metal paste deposition, combinations thereof, or the like.

[0040] In one embodiment, the transistor 100 can include a first contact 132. In one embodiment, the transistor 100 can include a second contact 134. In an embodiment, the first contact 132 and the second contact 134 can comprise a metallic, semi-metallic, or intermetallic material. In various embodiments, the first contact 132 and the second contact 134 can comprise a metallic material. Non-limiting examples include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the first contact 132 and the second contact 134 can comprise a semi-metallic material. Non-limiting examples include arsenic, antimony, bismuth, a-tin (gray tin) and graphite, and mercury telluride (HgTe). Semi-metallic materials may also be any mixtures of such materials. In various embodiments, the can comprise an intermetallic material. Non-limiting examples include gold and aluminum intermetallics, copper and tin intermetallic s, tin and nickel intermetallics, tin and silver intermetallics, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the first contact 132 and the second contact 134 may be deposited by any suitable mechanism including, but not limited to, metal foil lamination, physical vapor deposition, chemical vapor deposition, sputtering, metal paste deposition, combinations thereof, or the like.

[0041] In one embodiment, the transistor 100 can include an insulator 136. In one embodiment, the insulator 136 can include an interlayer dielectric (ILD) material. In another embodiment, the insulator 136 can include an oxide. In an embodiment, the insulator 136 can include a silicon dioxide (S1O2), or a low-K material. In one embodiment, the insulator 136 can be deposited using PVD, CVD, MOCVD, and/or ALD, and the like.

[0042] In one embodiment, the transistor 100 can include a third contact 138. In one embodiment, the transistor 100 can include a fourth contact 140. In an embodiment, the third contact 132 and the fourth contact 134 can n comprise a metallic, semi-metallic, or intermetallic material. In various embodiments, the third contact 132 and the fourth contact 134 can comprise a metallic material. Non-limiting examples include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the third contact 132 and the fourth contact 134 can comprise a semi-metallic material. Non-limiting examples include arsenic, antimony, bismuth, a-tin (gray tin) and graphite, and mercury telluride (HgTe). Semi-metallic materials may also be any mixtures of such materials. In various embodiments, the third contact 132 and the fourth contact 134 can comprise an intermetallic material. Non-limiting examples include gold and aluminum intermetallics, copper and tin intermetallics, tin and nickel intermetallics, tin and silver intermetallics, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the third contact 132 and the fourth contact 134 may be deposited by any suitable mechanism including, but not limited to, metal foil lamination, physical vapor deposition, chemical vapor deposition, sputtering, metal paste deposition, combinations thereof, or the like.

[0043] In one embodiment, the insulators 102, 106, 112, 122 and 136 can include similar but not identical material. In another embodiment, the said insulators can comprise distinct layers formed using separate deposition steps. In one embodiment, the first capacitor material and/or the second capacitor material 130 can include similar but not necessarily identical materials. In one embodiment, the first contact 132, the second contact 134, the third contact 138 and/or the fourth contact 140 can include similar but not necessarily identical materials and can be formed using the same and/or distinct deposition techniques and/or steps.

[0044] In one embodiment, current can flow vertically in the transistor 100, for example, between the bitline 104 serving as a source and/or drain contact and the bitline 120 serving as another source or drain contact. In one embodiment, depending on the order of deposition of the bitline layer serving as a source and/or drain, the direction of current flow can run in opposing directions between the bitline 104 and the bitline 120.

[0045] In one embodiment, the gate 110 can serve as a wraparound gate, that is, the gate can be continuous between different transistors on the same chip and/or die, each transistor resembling the transistor 100 of FIG. 1. In one embodiment, when the transistor 100 is turned off, the charge can be stored in a capacitor as shown and described in connection with FIG. 1 , in particular, the first capacitor material 126, the dielectric 128 and the second capacitor material 130. In one embodiment, the printing of the gate 110 can define the critical dimension and the corresponding L _G of the transistor 100.

[0046] FIG. 2 shows an example diagram of a partial structure of a transistor 200 in accordance with one or more example embodiments of the disclosure. In one embodiment, the transistor 200 can include an insulator 202.

[0047] In an embodiment, the insulator layer 202 can be deposited on a substrate, not shown. In one embodiment, the insulator 202 can include an interlayer dielectric (ILD) material. In another embodiment, the insulator 202 can include an oxide. In an embodiment, the insulator 202 can include a silicon dioxide (S1O2), or a low-K material. In one embodiment, the insulator 202 can be deposited using PVD, CVD, MOCVD, and/or ALD, and the like.

[0048] In an embodiment, the transistor 200 can include a bitline 204. In another embodiment, the bitline 204 can be deposited on the insulator 202. In one embodiment, the bitline 204 can serve as a contact for the transistor. In another embodiment, the bitline 204 can serve as a drain and/or a source for the transistor. In an embodiment, the bitline 204 an comprise a metallic, semi-metallic, or intermetallic material. In various embodiments, the bitline 204 can comprise a metallic material. Non-limiting examples include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the bitline 204 can comprise a semi-metallic material. Non-limiting examples include arsenic, antimony, bismuth, a-tin (gray tin) and graphite, and mercury telluride (HgTe). Semi-metallic materials may also be any mixtures of such materials. In various embodiments, the bitline 204 can comprise an intermetallic material. Non-limiting examples include gold and aluminum intermetallics, copper and tin intermetallics, tin and nickel intermetallics, tin and silver intermetallics, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the contacts bitline 204 may be deposited by any suitable mechanism including, but not limited to, metal foil lamination, physical vapor deposition, chemical vapor deposition, sputtering, metal paste deposition, combinations thereof, or the like.

[0049] In an embodiment, the transistor 200 can include an insulator 206. In another embodiment, the insulator 206 can be deposited on at least a portion of the bitline 204. In one embodiment, the deposition of the insulator 206 can be performed using a mask. In one embodiment, the insulator 206 can include an interlayer dielectric (ILD) material. In another embodiment, the insulator 206 can include an oxide. In an embodiment, the insulator 206 can include a silicon dioxide (S1O2), or a low-K material. In one embodiment, the insulator 206 can be deposited using PVD, CVD, MOCVD, and/or ALD, and the like.

[0050] In one embodiment, the transistor 200 can include a gate 210. In another embodiment, the gate 210 can be disposed on the insulator 206. In one embodiment, the gate 210 can include a metal. In one embodiment, the gate 210 can serve as a wordline in the transistor. In one embodiment, the gate 210 can extend in the X and Y dimensions.

[0051] In another embodiment, the gate 210 can serve as a wordline for a memory structure incorporating the transistor 200. In one embodiment, the wordline can serve to turn the transistor 200 on and off. In one embodiment, the gate 210 can be substantially perpendicular to the bitline 204. In another embodiment, the gate 210 can include a metal. In another embodiment, the gate 210 can include a transition metal. In one embodiment, the gate 210 can be used to tune the threshold voltage of the device. In one embodiment, gate 210 can include titanium nitride, cobalt, tungsten and/or platinum. In one embodiment, the gate 210 can be deposited using PVD, CVD, MOCVD, MBE and/or ALD, and the like. In one embodiment, the gate 210 can have a thickness of approximately 30 nm to approximately 100 nm, with an example thickness of approximately 40 nm to approximately 60 nm.

[0052] In one embodiment, the transistor 200 can include an insulator 212. In another embodiment, the insulator 212 can be disposed on the gate 210. In one embodiment, the insulator 212 can include an interlayer dielectric (ILD) material. In another embodiment, the insulator 212 can include an oxide. In an embodiment, the insulator 212 can include a silicon dioxide (S1O2), or a low-K material. In one embodiment, the insulator 212 can be deposited using PVD, CVD, MOCVD, and/or ALD, and the like.

[0053] In one embodiment, the transistor 200 can include gate dielectrics 214. In another embodiment, the gate dielectrics 214 can be disposed on a portion of a sidewall of the insulator 206, the gate 210 and the insulator 212. In another embodiment, the gate dielectrics 214 can be disposed substantially on sidewalls of the insulator 206, the gate 210 and the insulator 212. In one embodiment, the gate dielectrics 214 can include a dielectric material. In another embodiment, the gate dielectrics 214 can include silicon oxide. In another embodiment, the gate dielectrics 214 can include a high-K dielectric material. In another embodiment, the high- K material, for example, hafnium oxide, tantalum oxide, titanium oxide, aluminum oxide, silicon dioxide, lanthanum oxides, hafnium lanthanum oxides, silicon nitride and the like. In one embodiment, an electroglass (EG) can be used as the gate dielectrics 214. In one embodiment, the gate dielectrics 214 can include hexagonal boron nitride (HBN). In one embodiment, the gate material can be deposited using PVD, CVD, and/or ALD, and the like. In one embodiment, the gate dielectrics 214 can have a thickness of approximately 1 nm to approximately 10 nm, with an example thickness of approximately 2 nm to approximately 4 nm.

[0054] FIG. 3 shows a partial structure of a transistor 300, in accordance with one or more example embodiments of the disclosure. In one embodiment, the transistor 300 can include a semiconductor 316. In another embodiment, the semiconductor 316 can include a thin film transistor material. In one embodiment, the semiconductor 316 may not necessarily be continuous between transistors on a single die or on multiple die. In an embodiment, the semiconductor 316 can be either n-type or p-type material. In an embodiment, the semiconductor 316 can include, but not be limited to, indium gallium zinc oxide (IGZO). In an embodiment, the IGZO can be doped with nitrogen. In an embodiment, the IGZO can include a material composition where the ratio of In:Ga:Zn can go from 1: 1:1 to any combination of In, Zn, Ga content. In an embodiment, indium enrichment can result in an increase in mobility in the semiconductor. In an embodiment, the semiconductor can include indium zinc oxide (IZO), indium tin oxide (ITO), molybdenum sulfide (M0S2), black phosphorus, amorphous silicon (a-Si), amorphous germanium (a-Ge), polymorphous silicon (poly-Si), polymorphous germanium (poly-Ge), amorphous zinc oxide (AZO), tin oxides (SnO and Sn0 ₂ ), copper oxides (for example, Cu ₂ 0 and CuO).

[0055] In one embodiment, the transistor 300 can include a barrier 318. In another embodiment, the barrier 318 can include a buffer and/or passivation material. In another embodiment, the barrier 318 can serve to mitigate the effects of the neighboring insulator material such as insulator 322 to be discussed below on the finished transistor and, in particular, on the semiconductor 316.

[0056] In one embodiment, the transistor 300 can include a storage node 320. In another embodiment, the storage node 320 can serve as a contact for the transistor, for example, the storage node 320 can serve as source contact or a drain contact for the transistor. In another embodiment, the storage node 320 can serve as a contact to the transistor 300. In another embodiment, the storage node 320 can serve as a source contact. In another embodiment, the storage node 320 can serve as a drain contact. In one embodiment, the storage node 320 can be substantially perpendicular to the gate 310. In an embodiment, the storage node 320 can comprise a metallic, semi-metallic, or intermetallic material. In various embodiments, the storage node 320 can comprise a metallic material. Non-limiting examples include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the storage node 320 can comprise a semi-metallic material. Non-limiting examples include arsenic, antimony, bismuth, a-tin (gray tin) and graphite, and mercury telluride (HgTe). Semi-metallic materials may also be any mixtures of such materials. In various embodiments, the storage node 320 can comprise an intermetallic material. Non-limiting examples include gold and aluminum intermetallics, copper and tin intermetallics, tin and nickel intermetallics, tin and silver intermetallics, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the storage node 320 may be deposited by any suitable mechanism including, but not limited to, PVD, CVD, PECVD, MBE, metal foil lamination, sputtering, metal paste deposition, combinations thereof, or the like.

[0057] In one embodiment, the transistor 300 can include an insulator 322. In another embodiment, the insulator 322 can be disposed on the storage node 320, the barriers 318 and a portion of the semiconductor 316. In one embodiment, the insulator 322 can include an interlayer dielectric (ILD) material. In another embodiment, the insulator 322 can include an oxide. In an embodiment, the insulator 322 can include a silicon dioxide (S1O2), or a low-K material. In one embodiment, the insulator 322 can be deposited using PVD, CVD, MOCVD, and/or ALD, and the like.

[0058] In one embodiment, the transistor 300 can include a via 324 that can be formed in the insulator 322. In an embodiment, the via 324 can serve as an area for which subsequent layers can form a capacitor for use in connection with the transistor 300. In various embodiments, the via 324 can represent an electrical connection between layers in the transistor that goes through a plane (for example, an x-y plane) of one or more adjacent layers.

[0059] In various embodiments, the transistor 300 can further include the layers described previously in connection with FIG. 2. For example, the transistor 300 can include a substrate 202, a bitline 204, an insulator 206, a gate 210, an insulator 212, and gate dielectric 214. For further description of the various layers, including layer thicknesses, compositions, and/or fabrication techniques, please refer to the relevant description provided in connection with FIG. 2.

[0060] FIG. 4 shows an example diagram of a partial structure 400, in accordance with one or more example embodiments of the disclosure. In one embodiment, the structure 400 can include a first capacitor material 426. In an embodiment, the first capacitor material 426 can comprise a metallic, semi-metallic, or intermetallic material. In various embodiments, the first capacitor material 426 can comprise a metallic material. Non- limiting examples include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the first capacitor material 426 can comprise a semi-metallic material. Non-limiting examples include arsenic, antimony, bismuth, a-tin (gray tin) and graphite, and mercury telluride (HgTe). Semi-metallic materials may also be any mixtures of such materials. In various embodiments, the first capacitor material 426 can comprise an intermetallic material. Non-limiting examples include gold and aluminum intermetallic s, copper and tin intermetallics, tin and nickel intermetallics, tin and silver intermetallics, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the first capacitor material 426 may be deposited by any suitable mechanism including, but not limited to PVD, CVD, PECVD, MBE, ALD, metal foil lamination, sputtering, metal paste deposition, combinations thereof, or the like.

[0061] In one embodiment, the structure 400 can include a dielectric 428. In one embodiment, the dielectric 428 can include an interlayer dielectric (ILD) material. In another embodiment, the dielectric 428 can include an oxide. In an embodiment, the dielectric 428 can include a silicon dioxide (S1O2), or a low-K material. In one embodiment, the insulator 536 can be deposited using PVD, CVD, MOCVD, and/or ALD, and the like.

[0062] In one embodiment, the structure 400 can include a second capacitor material 430. In an embodiment, the second capacitor material 430 can comprise a metallic, semi-metallic, or intermetallic material. In various embodiments, the second capacitor material 430 can comprise a metallic material. Non-limiting examples include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the second capacitor material 430 can comprise a semi- metallic material. Non-limiting examples include arsenic, antimony, bismuth, a-tin (gray tin) and graphite, and mercury telluride (HgTe). Semi-metallic materials may also be any mixtures of such materials. In various embodiments, the second capacitor material 430 can comprise an intermetallic material. Non-limiting examples include gold and aluminum intermetallics, copper and tin intermetallics, tin and nickel intermetallics, tin and silver intermetallics, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the second capacitor material 430 may be deposited by any suitable mechanism including, but not limited to PVD, CVD, PECVD, MBE, ALD, metal foil lamination, sputtering, metal paste deposition, combinations thereof, or the like.

[0063] In one embodiment, the structure 400 can include a first contact 432. In an embodiment, the first contact 432 can comprise a metallic, semi-metallic, or intermetallic material. In various embodiments, the first contact 432 can comprise a metallic material. Non-limiting examples include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the first contact first contact 432 can comprise a semi-metallic material. Non-limiting examples include arsenic, antimony, bismuth, a-tin (gray tin) and graphite, and mercury telluride (HgTe). Semi- metallic materials may also be any mixtures of such materials. In various embodiments, the can comprise an intermetallic material. Non-limiting examples include gold and aluminum intermetallics, copper and tin intermetallics, tin and nickel intermetallics, tin and silver intermetallic s, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the first first contact 432 may be deposited by any suitable mechanism including, but not limited to, metal foil lamination, physical vapor deposition, chemical vapor deposition, sputtering, metal paste deposition, combinations thereof, or the like.

[0064] In one embodiment, the first capacitor material 426 can be disposed in the via 324. In another embodiment, the first capacitor material 426 can be in contact with at least the portion of the storage node 320. In one embodiment, the dielectric 428 can be disposed on a portion of the first capacitor material 426. In one embodiment, the second capacitor material 430 can be disposed on a portion of the dielectric 428. In one embodiment, the first contact 432 can be disposed on at least a portion of the second capacitor 430.

[0065] In various embodiments, the transistor 400 can further include the layers described previously in connection with FIGs. 2 and 3. For example, the transistor 300 can include a substrate 202, a bitline 204, an insulator 206, a gate 210, an insulator 212, gate dielectric 214, semiconductor 316, barrier 318, storage node 320, insulator 322, and via 324. For further description of the various layers, including layer thicknesses, compositions, and/or fabrication techniques, please refer to the relevant description provided in connection with FIGs. 2 and 3.

[0066] FIG. 5 shows an example diagram of a partial structure 500, in accordance with one or more example embodiments of the disclosure. In one embodiment, the structure 500 can include a second contact 534. In one embodiment, the second contact 534 can be disposed on a portion of the first contact 432 and a portion of the insulator 322 and a portion of the dielectric 428. In an embodiment, the second contact 534 can comprise a metallic, semi-metallic, or intermetallic material. In various embodiments, the second contact 534 can comprise a metallic material. Non-limiting examples include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the second contact 534 can comprise a semi-metallic material. Non-limiting examples include arsenic, antimony, bismuth, a-tin (gray tin) and graphite, and mercury telluride (HgTe). Semi-metallic materials may also be any mixtures of such materials. In various embodiments, the can comprise an intermetallic material. Non-limiting examples include gold and aluminum intermetallics, copper and tin intermetallics, tin and nickel intermetallics, tin and silver intermetallics, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the second contact 534 may be deposited by any suitable mechanism including, but not limited to, metal foil lamination, physical vapor deposition, chemical vapor deposition, sputtering, metal paste deposition, combinations thereof, or the like.

[0067] In one embodiment, the structure 500 can include an insulator 536. In another embodiment, the insulator 536 can be disposed on a portion of the second contact 534. In one embodiment, the insulator 536 can include an interlayer dielectric (ILD) material. In another embodiment, the insulator 536 can include an oxide. In an embodiment, the insulator 536 can include a silicon dioxide (S1O2), or a low-K material. In one embodiment, the insulator 536 can be deposited using PVD, CVD, MOCVD, and/or ALD, and the like.

[0068] In one embodiment, a portion of the insulator 536 can be removed to generate an area in which a third contact 538 can be deposited and/or formed. In one embodiment, the third contact 538 can be disposed on a portion of the second contact 534. In one embodiment, a fourth contact 540 can be disposed on a portion of the insulator 536 and a portion of the third contact 538.

[0069] In an embodiment, the third contact 538 and the fourth contact 540 can comprise a metallic, semi-metallic, or intermetallic material. In various embodiments, the third contact 538 and the fourth contact 540 can comprise a metallic material. Non-limiting examples include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the third contact 538 and the fourth contact 540 can comprise a semi-metallic material. Non-limiting examples include arsenic, antimony, bismuth, a-tin (gray tin) and graphite, and mercury telluride (HgTe). Semi-metallic materials may also be any mixtures of such materials. In various embodiments, the third contact 538 and the fourth contact 540 can comprise an intermetallic material. Non limiting examples include gold and aluminum intermetallic s, copper and tin intermetallics, tin and nickel intermetallics, tin and silver intermetallics, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the third contact 538 and the fourth contact 540 may be deposited by any suitable mechanism including, but not limited to, metal foil lamination, physical vapor deposition, chemical vapor deposition, sputtering, metal paste deposition, combinations thereof, or the like.

[0070] In various embodiments, the transistor 500 can further include the layers described previously in connection with FIGs. 2, 3, and 4. For example, the transistor 300 can include a substrate 202, a bitline 204, an insulator 206, a gate 210, an insulator 212, gate dielectric 214, semiconductor 316, barrier 318, storage node 320, insulator 322, and via 324, first capacitor material 426, dielectric 427, second capacitor material 430, and contact 432. For further description of the various layers, including layer thicknesses, compositions, and/or fabrication techniques, please refer to the relevant description provided in connection with FlGs. 2, 3, and 4.

[0071] FIG. 6 shows an example diagram of a flow for fabricating a transistor in accordance with one or more example embodiments of the disclosure. At block 602, a first insulator can be deposited on a substrate. In one embodiment, the insulator can include an interlayer dielectric (ILD) material. In another embodiment, the insulator can include an oxide. In an embodiment, the insulator can include a silicon dioxide (S1O2), or a low-K material. In one embodiment, the insulator can be deposited using PVD, CVD, MOCVD, and/or ALD, and the like.

[0072] At block 604, a first bitline can be deposited on a first insulator. In another embodiment, the bitline can serve as a transistor contact, for example, a drain contact. In another embodiment, the contact can comprise a source contact. In an embodiment, the bitline an comprise a metallic, semi-metallic, or intermetallic material. In various embodiments, the bitline can comprise a metallic material. Non-limiting examples include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the bitline can comprise a semi-metallic material. Non-limiting examples include arsenic, antimony, bismuth, a-tin (gray tin) and graphite, and mercury telluride (HgTe). Semi-metallic materials may also be any mixtures of such materials. In various embodiments, the bitline can comprise an intermetallic material. Non-limiting examples include gold and aluminum intermetallics, copper and tin intermetallics, tin and nickel intermetallics, tin and silver intermetallics, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the contacts bitline may be deposited by any suitable mechanism including, but not limited to, metal foil lamination, physical vapor deposition, chemical vapor deposition, sputtering, metal paste deposition, combinations thereof, or the like.

[0073] At block 606, a second insulator can be deposited on the bitline. In one embodiment, the insulator can include an interlayer dielectric (ILD) material. In another embodiment, the insulator can include an oxide. In an embodiment, the insulator can include a silicon dioxide (S1O2), or a low-K material. In one embodiment, the insulator can be deposited using PVD, CVD, MOCVD, and/or ALD, and the like. [0074] At block 608, a gate can be deposited on the second insulator. In another embodiment, the gate can serve as a wordline for a memory structure incorporating the transistor. In one embodiment, the wordline can serve to turn the transistor on and off. In one embodiment, the gate can be substantially perpendicular to the bitline. In another embodiment, the gate can include a metal. In another embodiment, the gate can include a transition metal. In one embodiment, the gate can be used to tune the threshold voltage of the device. In one embodiment, gate can include titanium nitride, cobalt, tungsten and/or platinum. In one embodiment, the gate can be deposited using PVD, CVD, MOCVD, MBE and/or ALD, and the like. In one embodiment, the gate can have a thickness of approximately 30 nm to approximately 100 nm, with an example thickness of approximately 40 nm to approximately 60 nm.

[0075] At block 610, a third insulator can be deposited on the gate. In one embodiment, the insulator can include an interlayer dielectric (ILD) material. In another embodiment, the insulator can include an oxide. In an embodiment, the insulator can include a silicon dioxide (SiCk), or a low-K material. In one embodiment, the insulator can be deposited using PVD, CVD, MOCVD, and/or ALD, and the like.

[0076] At block 612, a gate dielectrics can be deposited on sidewalls of the second insulator and third insulator. In another embodiment, the gate dielectrics can be disposed substantially on sidewalls of the second insulator, the gate, and the third insulator. In one embodiment, the gate dielectric 114 can include a dielectric material. In another embodiment, the gate dielectric 114 can include silicon oxide. In another embodiment, the gate dielectric 114 can include a high-K dielectric material. In another embodiment, the high-K material, for example, hafnium oxide, tantalum oxide, titanium oxide, aluminum oxide, silicon dioxide, silicon nitride and the like. In one embodiment, an electroglass (EG) can be used as the gate dielectric 114. In one embodiment, the gate dielectric 114 can include hexagonal boron nitride (HBN). In one embodiment, the gate material can be deposited using PVD, CVD, and/or ALD, and the like. In one embodiment, the gate dielectric 114 can have a thickness of approximately 1 nm to approximately 10 nm, with an example thickness of approximately 2 nm to approximately 4 nm.

[0077] At block 614, a semiconductor can be deposited on a portion of the bitline, gate dielectrics and the third insulator. In another embodiment, the semiconductor 116 can include a thin film transistor material. In one embodiment, the semiconductor 116 may not necessarily be continuous between transistors such as multiple transistors, each transistor similar to transistor 100.

[0078] At block 616, a barrier can be deposited on portions of the sidewalls of the semiconductor. In another embodiment, the barriers 118 can serve as buffer or passivation layers. In another embodiment, the barriers 118 can serve to reduce the effects of an insulator layer, for example, insulator 122 to be shown and discussed below.

[0079] At block 618, a second bitline can be deposited on a portion of the semiconductor. In another embodiment, the bitline can serve as a contact to the transistor. In another embodiment, the bitline can serve as a source contact. In another embodiment, the bitline can serve as a drain contact. In one embodiment, the bitline can be substantially perpendicular to the gate. In an embodiment, the bitline can comprise a metallic, semi-metallic, or intermetallic material. In various embodiments, the bitline can comprise a metallic material. Non-limiting examples include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the bitline can comprise a semi-metallic material. Non-limiting examples include arsenic, antimony, bismuth, a-tin (gray tin) and graphite, and mercury telluride (HgTe). Semi-metallic materials may also be any mixtures of such materials. In various embodiments, the bitline can comprise an intermetallic material. Non-limiting examples include gold and aluminum intermetallics, copper and tin intermetallics, tin and nickel intermetallics, tin and silver intermetallics, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the bitline may be deposited by any suitable mechanism including, but not limited to, metal foil lamination, physical vapor deposition, chemical vapor deposition, sputtering, metal paste deposition, combinations thereof, or the like.

[0080] At block 620, a fourth insulator can be deposited on the second bitline, the barriers and the semiconductor. In one embodiment, the insulator can include an interlayer dielectric (ILD) material. In another embodiment, the insulator can include an oxide. In an embodiment, the insulator can include a silicon dioxide (S1O2), or a low-K material. In one embodiment, the insulator can be deposited using PVD, CVD, MOCVD, and/or ALD, and the like.

[0081] At block 622, a portion of the fourth insulator can be removed to form a via. In various embodiments, the via can represent an electrical connection between layers in the transistor that goes through a plane (for example, an x-y plane) of one or more adjacent layers. In one embodiment, the removal can be implemented using an etching process. In an embodiment, the etching process can include, for example, a dry etch. In one embodiment, the dry etch can include, for example, a plasma-based and/or a mechanical-based etch. In one embodiment, the etching process can include, for example, a wet etch. The wet etching process can include, for example, any suitable chemicals for the removal of the portion of the fourth insulation.

[0082] At block 624, a first capacitor can be deposited in the via on a portion of the second bitline. In an embodiment, the first capacitor material can comprise a metallic, semi-metallic, or intermetallic material. In various embodiments, the first capacitor material can comprise a metallic material. Non-limiting examples include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the first capacitor material can comprise a semi-metallic material. Non limiting examples include arsenic, antimony, bismuth, a-tin (gray tin) and graphite, and mercury telluride (HgTe). Semi-metallic materials may also be any mixtures of such materials. In various embodiments, the first capacitor material can comprise an intermetallic material. Non-limiting examples include gold and aluminum intermetallic s, copper and tin intermetallic s, tin and nickel intermetallics, tin and silver intermetallics, tin and zinc intermetallic s, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the first capacitor material may be deposited by any suitable mechanism including, but not limited to, metal foil lamination, physical vapor deposition, chemical vapor deposition, sputtering, metal paste deposition, combinations thereof, or the like.

[0083] At block 626, a dielectric can be deposited on the first capacitor. In one embodiment, the dielectric can include an oxide. In an embodiment, the dielectric can include a silicon dioxide (S1O2), a hafnium oxide, or a low-K material. In one embodiment, the dielectric can be deposited using PVD, CVD, MOCVD, and/or ALD, and the like.

[0084] At block 628, a second capacitor can be deposited on the dielectric. In an embodiment, the second capacitor material can comprise a metallic, semi-metallic, or intermetallic material. In various embodiments, the second capacitor material can comprise a metallic material. Non limiting examples include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the second capacitor material can comprise a semi-metallic material. Non-limiting examples include arsenic, antimony, bismuth, a-tin (gray tin) and graphite, and mercury telluride (HgTe). Semi-metallic materials may also be any mixtures of such materials. In various embodiments, the second capacitor material can comprise an intermetallic material. Non-limiting examples include gold and aluminum intermetallics, copper and tin intermetallics, tin and nickel intermetallics, tin and silver intermetallics, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the second capacitor material may be deposited by any suitable mechanism including, but not limited to, metal foil lamination, physical vapor deposition, chemical vapor deposition, sputtering, metal paste deposition, combinations thereof, or the like.

[0085] At block 630, a first contact can be deposited on the second capacitor material. In an embodiment, the first contact can comprise a metallic, semi-metallic, or intermetallic material. In various embodiments, the first contact can comprise a metallic material. Non-limiting examples include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the first contact can comprise a semi-metallic material. Non-limiting examples include arsenic, antimony, bismuth, a-tin (gray tin) and graphite, and mercury telluride (HgTe). Semi-metallic materials may also be any mixtures of such materials. In various embodiments, the can comprise an intermetallic material. Non-limiting examples include gold and aluminum intermetallics, copper and tin intermetallics, tin and nickel intermetallics, tin and silver intermetallics, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the first contact may be deposited by any suitable mechanism including, but not limited to, metal foil lamination, physical vapor deposition, chemical vapor deposition, sputtering, metal paste deposition, combinations thereof, or the like.

[0086] At block 632, a second contact can be deposited on the first contact. In an embodiment, the second contact can comprise a metallic, semi-metallic, or intermetallic material. In various embodiments, the second contact can comprise a metallic material. Non-limiting examples include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, t the second contact can comprise a semi-metallic material. Non-limiting examples include arsenic, antimony, bismuth, a-tin (gray tin) and graphite, and mercury telluride (HgTe). Semi-metallic materials may also be any mixtures of such materials. In various embodiments, the can comprise an intermetallic material. Non-limiting examples include gold and aluminum intermetallics, copper and tin intermetallics, tin and nickel intermetallics, tin and silver intermetallics, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the second contact may be deposited by any suitable mechanism including, but not limited to, metal foil lamination, physical vapor deposition, chemical vapor deposition, sputtering, metal paste deposition, combinations thereof, or the like.

[0087] At block 634, a fifth insulator can be deposited on the second contact. In one embodiment, the insulator can include an interlayer dielectric (ILD) material. In another embodiment, the insulator can include an oxide. In an embodiment, the insulator can include a silicon dioxide (S1O2), or a low-K material. In one embodiment, the insulator can be deposited using PVD, CVD, MOCVD, and/or ALD, and the like.

[0088] At block 636, a portion of the fifth insulator can be removed. In one embodiment, the removal can be implemented using an etching process. In an embodiment, the etching process can include, for example, a dry etch. In one embodiment, the dry etch can include, for example, a plasma-based and/or a mechanical-based etch. In one embodiment, the etching process can include, for example, a wet etch. The wet etching process can include, for example, any suitable chemicals for the removal of the portion of the fifth insulator.

[0089] At block 638, a third contact can be deposited in the removed portion of the fifth insulator and on the second contact. In an embodiment, the third contact can comprise a metallic, semi-metallic, or intermetallic material. In various embodiments, the third contact can comprise a metallic material. Non-limiting examples include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the third contact can comprise a semi-metallic material. Non-limiting examples include arsenic, antimony, bismuth, a-tin (gray tin) and graphite, and mercury telluride (HgTe). Semi-metallic materials may also be any mixtures of such materials. In various embodiments, the third contact can comprise an intermetallic material. Non-limiting examples include gold and aluminum intermetallics, copper and tin intermetallic s, tin and nickel intermetallics, tin and silver intermetallics, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the third contact may be deposited by any suitable mechanism including, but not limited to, metal foil lamination, physical vapor deposition, chemical vapor deposition, sputtering, metal paste deposition, combinations thereof, or the like.

[0090] At block 640, a fourth contact can be deposited on the third contact. In one embodiment, the transistor can include a fourth contact. In an embodiment, the fourth contact can comprise a metallic, semi-metallic, or intermetallic material. In various embodiments, the fourth contact can comprise a metallic material. Non-limiting examples include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the fourth contact can comprise a semi-metallic material. Non-limiting examples include arsenic, antimony, bismuth, a-tin (gray tin) and graphite, and mercury telluride (HgTe). Semi-metallic materials may also be any mixtures of such materials. In various embodiments, the fourth contact can comprise an intermetallic material. Non-limiting examples include gold and aluminum intermetallics, copper and tin intermetallic s, tin and nickel intermetallics, tin and silver intermetallics, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the fourth contact may be deposited by any suitable mechanism including, but not limited to, metal foil lamination, physical vapor deposition, chemical vapor deposition, sputtering, metal paste deposition, combinations thereof, or the like.

[0091] FIG. 7 depicts an example of a system 700 according to one or more embodiments of the disclosure. In an embodiment, the system 700 and all of its components (to be discussed) may include transistors having the features described herein. In one embodiment, system 700 includes, but is not limited to, a desktop computer, a laptop computer, a netbook, a tablet, a notebook computer, a personal digital assistant (PDA), a server, a workstation, a cellular telephone, a mobile computing device, a smart phone, an Internet appliance or any other type of computing device. In some embodiments, system 700 can include a system on a chip (SOC) system.

[0092] In one embodiment, system 700 includes multiple processors including processor 710 and processor N 705, where processor N 705 has logic similar or identical to the logic of processor 710. In one embodiment, processor 710 has one or more processing cores (represented here by processing core 1 712 and processing core N 712N, where 712N represents the Nth processor core inside processor 710, where N is a positive integer). More processing cores can be present (but not depicted in the diagram of FIG. 7). In some embodiments, processing core 712 includes, but is not limited to, pre-fetch logic to fetch instructions, decode logic to decode the instructions, execution logic to execute instructions, a combination thereof, or the like. In some embodiments, processor 710 has a cache memory 716 to cache instructions and/or data for system 700. Cache memory 716 may be organized into a hierarchical structure including one or more levels of cache memory.

[0093] In some embodiments, processor 710 includes a memory controller (MC) 714, which is configured to perform functions that enable the processor 710 to access and communicate with memory 730 that includes a volatile memory 732 and/or a non-volatile memory 734. In some embodiments, processor 710 can be coupled with memory 730 and chipset 720. Processor 710 may also be coupled to a wireless antenna 778 to communicate with any device configured to transmit and/or receive wireless signals. In one embodiment, the wireless antenna antenna 778 operates in accordance with, but is not limited to, the IEEE 802.11 standard and its related family, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.

[0094] In some embodiments, volatile memory 732 includes, but is not limited to, Synchronous Dynamic Random Access Memory (SDRAM), Dynamic Random Access Memory (DRAM), RAMBUS Dynamic Random Access Memory (RDRAM), and/or any other type of random access memory device. Non-volatile memory 734 includes, but is not limited to, flash memory, phase change memory (PCM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), or any other type of non-volatile memory device.

[0095] Memory device 730 stores information and instructions to be executed by processor 710. In one embodiment, memory 730 may also store temporary variables or other intermediate information while processor 710 is executing instructions. In the illustrated embodiment, chipset 720 connects with processor 710 via Point-to-Point (PtP or P-P) interface 717 and P-P interface 722. Chipset 720 enables processor 710 to connect to other elements in system 700. In some embodiments of the disclosure, P-P interface 717 and P-P interface 722 can operate in accordance with a PtP communication protocol, such as the Intel® QuickPath Interconnect (QPI) or the like. In other embodiments, a different interconnect may be used.

[0096] In some embodiments, chipset 720 can be configured to communicate with processor 710, the processor N 705, display device 740, and other devices 772, 776, 774, 760, 762, 764, 766, 777, etc. Chipset 720 may also be coupled to the wireless antenna 778 to communicate with any device configured to transmit and/or receive wireless signals.

[0097] Chipset 720 connects to display device 740 via interface 726. Display 740 may be, for example, a liquid crystal display (LCD), a plasma display, cathode ray tube (CRT) display, or any other form of visual display device. In some embodiments of the disclosure, processor 710 and chipset 720 are integrated into a single SOC. In addition, chipset 720 connects to bus 750 and/or bus 755 that interconnect various elements 774, 760, 762, 764, and 766. Bus 750 and bus 755 may be interconnected via a bus bridge 772. In one embodiment, chipset 720 couples with a non-volatile memory 760, a mass storage device(s) 762, a keyboard/mouse 764, and a network interface 766 via interface 724 and/or 704, smart TV 776, consumer electronics 777, etc. [0098] In one embodiment, mass storage device(s) 762 can include, but not be limited to, a solid state drive, a hard disk drive, a universal serial bus flash memory drive, or any other form of computer data storage medium. In one embodiment, network interface 766 is implemented by any type of well-known network interface standard including, but not limited to, an Ethernet interface, a universal serial bus (USB) interface, a Peripheral Component Interconnect (PCI) Express interface, a wireless interface and/or any other suitable type of interface. In one embodiment, the wireless interface operates in accordance with, but is not limited to, the IEEE 802.11 standard and its related family, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.

[0099] While the modules shown in FIG. 7 are depicted as separate blocks within the system 700, the functions performed by some of these blocks may be integrated within a single semiconductor circuit or may be implemented using two or more separate integrated circuits. For example, although cache memory 716 is depicted as a separate block within processor 710, cache memory 716 or selected elements thereof can be incorporated into processor core 712.

[00100] It is noted that the system 700 described herein may include any suitable type of microelectronics packaging and configurations thereof, including, for example, system in a package (SiP), system on a package (SOP), package on package (PoP), interposer package, 3D stacked package, etc. Further, any suitable type of microelectronic components may be provided in the semiconductor packages, as described herein. For example, microcontrollers, microprocessors, baseband processors, digital signal processors, memory dies, field gate arrays, logic gate dies, passive component dies, MEMSs, surface mount devices, application specific integrated circuits, baseband processors, amplifiers, filters, combinations thereof, or the like may be packaged in the semiconductor packages, as disclosed herein. The semiconductor packages (for example, the semiconductor packages described in connection with any of FIGS. 1-6), as disclosed herein, may be provided in any variety of electronic device including consumer, industrial, military, communications, infrastructural, and/or other electronic devices.

[00101] In various embodiments, the devices, as described herein, may be used in connection with one or more processors. The one or more processors may include, without limitation, a central processing unit (CPU), a digital signal processor(s) (DSP), a reduced instruction set computer (RISC), a complex instruction set computer (CISC), a microprocessor, a microcontroller, a field programmable gate array (FPGA), or any combination thereof. The processors may also include one or more application specific integrated circuits (ASICs) or application specific standard products (ASSPs) for handling specific data processing functions or tasks. In certain embodiments, the processors may be based on an Intel® Architecture system and the one or more processors and any chipset included in an electronic device may be from a family of Intel® processors and chipsets, such as the Intel® Atom® processor(s) family or Intel-64 processors (for example, Sandy Bridge®, Ivy Bridge®, Haswell®, Broadwell®, Skylake®, etc.).

[00102] Additionally or alternatively, the devices, as described herein, may be used in connection with one or more additional memory chips. The memory may include one or more volatile and/or non-volatile memory devices including, but not limited to, magnetic storage devices, read-only memory (ROM), random access memory (RAM), dynamic RAM (DRAM), static RAM (SRAM), synchronous dynamic RAM (SDRAM), double data rate (DDR) SDRAM (DDR-SDRAM), RAM-BUS DRAM (RDRAM), flash memory devices, electrically erasable programmable read-only memory (EEPROM), non-volatile RAM (NVRAM), universal serial bus (USB) removable memory, or combinations thereof.

[00103] In example embodiments, the electronic device in which the disclosed devices are used and/or provided may be a computing device. Such a computing device may house one or more boards on which the devices may be disposed. The board may include a number of components including, but not limited to, a processor and/or at least one communication chip. The processor may be physically and electrically connected to the board through, for example, electrical connections of the devices. The computing device may further include a plurality of communication chips. For instance, a first communication chip may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth, and a second communication chip may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, and others. In various example embodiments, the computing device may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra- mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, combinations thereof, or the like. In further example embodiments, the computing device may be any other electronic device that processes data.

[00104] Example 1, the integrated circuit structure, comprising: a first source or drain; a first insulator on portion of the first source or drain; a gate on the first insulator; a second insulator on the gate; gate dielectrics on sidewalls of the first insulator, sidewall of the gate, and sidewalls of the second insulator; a layer comprising a semiconductor material disposed on a portion of the second insulator, sidewalls of the gate dielectrics, and the first source or drain; and a second source or drain on the layer.

[00105] Example 2 may include the integrated circuit structure of example 1 and/or some other example herein, further comprising a capacitor element connected to the second source or drain, the capacitor element comprising: a first capacitor material on a portion of the second source or drain; a dielectric on the first capacitor material; a second capacitor material on the dielectric; and a first contact on the second capacitor material.

[00106] Example 3 may include the integrated circuit structure of example 1 and/or some other example herein, wherein the first source or drain comprises a bitline and the second source or drain comprises a wordline.

[00107] Example 4 may include the integrated circuit structure of example 1 and/or some other example herein, wherein the first source or drain is substantially perpendicular to the second source or drain.

[00108] Example 5 may include the integrated circuit structure of example 1 and/or some other example herein, further comprising a third insulator on the integrated circuit structure, the third insulator comprising a via.

[00109] Example 6 may include the integrated circuit structure of example 5 and/or some other example herein, wherein the capacitor element is disposed in the via.

[00110] Example 7 may include the integrated circuit structure of example 1 and/or some other example herein, wherein the gate dielectric comprises hafnium and oxygen.

[00111] Example 8 may include the integrated circuit structure of example 1 and/or some other example herein, wherein the layer comprises a thin film transistor material.

[00112] Example 9, the memory device comprising a an integrated circuit structure and a capacitor element, the integrated circuit structure comprising: first source or drain; a first insulator on a portion of the first source or drain; a gate on the first insulator; a second insulator on the gate; gate dielectrics disposed on sidewalls of the first insulator, sidewalls of the gate, and sidewalls of the second insulator; a layer comprising a semiconductor material disposed on a portion of the second insulator, sidewalls of the gate dielectrics, and the first source or drain; and a second source or drain on the layer; wherein the integrated circuit structure is connected to the capacitor element by the second source or drain.

[00113] Example 10 may include the memory device of example 9 and/or some other example herein, wherein the integrated circuit structure is connected to the capacitor element by the second source or drain, the capacitor element comprising: a first capacitor material on a portion of the second source or drain; a dielectric on the first capacitor material; a second capacitor material on the dielectric; and a first contact on the second capacitor material.

[00114] Example 11 may include the memory device of example 9 and/or some other example herein, wherein the first source or drain comprises a bitline and the second source or drain comprises a wordline.

[00115] Example 12 may include the memory device of example 9 and/or some other example herein, wherein the first source or drain is substantially perpendicular to the second source or drain.

[00116] Example 13 may include the memory device of example 9 and/or some other example herein, further comprising a third insulator disposed on the integrated circuit structure, the third insulator comprising a via.

[00117] Example 14 may include the memory device of example 13 and/or some other example herein, wherein the capacitor element is disposed in the via.

[00118] Example 15 may include the memory device of example 9 and/or some other example herein, wherein the gate dielectrics comprise hafnium and oxygen.

[00119] Example 16 may include the memory device of example 9 and/or some other example herein, wherein the layer comprises a thin film transistor material.

[00120] Example 17 may include the memory device of example 9 and/or some other example herein, wherein the memory device comprises an embedded dynamic random access memory.

[00121] Example 18, the device comprising an integrated circuit structure, the integrated circuit structure comprising: a first source or drain; a first insulator on a portion of the first source or drain; a gate on the first insulator; a second insulator on the gate; gate dielectrics disposed on sidewalls of the first insulator, sidewalls of the gate, and the second insulator; a layer comprising a semiconductor material disposed on a portion of the second insulator, sidewalls of the gate dielectrics, and the first source or drain; and a second source or drain on the layer.

[00122] Example 19 may include the device of example 18 and/or some other example herein, wherein the integrated circuit structure is connected to a capacitor element by the second source or drain, the capacitor element comprising: a first capacitor material on a portion of the second source or drain; a dielectric on the first capacitor material; a second capacitor material on the dielectric; and a first contact on the second capacitor material. [00123] Example 20 may include the device of example 18 and/or some other example herein, further comprising a third insulator is disposed on the integrated circuit structure, the third insulator comprising a via.

[00124] Example 21 may include the device of example 18 and/or some other example herein, wherein the first source or drain comprises a bitline and the second source or drain comprises a wordline.

[00125] Example 22 may include the device of example 18 and/or some other example herein, wherein the first source or drain is substantially perpendicular to the second source or drain.

[00126] Example 23 may include the device of example 20 and/or some other example herein, wherein the capacitor element is disposed in the via.

[00127] Example 24 may include the device of example 18 and/or some other example herein, wherein the gate dielectric comprises hafnium and oxygen.

[00128] Example 25 may include the device of example 18 and/or some other example herein, wherein the layer comprises a thin film transistor material.

[00129] Example 26, the electronic device comprising: an integrated circuit structure, comprising: a first source or drain; a first insulator on a portion of the first source or drain; a gate on the first insulator; a second insulator on the gate; gate dielectrics on sidewalls of the first insulator, sidewall of the gate, and sidewalls of the second insulator; a layer comprising a semiconductor material disposed on a portion of the second insulator, sidewalls of the gate dielectrics, and the first source or drain; and a second source or drain on the layer.

[00130] Example 27 may include the electronic device of example 26 and/or some other example herein, further comprising a capacitor element connected to the second source or drain, the capacitor element comprising: a first capacitor material on a portion of the second source or drain; a dielectric on the first capacitor material; a second capacitor material on the dielectric; and a first contact on the second capacitor material.

[00131] Example 28 may include the electronic device of example 26 and/or some other example herein, wherein the first source or drain comprises a bitline and the second source or drain comprises a wordline.

[00132] Example 29 may include the electronic device of example 26 and/or some other example herein, wherein the first source or drain is substantially perpendicular to the second source or drain. [00133] Example 30 may include the electronic device of example 26 and/or some other example herein, further comprising a third insulator on the integrated circuit structure, the third insulator comprising a via.

[00134] Example 31 may include the electronic device of example 30 and/or some other example herein, wherein the capacitor element is disposed in the via.

[00135] Example 32 may include the electronic device of example 26 and/or some other example herein, wherein the gate dielectric comprises hafnium and oxygen.

[00136] Example 33 may include the electronic device of example 26 and/or some other example herein, wherein the layer comprises a thin film transistor material.

[00137] Various features, aspects, and embodiments have been described herein. The features, aspects, and embodiments are susceptible to combination with one another as well as to variation and modification, as will be understood by those having skill in the art. The present disclosure should, therefore, be considered to encompass such combinations, variations, and modifications.

[00138] The terms and expressions which have been employed herein are used as terms of description and not of limitation, and there is no intention, in the use of such terms and expressions, of excluding any equivalents of the features shown and described (or portions thereof), and it is recognized that various modifications are possible within the scope of the claims. Other modifications, variations, and alternatives are also possible. Accordingly, the claims are intended to cover all such equivalents.

[00139] While the disclosure includes various embodiments, including at least a best mode, it is to be understood that many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the foregoing description. Accordingly, the disclosure is intended to embrace all such alternatives, modifications, and variations, which fall within the scope of the included claims. All matters disclosed herein or shown in the accompanying drawings are to be interpreted in an illustrative and non-limiting sense.

[00140] This written description uses examples to disclose certain embodiments of the disclosure, including the best mode, and also to enable any person skilled in the art to practice certain embodiments of the disclosure, including making and using any apparatus, devices or systems and the performance of any incorporated methods and processes. The patentable scope of certain embodiments of the disclosure is defined in the claims, and may include other examples that occur to those skilled in the art. Such other examples are intended to be within the scope of the claims if they have structural elements that do not differ from the literal language of the claims, or if they include equivalent structural elements with insubstantial differences from the literal language of the claims.