TECHNICAL FIELD

[0001] This disclosure generally relates to integrated circuit structure, such as selector devices for semiconductor memories.

BACKGROUND

[0002] Modern electronics devices, such as non-volatile memories, may make use of various devices, for example, for the storage of bits. The memory devices can be distributed in arrays, for example, on the surface of the chip. One-bit memory cells can be grouped in small units called words which can be accessed together as a single memory address. Memory can be manufactured in word length that is usually a power of two, for example, 1, 2, 4 or 8 bits.

BRIEF DESCRIPTION OF THE FIGURES

[0003] Reference will now be made to the accompanying drawings, which are not necessarily drawn to scale, and wherein:

[0004] FIG. 1 shows an example diagram of a selector, in accordance with one or more example embodiments of the disclosure.

[0005] FIG. 2 shows example of various current-voltage curves associated with different devices, in accordance with one or more example embodiments of the disclosure.

[0006] FIG. 3A shows a flow diagram that represents various intermediate structures in the fabrication of a selector, in accordance with one or more example embodiments of the disclosure. FIG. 3B shows a flow diagram that represents a continuation of the flow diagram of FIG. 3A showing further intermediate structures in the fabrication of the selector, in accordance with one or more example embodiments of the disclosure.

[0007] FIG. 4 shows a flow diagram of intermediate structures used in the fabrication of a selector, in accordance with one or more example embodiments of the disclosure.

[0008] FIG. 5 shows an example flow diagram used in the fabrication of an example selector, in accordance with one or more example embodiments of the disclosure.

[0009] FIG. 6 depicts an example of a system, in accordance with one or more embodiments of the disclosure. DETAILED DESCRIPTION

[0010] Embodiments of the disclosure are described more fully hereinafter with reference to the accompanying drawings, in which example embodiments of the disclosure are shown. This disclosure may, however, be embodied in many different forms and should not be construed as limited to the example embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Like numbers refer to like, but not necessarily the same or identical, elements throughout.

[0011] The following embodiments are described in sufficient detail to enable at least those skilled in the art to understand and use the disclosure. It is to be understood that other embodiments would be evident based on the present disclosure and that process, mechanical, material, dimensional, process equipment, and parametric changes may be made without departing from the scope of the present disclosure.

[0012] In the following description, numerous specific details are given to provide a thorough understanding of various embodiments of the disclosure. However, it will be apparent that the disclosure may be practiced without these specific details. In order to avoid obscuring the present disclosure, some well-known system configurations and process steps may not be disclosed in full detail. Likewise, the drawings showing embodiments of the disclosure are semi-diagrammatic and not to scale and, particularly, some of the dimensions are for the clarity of presentation and may be exaggerated in the drawings. In addition, where multiple embodiments are disclosed and described as having some features in common, for clarity and ease of illustration, description, and comprehension thereof, similar and like features will ordinarily be described with like reference numerals even if the features are not identical.

[0013] The term“horizontal” as used herein may be defined as a direction parallel to a plane or surface (for example, surface of a substrate), regardless of its orientation. The term “vertical,” as used herein, may refer to a direction orthogonal to the horizontal direction as just described. Terms, such as“on,”“above,”“below,”“bottom,”“top,”� �side” (as in“sidewall”), “higher,” “lower,” “upper,” “over,” and“under,” may be referenced with respect to a horizontal plane, where the horizontal plane can include an x-y plane, a x-z plane, or a y-z plane, as the case may be. The term“processing” as used herein includes deposition of material or photoresist, patterning, exposure, development, etching, cleaning, ablating, polishing, and/or removal of the material or photoresist as required in formation a described structure. [0014]“An embodiment,”“various embodiments,” and the like indicate embodiment(s) so described may include particular features, structures, or characteristics, but not every embodiment necessarily includes the particular features, structures, or characteristics. Some embodiments may have some, all, or none of the features described for other embodiments. “First,”“second,”“third,” and the like describe a common object and indicate different instances of like objects are being referred to. Such adjectives do not imply objects so described must be in a given sequence, either temporally, spatially, in ranking, or in any other manner. “Connected” may indicate elements are in direct physical or electrical contact with each other and“coupled” may indicate elements co-operate or interact with each other, but they may or may not be in direct physical or electrical contact. Also, while similar or same numbers may be used to designate same or similar parts in different figures, doing so does not mean all figures including similar or same numbers constitute a single or same embodiment.

[0015] In various embodiments, disclosed herein are systems, methods, and apparatuses that generally relate to semiconductor devices. More particularly, some embodiments relate to memory devices, such as non-volatile memory (NVM) devices. Such memory devices, for example, can be incorporated into standalone memory devices, such as universal serial bus (USB) or other types of portable storage units, or integrated circuits (ICs), such as microcontrollers or system on chips (SoCs). The devices or ICs can be incorporated into or used with, for example, consumer electronic products, or relate to other types of devices.

[0016] Disclosed herein are systems, methods, and apparatuses for a selector device for use in connection with memory devices. In an embodiment, the selector can include two devices having asymmetric current-voltage characteristics that are electrically connected in an anti parallel configuration such that the selector device as a whole has a symmetric current-voltage characteristics. In an embodiment, the two devices can include an insulator-metal-transition (IMT) device or an IMT like device. In another embodiment the devices can include a diode, for example, a P-I-N diode, or a diode-like device. In an embodiment, the devices can include unipolar devices, that is, devices that predominantly conducts the flow of current in one voltage bias polarity, while suppressing the in the reverse voltage bias polarity.

[0017] In an embodiment, the selector can be integrated into interconnects associated with a memory array. In an embodiment, a first device having a first asymmetric current-voltage characteristic can be fabricated in between first interconnects, and a second device having a second asymmetric current-voltage characteristic can be fabricated between the same or between different interconnects. For example, the first device having a first asymmetric current-voltage characteristic can be fabricated between an interconnect M _x-i and an interconnect M _x ; the second device having a second asymmetric current-voltage characteristic can be fabricated between the interconnect M _x between interconnect M _x+i . In another embodiment the second device can be fabricated between the interconnect M _x-i and the interconnect M _x as well. In an embodiment, there can be insulator layers between the devices and interconnects associated with a selector.

[0018] In an embodiment, the selector can comprise two devices electrically connected in an antiparallel configuration such that the selector can have current-voltage characteristics that are substantially symmetric with respect to different voltage bias polarities. For example, the selector can have a first current-voltage characteristic in a first positive applied voltage regime, and a second current- voltage characteristic in a second positive applied voltage regime; further, the first and second current-voltage characteristic plots can be nearly mirror images of one another, within a predetermined tolerance for the current values at a given voltage.

[0019] In an embodiment, the selector as described herein can be used in connection with a memory arrays having a three-dimensional lattice-like architecture, such as an x-point memory array, or a cross-point memory array. In an embodiment, in such memory architectures, a selector and a memory device can be located at the intersection of each wordline and bitline. In an embodiment, the memory device used for each memory element in connection with the selector described herein can include transistor-based memory devices or negative-resistance memory devices. In an embodiment, the memory devices used for each memory element in connection with the selector described herein can include an spin transfer torque memory (STTM) device, or the like.

[0020] In an embodiment, the IMT or IMT-like device can include an insulator, such as an oxide material, for example, VO2, T13O5, T12O3, LaCoCb, NbCk, SmNiCF, and the like. In an embodiment, the IMT or IMT-like device can a device structure that includes a first electrode, an insulator (for example, an oxide), and a second electrode. For example, the IMT device can include a Cu electrode-oxide-inert electrode structure, a Ag-oxide-inert electrode structure, a Cu electrode-chalcogenide-inert electrode structure, or an Ag electrode-chalcogenide-inert electrode structure.

[0021] FIG. 1 shows an example diagram of a selector 100 in accordance with one or more example embodiments of the disclosure. In one embodiment, the selector 100 can represent a bipolar selector, that is, a selector that transmits current relatively equally under opposite voltage polarities (positive and negative), as discussed further below. [0022] In one embodiment, the selector 100 can include a first interconnect 102. In another embodiment, the first interconnect 102 can also be referred to as an Mc-i layer. In an embodiment, the selector 100 can include a second interconnect 104. In another embodiment, the second interconnect 104 can also be referred to as an Mc layer. In one embodiment, the selector 100 can include a third interconnect 106. In another embodiment, the third interconnect 106 can also be referred to as an Mc ₊ i layer. In one embodiment, the first interconnect 102, the second interconnect 104 and/or the third interconnect 106 can be provided and/or fabricated using backend of line (BEOL) techniques and processes.

[0023] In an embodiment, the first interconnect 102, the second interconnect 104, and the third interconnect 106 can include an inert metal or a doped semiconductor. In an embodiment, the first interconnect 102, the second interconnect 104, and the third interconnect 106 can include a platinum, gold, or similar material. Further examples of the conductive materials that may be used for the first interconnect 102, the second interconnect 104, and the third interconnect 106 can include, but are not limited to, metals, for example, copper, tungsten, tantalum, titanium, hafnium, zirconium, aluminum, silver, tin, lead, metal alloys, metal carbides, for example, hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, aluminum carbide, other conductive materials, or any combination thereof, and the like.

[0024] In an embodiment, the first interconnect 102, the second interconnect 104, and the third interconnect 106 can include a metallic material. In an embodiment, the first interconnect 102 can include an inert metal. In an embodiment, the metallic material can include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the first interconnect 102, the second interconnect 104, and the third interconnect 106 can comprise a semi-metallic material. Non limiting examples include arsenic, antimony, bismuth, a-tin (gray tin) and graphite, and mercury telluride (HgTe). Semi-metallic materials may also be any mixtures of such materials. In various embodiments, the first interconnect 102, the second interconnect 104, and the third interconnect 106 can comprise an intermetallic material. Non-limiting examples include gold and aluminum intermetallics, copper and tin intermetallics, tin and nickel intermetallics, tin and silver intermetallics, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the first interconnect 102, the second interconnect 104, and the third interconnect 106 can have a thickness of approximately 1 nm to approximately 400 nm, with an example thickness of approximately 15 nm to approximately 100 nm. In an embodiment, the first interconnect 102, the second interconnect 104, and the third interconnect 106 may be deposited by any suitable mechanism including, but not limited to, PVD, CVD, MOCVD, metal foil lamination, sputtering, metal paste deposition, combinations thereof, or the like.

[0025] In an embodiment, the selector 100 can include a second interconnect 104. In another embodiment, the second interconnect 104 can also be referred to as an Mx layer. In one embodiment, the selector 100 can include a third interconnect 106. In another embodiment, the third interconnect 106 can also be referred to as an Mc ₊ i layer. In one embodiment, the first interconnect 102, the second interconnect 104 and/or the third interconnect 106 can be provided and/or fabricated using backend of line (BEOL) techniques and processes.

[0026] In one embodiment, the selector 100 can include a first insulator 108. In another embodiment, the selector 100 can include a second insulator 110. In one embodiment, the selector 100 can include a third insulator 112.

[0027] In another embodiment the first insulator 108, the second insulator 110, and the third insulator 112 can include an oxide. In one embodiment the first insulator 108, the second insulator 110, and the third insulator 112 can include a dielectric. In an embodiment, the first insulator 108, the second insulator 110, and the third insulator 112 can include a silicon dioxide (S1O2), or a low-K material. In an embodiment, the first insulator 108, the second insulator 110, and the third insulator 112 can have a thickness of approximately 10 nm to approximately 400 nm, with an example thickness of approximately 100 nm to approximately 200 nm. In one embodiment, the first insulator 108, the second insulator 110, and the third insulator 112 can be deposited using PVD, CVD, MOCVD, and/or ALD, and the like.

[0028] In one embodiment, the selector 100 can include a first conductor 120. In another embodiment, the selector 100 can include a second conductor 130. In an embodiment, the first conductor 120 and the second conductor 130 can include an inert metal or a doped semiconductor. In an embodiment, the first conductor 120 and the second conductor 130 can include a platinum, gold, or similar material. Further examples of the conductive materials that may be used for the first conductor 120 and the second conductor 130 can include, but are not limited to, metals, for example, copper, tungsten, tantalum, titanium, hafnium, zirconium, aluminum, silver, tin, lead, metal alloys, metal carbides, for example, hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, aluminum carbide, other conductive materials, or any combination thereof, and the like.

[0029] In an embodiment, the first conductor 120 and the second conductor 130 can include a metallic material. In an embodiment, the first conductor 120 and the second conductor 130 can include an inert metal. In an embodiment, the metallic material can include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the first conductor 120 and the second conductor 130 can comprise a semi-metallic material. Non-limiting examples include arsenic, antimony, bismuth, a-tin (gray tin) and graphite, and mercury telluride (HgTe). Semi-metallic materials may also be any mixtures of such materials. In various embodiments, the first conductor 120 and the second conductor 130 can comprise an intermetallic material. Non-limiting examples include gold and aluminum intermetallics, copper and tin intermetallics, tin and nickel intermetallic s, tin and silver intermetallics, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the first conductor 120 and the second conductor 130 can have a thickness of approximately 1 nm to approximately 400 nm, with an example thickness of approximately 15 nm to approximately 100 nm. In an embodiment, the first conductor 120 and the second conductor 130 may be deposited by any suitable mechanism including, but not limited to, PVD, CVD, MOCVD, metal foil lamination, sputtering, metal paste deposition, combinations thereof, or the like.

[0030] In another embodiment, the selector 100 can include a first device 124. In another embodiment, the first device 124 can represent an IMT device. In another embodiment, the device 124 can represent a diode, for example, a P-N and/or a P-I-N junction-based diode. In one embodiment, the device 124 can include a multiple stack device comprising multiple layers including at least two electrodes and an active layer. In an embodiment, the electrodes can include a metal or a doped semiconductor. In an embodiment, the electrodes can include a platinum, gold, or similar material. Further examples of the conductive materials that may be used for the electrodes include, but are not limited to, metals, for example, copper, tungsten, tantalum, titanium, hafnium, zirconium, aluminum, silver, tin, lead, metal alloys, metal carbides, for example, hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, aluminum carbide, other conductive materials, or any combination thereof, and the like. In an embodiment, the electrodes can have a thickness of approximately 1 nm to approximately 400 nm, with an example thickness of approximately 15 nm to approximately 100 nm. In an embodiment, the electrodes may be deposited by any suitable mechanism including, but not limited to, PVD, CVD, MOCVD, metal foil lamination, sputtering, metal paste deposition, combinations thereof, or the like.

[0031] In an embodiment, the active layer can include an oxide, for example, a hafnium oxide material. In an embodiment, the active layer can include an amorphous oxide semiconductor (AOS) film, a polycrystalline silicon film, an amorphous silicon film, a polycrystalline TTT-V semiconductor film, a polycrystalline germanium, an amorphous germanium, an organic film, a transition metal dichalcogenide (TMD) film, or any combination thereof. In another embodiment, the active layer can include an oxide film, for example, a binary oxide (for example, ruthenium oxide, titanium oxide, tantalum oxide), a ternary oxide (e.g., InZnGaO).

[0032] In one embodiment, the selector 100 can include a second device 126. In another embodiment, the second device 126 can represent an IMT device. In another embodiment, the second device 126 can represent a diode, for example, a P-N and/or a P-I-N junction-based diode. In one embodiment, the second device 126 can include a multiple stack device comprising multiple layers including at least two electrodes and an active layer. In an embodiment, the electrodes can include a metal or a doped semiconductor. In an embodiment, the first electrode can include a platinum, gold, or similar material. Further examples of the conductive materials that may be used for the electrodes include, but are not limited to, metals, for example, copper, tungsten, tantalum, titanium, hafnium, zirconium, aluminum, silver, tin, lead, metal alloys, metal carbides, for example, hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, aluminum carbide, other conductive materials, or any combination thereof, and the like. In an embodiment, the electrodes can have a thickness of approximately 1 nm to approximately 400 nm, with an example thickness of approximately 15 nm to approximately 100 nm. In an embodiment, the electrodes may be deposited by any suitable mechanism including, but not limited to, PVD, CVD, MOCVD, metal foil lamination, sputtering, metal paste deposition, combinations thereof, or the like.

[0033] In an embodiment, the active layer can include an insulator such as an oxide, for example, a hafnium oxide material. In one embodiment, the active layer can include a thin film transistor material. In an embodiment, the active layer can include an amorphous oxide semiconductor (AOS) film, a polycrystalline silicon film, an amorphous silicon film, a polycrystalline III-V semiconductor film, a polycrystalline germanium, an amorphous germanium, an organic film, a transition metal dichalcogenide (TMD) film, or any combination thereof. In another embodiment, the active layer can include an oxide film, for example, a binary oxide (for example, ruthenium oxide, titanium oxide, tantalum oxide), a ternary oxide (e.g., InZnGaO).

[0034] In one embodiment, the device 124 and the device 126 can alternatively be located in- between the same interconnects (not shown). For example, the devices 124 and 126 can both be positioned between the first interconnect 102 and the second interconnect 104 or between the second interconnect 104 and the third interconnect 106.

[0035] FIG. 2 shows example plots 200 of various current-voltage curves associated with different devices in accordance with one or more example embodiments of the disclosure. In an embodiment, the plots 200 can include a plot of a first device 202. In another embodiment, the plot of the first device 202 can represent an asymmetric current voltage (IV) curve characteristics, to be discussed further below. In one embodiment, the plots 200 can include a plot of a second device 204. In another embodiment, the plot of the second device 204 can also represent an asymmetric current voltage curve characteristics. In one embodiment, the plots 200 can include a plot of a third device 206. In another embodiment, the plot of the third device 206 can represent a symmetric current voltage curve characteristics. In one embodiment, the plots 200 can include a plot of a fourth device 210. In another embodiment, the plot of the fourth device 210 can also represent symmetric current voltage curve characteristics.

[0036] Turning back to the plot of the first device 202, in an embodiment, the plot of the first device 202 can include a current 212 on the Y-axis versus a voltage 214 on the X-axis. In an embodiment, the plot of the first device 202 can include a first portion of the current voltage curve 216. In an embodiment, the first portion of the current voltage curve 216 can represent a positive bias portion of the plot of the first device 202. In an embodiment, the first portion of the current voltage curve 216 can represent the current voltage characteristics of an IMT device or an IMT-like device. In another embodiment, the first portion of the current voltage curve 216 can represent the device being active, that is, also in a low resistance state or a high current state.

[0037] In an embodiment, the plot of the first device 202 can further include a second portion of the current voltage curve 218. In an embodiment, the second portion of the current voltage curve 218 can represent a portion of the plot of the first device 202 that is in a positive bias. In an embodiment, the second portion of the current voltage curve 218 can represent a device that is in a non-active or a high resistance state or alternatively a low current state. In an embodiment, the second portion of the current-voltage curve 218 can represent a portion of the plot of the first device 202 that has a portion that is in a negative bias 220 and 222, to be discussed further, and a portion that is in a positive bias 219. In an embodiment, the positive bias portion 219 of the second portion of the current-voltage curve 218 can represent a high- resistance state and/or a low current state of the device. [0038] In an embodiment, the negative bias portion 220 of the second portion of the current voltage curve 218 can represent a high resistance state and/or a low current state of the device. In an embodiment, the second portion of the current voltage curve 218 further shows a breakdown voltage 221 that is associated with the negative bias portion 220 of the second portion of the current voltage curve 218. In an embodiment, the second portion of the current voltage curve 218 can further include a breakdown current regime 222. In the breakdown current regime 222, the device can operate in a low resistance state and/or a high current state, in negative bias. In an embodiment, the second portion of the current- voltage curve 218 can represent the current voltage characteristics of a device exhibiting diode-like behavior.

[0039] Turning back to the plot of the second device 204, in an embodiment, the plot of the second device 204 can include a current 222 on the Y-axis versus a voltage 224 on the X-axis. In an embodiment, the plot of the second device 204 can include a first portion of the current voltage curve 226. In an embodiment, the first portion of the current voltage curve 226 can represent a positive bias portion of the plot of the second device 204. In an embodiment, the first portion of the current voltage curve 226 can represent the current voltage characteristics of an IMT device or an IMT-like device. In another embodiment, the first portion of the current voltage curve 226 can represent the device being active, that is, also in a low resistance state or a high current state.

[0040] In an embodiment, the plot of the second device 204 can further include a second portion of the current voltage curve 228. In an embodiment, the second portion of the current voltage curve 228 can represent a portion of the plot of the second device 204 that is in a positive bias. In an embodiment, the second portion of the current voltage curve 228 can represent a device that is in a non-active or a high resistance state or alternatively a low current state. In an embodiment, the second portion of the current-voltage curve 228 can represent a portion of the plot of the second device 204 that has a portion that is in a negative bias 230 and 232, to be discussed further, and a portion that is in a positive bias 229. In an embodiment, the positive bias portion 229 of the second portion of the current- voltage curve 228 can represent a high-resistance state and/or a low current state of the device.

[0041] In an embodiment, the negative bias portion 230 of the second portion of the current voltage curve 228 can represent a high resistance state and/or a low current state of the device. In an embodiment, the second portion of the current voltage curve 228 further shows a breakdown voltage 231 that is associated with the negative bias portion 230 of the second portion of the current voltage curve 228. In an embodiment, the second portion of the current voltage curve 228 can further include a breakdown current regime 232. In the breakdown current regime 232, the device can operate in a low resistance state and/or a high current state, in negative bias. In an embodiment, the second portion of the current-voltage curve 228 can represent the current-voltage characteristics of a device exhibiting diode-like behavior.

[0042] In an embodiment, the plots 200 can include a plot of a third device 206. In one embodiment, the plot of the third device 206 can include a current 242 on the Y-axis versus a voltage 244 on the X-axis. In an embodiment, the plot of the third device 206 can include a first portion of a current voltage characteristic curve 246. In another embodiment, the first portion of the current voltage curve 246 can represent a negative bias portion of the plot of the third device 206. In an embodiment, the first portion of the current voltage curve 246 can represent an IMT device or an IMT-like device current voltage characteristics. In an embodiment, the first portion of the current voltage curve 246 can represent a device that is in an active, that is, low resistance and/or high current state.

[0043] In an embodiment, the plot of the third device 206 can further include a second portion of the current voltage curve 247. In an embodiment, the second portion of the current voltage curve 247 can represent a portion of the device that is in a positive bias. In an embodiment, the second portion of the current voltage curve 247 can represent an IMT-like operation of the device. In another embodiment, the second portion of the current voltage curve 247 can represent a device that is in an active state, that is, in a low resistance state and/or a high current state.

[0044] In an embodiment, the plot of the third device 206 can further include a third portion of a current voltage curve 248. In an embodiment, the third portion of the current voltage curve

248 can represent both a positive bias portion and a negative bias portion associated with the operation of the device. In an embodiment, the third portion of the current voltage curve 248 can represent a non-active state of a device, that is, a device that is in a high resistance state or a low current state.

[0045] In an embodiment, the plot of the third device 206 can include a fourth portion of the current voltage curve 249. In an embodiment, the fourth portion of the current voltage curve

249 can represent a negative bias operation of the device. In an embodiment, the fourth portion of the current voltage curve 249 can represent a non-active operation of the device, that is, a device in a high resistance state or a low current state.

[0046] In an embodiment, the plot of the third device 206 can further include a fifth portion of the current voltage curve 250. In an embodiment, the fifth portion of the current voltage curve 250 can represent a positive bias operation of the device. In another embodiment, the fifth portion of the current voltage curve 250 can represent a non-active state of the device, that is, a high resistance state or a low current state of the device.

[0047] In an embodiment, the plots 200 can further include a plot of a fourth device 210. In an embodiment, the plot of the fourth device 210 can further include a current 252 on the Y-axis versus a voltage 244 on the X-axis. In an embodiment, the plot of the fourth device 210 can include a current voltage curve 256. In an embodiment, the current voltage curve 256 can represent both a positive bias operation and a negative bias operation of the device. In an embodiment, the current voltage curve 256 can represent a diode-like operation of the device.

[0048] In an embodiment, the plot of the fourth device 210 can include a first portion of the current voltage curve 257. In an embodiment, the first portion of the current voltage curve 257 can represent a negative bias operation of the device. In an embodiment, the first portion of the current voltage curve 257 can represent an active state, that is, a low resistance state or a high current state of the device.

[0049] In an embodiment, the plot of the fourth device 210 can further include a transition voltage 260. In an embodiment, the transition voltage 260 can occur at a negative voltage.

[0050] In an embodiment, the plot of the fourth device 210 can include a second portion 262. In another embodiment, the second portion 262 can represent a device that is operating under a negative bias. In an embodiment, the second portion of the current voltage curve 262 can further include a device that is active, that is, in a low resistance state or a high current state.

[0051] In an embodiment, the plot of the fourth device 210 can further include a third portion of the current voltage curve 258. In an embodiment, the third portion of the current voltage curve 258 can represent a device under positive bias. In an embodiment, the third portion of the current voltage curve 258 can represent a device in a high resistance state or in a low current state, that is, in inactive mode of operation.

[0052] In an embodiment, the plot of the fourth device 210 can further include a transition voltage 259. In another embodiment, the transition voltage 259 can represent a positive voltage.

[0053] In an embodiment, the plot of the fourth device 210 can further include a fourth portion of the current voltage curve 264. In an embodiment, the fourth portion of the current voltage curve 264 can represent a device under positive bias operation. In an embodiment, the fourth portion of the current voltage curve 264 can represent an active mode of operation of the device, that is, a device in a low resistance state or a high current state. [0054] FIG. 3A shows a flow diagram 300 that represents the fabrication of a selector in accordance with one or more example embodiments of the disclosure. In an embodiment, the flow diagram 300 shows a first structure 301 in the fabrication of the selector. In an embodiment, the first structure 301 can include a first interconnect 302. In an embodiment, the first interconnect 302 can include an inert metal or a doped semiconductor. In an embodiment, the first interconnect 302 can include a platinum, gold, or similar material. Further examples of the conductive materials that may be used for first interconnect 302 can include, but are not limited to, metals, for example, copper, tungsten, tantalum, titanium, hafnium, zirconium, aluminum, silver, tin, lead, metal alloys, metal carbides, for example, hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, aluminum carbide, other conductive materials, or any combination thereof, and the like.

[0055] In an embodiment, the first interconnect 302 can include a metallic material. In an embodiment, the first interconnect 302 can include an inert metal. In an embodiment, the metallic material can include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the first interconnect 302 can comprise a semi-metallic material. Non-limiting examples include arsenic, antimony, bismuth, a-tin (gray tin) and graphite, and mercury telluride (HgTe). Semi-metallic materials may also be any mixtures of such materials. In various embodiments, the first interconnect 302 can comprise an intermetallic material. Non-limiting examples include gold and aluminum intermetallics, copper and tin intermetallics, tin and nickel intermetallics, tin and silver intermetallics, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the first interconnect 302 can have a thickness of approximately 1 nm to approximately 400 nm, with an example thickness of approximately 15 nm to approximately 100 nm. In an embodiment, the first interconnect 302 may be deposited by any suitable mechanism including, but not limited to, PVD, CVD, MOCVD, metal foil lamination, sputtering, metal paste deposition, combinations thereof, or the like.

[0056] In another embodiment, the first structure 301 can include a first device 304. In another embodiment, the first device 304 can represent an IMT device or an IMT-like device. In an embodiment, the first device 304 can represent a diode or diode-like device. In an embodiment, the first device 304 can represent a PN and/or a P-I-N diode device. In an embodiment, the first device 304 can include a unipolar device, that is, a device that predominantly conducts the flow of current in one voltage bias polarity, while suppressing the in the reverse voltage bias polarity. In an embodiment, the first device 304 including an IMT or IMT-like device can include an oxide material, for example, VO2, T13O5, T12O3, LaCoCb, NbCk, SmNiCb, and the like. In an embodiment, the IMT or IMT-like device can a device structure that includes a first electrode, an insulator such as an oxide, and a second electrode. For example, the IMT device can include a Cu electrode-oxide-inert electrode structure, a Ag-oxide-inert electrode structure, a Cu electrode-chalcogenide-inert electrode structure, or an Ag electrode-chalcogenide-inert electrode structure.

[0057] In an embodiment, the first structure 301 can further include a resist 306 that may be used to pattern the first device 304. In one embodiment, patterning and/or processing the first device 304 using the resist 306 can further include exposing the resist 306 using a mask. The mask can include, for example, a photomask, which can refer to an opaque plate with holes or transparencies that allow light to shine through in a defined pattern. In one embodiment, the photomask can include transparent fused silica blanks covered with a pattern defined with a chrome metal-absorbing film. In another embodiment, the photomask can be used at a predetermined wavelength, including, but not be limited to, approximately 436 nm, approximately 365 nm, approximately 248 nm, and approximately 193 nm. In one embodiment, there can be a one-to-one correspondence between the mask pattern and the resist 306 pattern, for example, using one-to-one mask aligners. In other embodiments, steppers and scanners with reduction optics can be used to project and shrink the pattern by four or five times onto the surface of the resist 306. To achieve complete coverage, the resist 306 can be repeatedly "stepped" from position to position under the optical column until full exposure is achieved. In one embodiment, processing the resist 306 can further include developing the first resist 306 using an ultraviolet light source. In one embodiment, the light types that can be used to image the resist 306 can include, but not be limited to, UV, DUV (Deep UV), and the g and I lines having wavelength of approximately 436 nm and approximately 365 nm respectively of a mercury-vapor lamp. In various embodiments, the development of the resist 306 can include an exposure to the ultraviolet light source for a few seconds through the mask. The areas of the resist 306 which are exposed stay, and the rest of the resist 306 is developed. In one embodiment, the developing light wavelength parameter can be related to the thickness of the applied resist 306, with thinner layers corresponding to shorter wavelengths. This can permit a reduced aspect ratio and a reduced minimum feature size.

[0058] In one embodiment, a portion of the first device 304 not covered by the resist 306 can be removed using an etching process. In one embodiment, the etching process can include, for example, a dry etch. In one embodiment, the dry etch can include, for example, a plasma-based and/or a mechanical-based etch. In one embodiment, the etching process can include, for example, a wet etch. The wet etching process can include, for example, any suitable chemicals for the removal of the portion of the first device 304.

[0059] In an embodiment, the flow diagram 300 further includes a second structure 303 that represents the fabrication of the selector. In an embodiment, the second structure 303 includes an insulator 308. In another embodiment the insulator 308 can include an oxide. In one embodiment the insulator 308 can include a dielectric. In an embodiment, the insulator 308 can include a silicon dioxide (SiC ), or a low-K material. In an embodiment, the insulator 308 can have a thickness of approximately 2 nm to approximately 10 nm, with an example thickness of approximately 3 nm to approximately 5 nm In one embodiment, the insulator 308 can be deposited using PVD, CVD, MOCVD, and/or ALD, and the like.

[0060] In another embodiment, the flow diagram 300 can include a third structure 305 in the fabrication of the selector. In an embodiment, the third structure 305 can include a resist 310. In an embodiment, the resist 310 can be used to pattern the insulator 308. In one embodiment, patterning and/or processing the insulator 308 using the resist 310 can further include exposing the resist 310 using a mask. The mask can include, for example, a photomask, which can refer to an opaque plate with holes or transparencies that allow light to shine through in a defined pattern. In one embodiment, the photomask can include transparent fused silica blanks covered with a pattern defined with a chrome metal-absorbing film. In another embodiment, the photomask can be used at a predetermined wavelength, including, but not be limited to, approximately 436 nm, approximately 365 nm, approximately 248 nm, and approximately 193 nm. In one embodiment, there can be a one-to-one correspondence between the mask pattern and the resist 310 pattern, for example, using one-to-one mask aligners. In other embodiments, steppers and scanners with reduction optics can be used to project and shrink the pattern by four or five times onto the surface of the resist 310. To achieve complete coverage, the resist 310 can be repeatedly "stepped" from position to position under the optical column until full exposure is achieved. In one embodiment, processing the resist 306 can further include developing the resist 310 using an ultraviolet light source. In one embodiment, the light types that can be used to image the resist 310 can include, but not be limited to, UV, DUV (Deep UV), and the g and I lines having wavelength of approximately 436 nm and approximately 365 nm respectively of a mercury-vapor lamp. In various embodiments, the development of the resist 310 can include an exposure to the ultraviolet light source for a few seconds through the mask. The areas of the resist 310 which are exposed stay, and the rest of the resist 310 is developed. In one embodiment, the developing light wavelength parameter can be related to the thickness of the applied resist 310, with thinner layers corresponding to shorter wavelengths. This can permit a reduced aspect ratio and a reduced minimum feature size.

[0061] In one embodiment, a portion of the insulator 308 not covered by the resist 310 can be removed using an etching process. In one embodiment, the etching process can include, for example, a dry etch. In one embodiment, the dry etch can include, for example, a plasma-based and/or a mechanical-based etch. In one embodiment, the etching process can include, for example, a wet etch. The wet etching process can include, for example, any suitable chemicals for the removal of the portion of the insulator 308.

[0062] In an embodiment, the flow diagram 300 can include a fourth structure 307. In an embodiment, the fourth structure 307 can include a conductor 314. In an embodiment, the conductor 314 can include an inert metal or a doped semiconductor. In an embodiment, the conductor 314 can include a platinum, gold, or similar material. Further examples of the conductive materials that may be used for conductor 314 can include, but are not limited to, metals, for example, copper, tungsten, tantalum, titanium, hafnium, zirconium, aluminum, silver, tin, lead, metal alloys, metal carbides, for example, hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, aluminum carbide, other conductive materials, or any combination thereof, and the like.

[0063] In an embodiment, the conductor 314 can include a metallic material. In an embodiment, the conductor 314 can include an inert metal. In an embodiment, the metallic material can include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the conductor 314 can comprise a semi-metallic material. Non-limiting examples include arsenic, antimony, bismuth, a-tin (gray tin) and graphite, and mercury telluride (HgTe). Semi-metallic materials may also be any mixtures of such materials. In various embodiments, the conductor 314 can comprise an intermetallic material. Non-limiting examples include gold and aluminum intermetallics, copper and tin intermetallics, tin and nickel intermetallic s, tin and silver intermetallic s, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the conductor 314 can have a thickness of approximately 1 nm to approximately 400 nm, with an example thickness of approximately 15 nm to approximately 100 nm. In an embodiment, the conductor 314 may be deposited by any suitable mechanism including, but not limited to, PVD, CVD, MOCVD, metal foil lamination, sputtering, metal paste deposition, combinations thereof, or the like.

[0064] In an embodiment, the flow diagram 300 can further include a fifth structure 309 that represents the fabrication of the selector. In an embodiment, the fifth structure 309 can further include a second interconnect 316. In an embodiment, the second interconnect 316 can include an inert metal or a doped semiconductor. In an embodiment, the second interconnect 316 can include a platinum, gold, or similar material. Further examples of the conductive materials that may be used for second interconnect 316 can include, but are not limited to, metals, for example, copper, tungsten, tantalum, titanium, hafnium, zirconium, aluminum, silver, tin, lead, metal alloys, metal carbides, for example, hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, aluminu carbide, other conductive materials, or any combination thereof, and the like.

[0065] In an embodiment, the second interconnect 316 can include a metallic material. In an embodiment, the second interconnect 316 can include an inert metal. In an embodiment, the metallic material can include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the second interconnect 316 can comprise a semi-metallic material. Non-limiting examples include arsenic, antimony, bismuth, a-tin (gray tin) and graphite, and mercury telluride (HgTe). Semi-metallic materials may also be any mixtures of such materials. In various embodiments, the second interconnect 316 can comprise an intermetallic material. Non limiting examples include gold and aluminum intermetallics, copper and tin intermetallic s, tin and nickel intermetallics, tin and silver intermetallics, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the second interconnect 316 can have a thickness of approximately 1 nm to approximately 400 nm, with an example thickness of approximately 15 nm to approximately 100 nm. In an embodiment, the second interconnect 316 may be deposited by any suitable mechanism including, but not limited to, PVD, CVD, MOCVD, metal foil lamination, sputtering, metal paste deposition, combinations thereof, or the like.

[0066] FIG. 3B shows a flow diagram 317 that represents various intermediate structures in the fabrication of the selector in accordance with one or more example embodiments of the disclosure. In an embodiment, the flow diagram 317 can include a sixth structure 311 representing the fabrication of the selector. In an embodiment, the sixth structure 311 can include a resist 318. In an embodiment, the resist 318 can be used to pattern the second interconnect 316. In one embodiment, patterning and/or processing the second interconnect 316 using the resist 318 can further include exposing the resist 318 using a mask, as described above. In one embodiment, a portion of the second interconnect 316 not covered by the resist 318 can be removed using an etching process. In one embodiment, the etching process can include, for example, a dry etch. In one embodiment, the dry etch can include, for example, a plasma-based and/or a mechanical-based etch. In one embodiment, the etching process can include, for example, a wet etch. The wet etching process can include, for example, any suitable chemicals for the removal of the portion of the second interconnect 316.

[0067] In an embodiment, the flow diagram 317 can further include a seventh structure 313 that represents the fabrication of the selector. In an embodiment, the seventh structure 313 can include an insulator 320. In another embodiment the insulator 320 can include an oxide. In one embodiment the insulator 320 can include a dielectric. In an embodiment, the insulator 320 can include a silicon dioxide (SiCk), or a low-K material. In an embodiment, the insulator 320 can have a thickness of approximately 2 nm to approximately 10 nm, with an example thickness of approximately 3 nm to approximately 5 nm. In one embodiment, the insulator 320 can be deposited using PVD, CVD, MOCVD, and/or ALD, and the like.

[0068] In an embodiment, the flow diagram 300 can include an eighth structure 315 representing the fabrication of the selector. In an embodiment, the eighth structure 315 can include a second device 322. In another embodiment, the second device 322 can represent an IMT device or an IMT-like device. In an embodiment, the second device 322 can represent a diode or diode-like device. In an embodiment, the second device 322 can represent a PN and/or a P-I-N diode device. In an embodiment, the second device 322 can include a unipolar device, that is, a device that predominantly conducts the flow of current in one voltage bias polarity, while suppressing the in the reverse voltage bias polarity. In an embodiment, the second device 322 including an IMT or IMT-like device can include an oxide material, for example, VO2, T13O5, T12O3, LaCoCk, NbCk, SmNiCk, and the like. In an embodiment, the IMT or IMT-like device can a device structure that includes a first electrode, an insulator such as an oxide, and a second electrode. For example, the IMT device can include a Cu electrode-oxide-inert electrode structure, a Ag-oxide-inert electrode structure, a Cu electrode-chalcogenide-inert electrode structure, or an Ag electrode-chalcogenide-inert electrode structure. In an embodiment, the second device 322 can have an opposite polarity, that is, can have electrodes that are reversed in position in terms of top and bottom with respect to the patterned first device 308. [0069] In another embodiment, the eighth structure 315 can include a resist 324. In an embodiment, the resist 324 can be used to pattern the second device 322. In one embodiment, patterning and/or processing the second device 322 using the resist 324 can further include exposing the resist 324 using a mask, as described above. In one embodiment, a portion of the second device 322 not covered by the resist 324 can be removed using an etching process. In one embodiment, the etching process can include, for example, a dry etch. In one embodiment, the dry etch can include, for example, a plasma-based and/or a mechanical-based etch. In one embodiment, the etching process can include, for example, a wet etch. The wet etching process can include, for example, any suitable chemicals for the removal of the portion of the second device 322.

[0070] FIG. 4 shows another flow diagram 400 of intermediate structures used in the fabrication of another example selector, in accordance with one or more example embodiments of the disclosure. In an embodiment, the flow diagram 400 can include a first structure 401 that represents the fabrication of the selector.

[0071] In an embodiment, the first structure 401 can include a first interconnect 402. In an embodiment, the first interconnect 402 can include a metallic material. In an embodiment, the first interconnect 402 can include an inert metal. In an embodiment, the metallic material can include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the first interconnect 402 can comprise a semi-metallic material. Non-limiting examples include arsenic, antimony, bismuth, a-tin (gray tin) and graphite, and mercury telluride (HgTe). Semi- metallic materials may also be any mixtures of such materials. In various embodiments, the first interconnect 402 can comprise an intermetallic material. Non-limiting examples include gold and aluminum intermetallics, copper and tin intermetallic s, tin and nickel intermetallics, tin and silver intermetallics, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the first interconnect 402 can have a thickness of approximately 1 nm to approximately 400 nm, with an example thickness of approximately 15 nm to approximately 100 nm. In an embodiment, the first interconnect 402 may be deposited by any suitable mechanism including, but not limited to, PVD, CVD, MOCVD, metal foil lamination, sputtering, metal paste deposition, combinations thereof, or the like.

[0072] In another embodiment, the first structure 401 can include a first device 404. In another embodiment, the first device 404 can represent an IMT device or an IMT-like device. In an embodiment, the first device 404 can represent a diode or diode-like device. In an embodiment, the first device 404 can represent a PN and/or a P-I-N diode device. In an embodiment, the first device 404 can include a unipolar device, that is, a device that predominantly conducts the flow of current in one voltage bias polarity, while suppressing the in the reverse voltage bias polarity. In an embodiment, the first device 404 including an IMT or IMT-like device can include an oxide material, for example, VO2, T13O5, T12O3, LaCoCb, NbCk, SmNiCb, and the like. In an embodiment, the IMT or IMT-like device can a device structure that includes a first electrode, an insulator such as an oxide, and a second electrode. For example, the IMT device can include a Cu electrode-oxide-inert electrode structure, a Ag-oxide-inert electrode structure, a Cu electrode-chalcogenide-inert electrode structure, or an Ag electrode-chalcogenide-inert electrode structure.

[0073] In an embodiment, the first structure 401 can further include a resist 406. In an embodiment, the resist 406 can be used to pattern the first device 404. In one embodiment, patterning and/or processing the first device 404 using the resist 406 can further include exposing the resist 406 using a mask, as described above. In one embodiment, a portion of the first device 404 not covered by the resist 406 can be removed using an etching process. In one embodiment, the etching process can include, for example, a dry etch. In one embodiment, the dry etch can include, for example, a plasma-based and/or a mechanical-based etch. In one embodiment, the etching process can include, for example, a wet etch. The wet etching process can include, for example, any suitable chemicals for the removal of the portion of the first device 404.

[0074] In an embodiment, the flow diagram 400 can include a second structure in the fabrication of the selector 403. In an embodiment, the second structure 403 can include an insulator 408. In another embodiment the insulator 408 can include an oxide. In one embodiment the insulator 408 can include a dielectric. In an embodiment, the insulator 408 can include a silicon dioxide (S1O2), or a low-K material. In an embodiment, the insulator 408 can have a thickness of approximately 2 nm to approximately 10 nm, with an example thickness of approximately 3 nm to approximately 5 nm. In one embodiment, the insulator 408 can be deposited using PVD, CVD, MOCVD, and/or ALD, and the like.

[0075] In an embodiment, the flow diagram 400 can further include a third structure 405 in the fabrication of the selector. In an embodiment, the third structure 405 can include a resist 410. In an embodiment, the resist 410 can be used to pattern the insulator 408. In one embodiment, patterning and/or processing the insulator 408 using the resist 410 can further include exposing the resist 410 using a mask, as described above. In one embodiment, a portion of the insulator 408 not covered by the resist 410 can be removed using an etching process. In one embodiment, the etching process can include, for example, a dry etch. In one embodiment, the dry etch can include, for example, a plasma-based and/or a mechanical-based etch. In one embodiment, the etching process can include, for example, a wet etch. The wet etching process can include, for example, any suitable chemicals for the removal of the portion of the insulator 408.

[0076] In an embodiment, the flow diagram 400 can include a fourth structure 407 in the fabrication of the selector. In an embodiment, the fourth structure 407 can include a second device 414. In another embodiment, the second device 414 can represent an IMT device or an IMT-like device. In an embodiment, the second device 414 can represent a diode or diode-like device. In an embodiment, the second device 414 can represent a PN and/or a P-I-N diode device. In an embodiment, the second device 414 can include a unipolar device, that is, a device that predominantly conducts the flow of current in one voltage bias polarity, while suppressing the in the reverse voltage bias polarity. In an embodiment, the second device 414 including an IMT or IMT-like device can include an oxide material, for example, VO2, T13O5, T12O3, LaCoCb, NbCk, SmNiCb, and the like. In an embodiment, the IMT or IMT-like device can a device structure that includes a first electrode, an oxide, and a second electrode. For example, the IMT device can include a Cu electrode-Oxide-inert electrode structure, a Ag-oxide-inert electrode structure, a Cu electrode-chalcogenide-inert electrode structure, or an Ag electrode- chalcogenide-inert electrode structure. In an embodiment, the second device 414 can have an opposite polarity, that is, can have electrodes that are reversed in position in terms of top and bottom with respect to the patterned first device 404.

[0077] In an embodiment, the fourth structure 407 can include second interconnect 416. In an embodiment, the second interconnect 416 can include a metallic material. In an embodiment, the second interconnect 416 can include an inert metal. In an embodiment, the metallic material can include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the second interconnect 416 can comprise a semi-metallic material. Non-limiting examples include arsenic, antimony, bismuth, a-tin (gray tin) and graphite, and mercury telluride (HgTe). Semi- metallic materials may also be any mixtures of such materials. In various embodiments, the second interconnect 416 can comprise an intermetallic material. Non-limiting examples include gold and aluminum intermetallics, copper and tin intermetallics, tin and nickel intermetallics, tin and silver intermetallics, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the second interconnect 416 can have a thickness of approximately 1 nm to approximately 400 nm, with an example thickness of approximately 15 nm to approximately 100 nm. In an embodiment, the second interconnect 416 may be deposited by any suitable mechanism including, but not limited to, PVD, CVD, MOCVD, metal foil lamination, sputtering, metal paste deposition, combinations thereof, or the like.

[0078] FIG. 5 shows an example flow diagram 500 used in the fabrication of an example selector, in accordance with one or more example embodiments of the disclosure. At block 502, a first interconnect can be provided. In an embodiment, the first interconnect can include an inert metal or a doped semiconductor. In an embodiment, the first interconnect can include a platinum, gold, or similar material. Further examples of the conductive materials that may be used for the first interconnect can include, but are not limited to, metals, for example, copper, tungsten, tantalum, titanium, hafnium, zirconium, aluminum, silver, tin, lead, metal alloys, metal carbides, for example, hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, aluminum carbide, other conductive materials, or any combination thereof, and the like.

[0079] In an embodiment, the first interconnect can include a metallic material. In an embodiment, the first interconnect can include an inert metal. In an embodiment, the metallic material can include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the first interconnect can comprise a semi-metallic material. Non-limiting examples include arsenic, antimony, bismuth, a-tin (gray tin) and graphite, and mercury telluride (HgTe). Semi-metallic materials may also be any mixtures of such materials. In various embodiments, the first interconnect can comprise an intermetallic material. Non-limiting examples include gold and aluminum intermetallics, copper and tin intermetallics, tin and nickel intermetallics, tin and silver intermetallics, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the first interconnect can have a thickness of approximately 1 nm to approximately 400 nm, with an example thickness of approximately 15 nm to approximately 100 nm. In an embodiment, the first interconnect may be deposited by any suitable mechanism including, but not limited to, PVD, CVD, MOCVD, metal foil lamination, sputtering, metal paste deposition, combinations thereof, or the like. [0080] At block 504, a first device can be provided on the first interconnect. In another embodiment, the first device can represent an IMT device or an IMT-like device. In an embodiment, the first device can represent a diode or diode-like device. In an embodiment, the first device can represent a PN and/or a P-I-N diode device. In an embodiment, the first device can include a unipolar device, that is, a device that predominantly conducts the flow of current in one voltage bias polarity, while suppressing the in the reverse voltage bias polarity. In an embodiment, the first device including an IMT or IMT-like device can include an oxide material, for example, VO2, T13O5, T12O3, LaCoCb, NbCk, SmNiCb, and the like. In an embodiment, the IMT or IMT-like device can a device structure that includes a first electrode, an insulator such as an oxide, and a second electrode. For example, the IMT device can include a Cu electrode-oxide-inert electrode structure, a Ag-oxide-inert electrode structure, a Cu electrode-chalcogenide-inert electrode structure, or an Ag electrode-chalcogenide-inert electrode structure.

[0081] At block 506, a portion of the first device can be removed. In one embodiment, the removal of the portion of the first device can be performed using an etching process. In one embodiment, the etching process can include, for example, a dry etch. In one embodiment, the dry etch can include, for example, a plasma-based and/or a mechanical-based etch. In one embodiment, the etching process can include, for example, a wet etch. The wet etching process can include, for example, any suitable chemicals for the removal of the portion of the first device.

[0082] At block 508, a first insulator can be deposited on the first interconnect. In another embodiment the first insulator can include an oxide. In one embodiment the first insulator can include a dielectric. In an embodiment, the first insulator can include a silicon dioxide (S1O2), or a low-K material. In an embodiment, the first insulator can have a thickness of approximately 2 nm to approximately 10 nm, with an example thickness of approximately 3 nm to approximately 5 nm. In one embodiment, the first insulator can be deposited using PVD, CVD, MOCVD, and/or ALD, and the like.

[0083] At block 510, a portion of the first insulator can be removed. In one embodiment, the removal of the portion of the first insulator can be performed using an etching process. In one embodiment, the etching process can include, for example, a dry etch. In one embodiment, the dry etch can include, for example, a plasma-based and/or a mechanical-based etch. In one embodiment, the etching process can include, for example, a wet etch. The wet etching process can include, for example, any suitable chemicals for the removal of the portion of the first insulator.

[0084] At block 512, a first conductor can be deposited in the removed portion of the first insulator. In an embodiment, the first connector can include an inert metal or a doped semiconductor. In an embodiment, the first connector can include a platinum, gold, or similar material. Further examples of the conductive materials that may be used for the first connector can include, but are not limited to, metals, for example, copper, tungsten, tantalum, titanium, hafnium, zirconium, aluminum, silver, tin, lead, metal alloys, metal carbides, for example, hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, aluminum carbide, other conductive materials, or any combination thereof, and the like.

[0085] In an embodiment, the first conductor can include a metallic material. In an embodiment, the first conductor can include an inert metal. In an embodiment, the metallic material can include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the first conductor can comprise a semi-metallic material. Non-limiting examples include arsenic, antimony, bismuth, a-tin (gray tin) and graphite, and mercury telluride (HgTe). Semi-metallic materials may also be any mixtures of such materials. In various embodiments, the first conductor can comprise an intermetallic material. Non-limiting examples include gold and aluminum intermetallics, copper and tin intermetallics, tin and nickel intermetallic s, tin and silver intermetallics, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the first conductor can have a thickness of approximately 1 nm to approximately 400 nm, with an example thickness of approximately 15 nm to approximately 100 nm. In an embodiment, the first conductor may be deposited by any suitable mechanism including, but not limited to, PVD, CVD, MOCVD, metal foil lamination, sputtering, metal paste deposition, combinations thereof, or the like.

[0086] At block 514, a second interconnect can be deposited on the first insulator, the first device and the first conductor. In an embodiment, the second interconnect can include an inert metal or a doped semiconductor. In an embodiment, the second interconnect can include a platinum, gold, or similar material. Further examples of the conductive materials that may be used for the second interconnect can include, but are not limited to, metals, for example, copper, tungsten, tantalum, titanium, hafnium, zirconium, aluminum, silver, tin, lead, metal alloys, metal carbides, for example, hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, aluminum carbide, other conductive materials, or any combination thereof, and the like.

[0087] In an embodiment, the second interconnect can include a metallic material. In an embodiment, the second interconnect can include an inert metal. In an embodiment, the metallic material can include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the second interconnect can comprise a semi-metallic material. Non-limiting examples include arsenic, antimony, bismuth, a-tin (gray tin) and graphite, and mercury telluride (HgTe). Semi- metallic materials may also be any mixtures of such materials. In various embodiments, the second interconnect can comprise an intermetallic material. Non-limiting examples include gold and aluminum intermetallics, copper and tin intermetallic s, tin and nickel intermetallics, tin and silver intermetallics, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the second interconnect can have a thickness of approximately 1 nm to approximately 400 nm, with an example thickness of approximately 15 nm to approximately 100 nm. In an embodiment, the second interconnect may be deposited by any suitable mechanism including, but not limited to, PVD, CVD, MOCVD, metal foil lamination, sputtering, metal paste deposition, combinations thereof, or the like.

[0088] At block 516, a portion of the second interconnect can be removed. In one embodiment, the removal of the portion of the second interconnect can be performed using an etching process. In one embodiment, the etching process can include, for example, a dry etch. In one embodiment, the dry etch can include, for example, a plasma-based and/or a mechanical-based etch. In one embodiment, the etching process can include, for example, a wet etch. The wet etching process can include, for example, any suitable chemicals for the removal of the portion of the second interconnect.

[0089] At block 518, a second insulator can be deposited in the removed portions of the second interconnect on the first insulator. In another embodiment the second insulator can include an oxide. In one embodiment the second insulator can include a dielectric. In an embodiment, the second insulator can include a silicon dioxide (SiC ), or a low-K material. In an embodiment, the second insulator can have a thickness of approximately 2 nm to approximately 10 nm, with an example thickness of approximately 3 nm to approximately 5 nm. In one embodiment, the second insulator can be deposited using PVD, CVD, MOCVD, and/or ALD, and the like. [0090] At block 520, a second device can be deposited on the second insulator and the second interconnect. In another embodiment, the second device can represent an IMT device or an IMT-like device. In an embodiment, the second device can represent a diode or diode-like device. In an embodiment, the second device can represent a PN and/or a P-I-N diode device. In an embodiment, the second device can include a unipolar device, that is, a device that predominantly conducts the flow of current in one voltage bias polarity, while suppressing the in the reverse voltage bias polarity. In an embodiment, the second device including an IMT or IMT-like device can include an oxide material, for example, VO2, T13O5, T12O3, LaCoCb, NbCk, SmNiCb, and the like. In an embodiment, the IMT or IMT-like device can a device structure that includes a first electrode, an insulator such as an oxide, and a second electrode. For example, the IMT device can include a Cu electrode-oxide-inert electrode structure, a Ag- oxide-inert electrode structure, a Cu electrode-chalcogenide-inert electrode structure, or an Ag electrode-chalcogenide-inert electrode structure. In an embodiment, the second device can have an opposite polarity, that is, can have electrodes that are reversed in position in terms of top and bottom with respect to the patterned first device.

[0091] At block 522, a portion of the second device can be removed. In one embodiment, the removal of the portion of the second device can be performed using an etching process. In one embodiment, the etching process can include, for example, a dry etch. In one embodiment, the dry etch can include, for example, a plasma-based and/or a mechanical-based etch. In one embodiment, the etching process can include, for example, a wet etch. The wet etching process can include, for example, any suitable chemicals for the removal of the portion of the second device.

[0092] At block 524, a second conductor can be deposited and a third insulator can be deposited on the second insulator and the second interconnect. In an embodiment, the second conductor can include an inert metal or a doped semiconductor. In an embodiment, the second conductor can include a platinum, gold, or similar material. Further examples of the conductive materials that may be used for the second conductor can include, but are not limited to, metals, for example, copper, tungsten, tantalum, titanium, hafnium, zirconium, aluminum, silver, tin, lead, metal alloys, metal carbides, for example, hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, aluminum carbide, other conductive materials, or any combination thereof, and the like.

[0093] In an embodiment, the second conductor can include a metallic material. In an embodiment, the second conductor can include an inert metal. In an embodiment, the metallic material can include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the second conductor can comprise a semi-metallic material. Non-limiting examples include arsenic, antimony, bismuth, a-tin (gray tin) and graphite, and mercury telluride (HgTe). Semi- metallic materials may also be any mixtures of such materials. In various embodiments, the second conductor can comprise an intermetallic material. Non-limiting examples include gold and aluminum intermetallics, copper and tin intermetallics, tin and nickel intermetallics, tin and silver intermetallics, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the second conductor can have a thickness of approximately 1 nm to approximately 400 nm, with an example thickness of approximately 15 nm to approximately 100 nm. In an embodiment, the second conductor may be deposited by any suitable mechanism including, but not limited to, PVD, CVD, MOCVD, metal foil lamination, sputtering, metal paste deposition, combinations thereof, or the like.

[0094] In another embodiment the third insulator can include an oxide. In one embodiment the third insulator can include a dielectric. In an embodiment, the third insulator can include a silicon dioxide (SiCk), or a low-K material. In an embodiment, the third insulator can have a thickness of approximately 2 nm to approximately 10 nm, with an example thickness of approximately 3 nm to approximately 5 nm. In one embodiment, the third insulator can be deposited using PVD, CVD, MOCVD, and/or ALD, and the like.

[0095] At block 526, a third interconnect can be deposited on the second device. In an embodiment, the third interconnect can include an inert metal or a doped semiconductor. In an embodiment, the third interconnect can include a platinum, gold, or similar material. Further examples of the conductive materials that may be used for the third interconnect can include, but are not limited to, metals, for example, copper, tungsten, tantalum, titanium, hafnium, zirconium, aluminum, silver, tin, lead, metal alloys, metal carbides, for example, hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, aluminum carbide, other conductive materials, or any combination thereof, and the like.

[0096] In an embodiment, the third interconnect can include a metallic material. In an embodiment, the third interconnect can include an inert metal. In an embodiment, the metallic material can include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the third interconnect can comprise a semi-metallic material. Non-limiting examples include arsenic, antimony, bismuth, a-tin (gray tin) and graphite, and mercury telluride (HgTe). Semi-metallic materials may also be any mixtures of such materials. In various embodiments, the third interconnect can comprise an intermetallic material. Non-limiting examples include gold and aluminum intermetallics, copper and tin intermetallics, tin and nickel intermetallic s, tin and silver intermetallics, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the third interconnect can have a thickness of approximately 1 nm to approximately 400 nm, with an example thickness of approximately 15 nm to approximately 100 nm. In an embodiment, the third interconnect may be deposited by any suitable mechanism including, but not limited to, PVD, CVD, MOCVD, metal foil lamination, sputtering, metal paste deposition, combinations thereof, or the like.

[0097] FIG. 6 depicts an example of a system 600 according to one or more embodiments of the disclosure. In an embodiment, the system 600 can include the selectors described herein. In one embodiment, system 600 includes, but is not limited to, a desktop computer, a laptop computer, a netbook, a tablet, a notebook computer, a personal digital assistant (PDA), a server, a workstation, a cellular telephone, a mobile computing device, a smart phone, an Internet appliance or any other type of computing device. In some embodiments, system 600 can include a system on a chip (SOC) system.

[0098] In one embodiment, system 600 includes multiple processors including processor 610 and processor N 605, where processor N 605 has logic similar or identical to the logic of processor 610. In one embodiment, processor 610 has one or more processing cores (represented here by processing core 1 612 and processing core N 612N, where 612N represents the Nth processor core inside processor 610, where N is a positive integer). More processing cores can be present (but not depicted in the diagram of FIG. 6). In some embodiments, processing core 612 includes, but is not limited to, pre-fetch logic to fetch instructions, decode logic to decode the instructions, execution logic to execute instructions, a combination thereof, or the like. In some embodiments, processor 610 has a cache memory 616 to cache instructions and/or data for system 600. Cache memory 616 may be organized into a hierarchical structure including one or more levels of cache memory.

[0099] In some embodiments, processor 610 includes a memory controller (MC) 614, which is configured to perform functions that enable the processor 610 to access and communicate with memory 630 that includes a volatile memory 632 and/or a non-volatile memory 634. In some embodiments, processor 610 can be coupled with memory 630 and chipset 620. Processor 610 may also be coupled to a wireless antenna 678 to communicate with any device configured to transmit and/or receive wireless signals. In one embodiment, the wireless antenna antenna 678 operates in accordance with, but is not limited to, the IEEE 802.11 standard and its related family, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.

[00100] In some embodiments, volatile memory 632 includes, but is not limited to, Synchronous Dynamic Random Access Memory (SDRAM), Dynamic Random Access Memory (DRAM), RAMBUS Dynamic Random Access Memory (RDRAM), and/or any other type of random access memory device. Non-volatile memory 634 includes, but is not limited to, flash memory, phase change memory (PCM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), or any other type of non-volatile memory device.

[00101] Memory device 630 stores information and instructions to be executed by processor 610. In one embodiment, memory 630 may also store temporary variables or other intermediate information while processor 610 is executing instructions. In the illustrated embodiment, chipset 620 connects with processor 610 via Point-to-Point (PtP or P-P) interface 617 and P-P interface 622. Chipset 620 enables processor 610 to connect to other elements in system 600. In some embodiments of the disclosure, P-P interface 617 and P-P interface 622 can operate in accordance with a PtP communication protocol, such as the Intel® QuickPath Interconnect (QPI) or the like. In other embodiments, a different interconnect may be used.

[00102] In some embodiments, chipset 620 can be configured to communicate with processor 610, the processor N 605, display device 640, and other devices 672, 676, 674, 660, 662, 664, 666, 677, etc. Chipset 620 may also be coupled to the wireless antenna 678 to communicate with any device configured to transmit and/or receive wireless signals.

[00103] Chipset 620 connects to display device 640 via interface 626. Display 640 may be, for example, a liquid crystal display (LCD), a plasma display, cathode ray tube (CRT) display, or any other form of visual display device. In some embodiments of the disclosure, processor 610 and chipset 620 are integrated into a single SOC. In addition, chipset 620 connects to bus 650 and/or bus 655 that interconnect various elements 674, 660, 662, 664, and 666. Bus 650 and bus 655 may be interconnected via a bus bridge 672. In one embodiment, chipset 620 couples with a non-volatile memory 660, a mass storage device(s) 662, a keyboard/mouse 664, and a network interface 666 via interface 624 and/or 604, smart TV 676, consumer electronics 677, etc.

[00104] In one embodiment, mass storage device(s) 662 can include, but not be limited to, a solid state drive, a hard disk drive, a universal serial bus flash memory drive, or any other form of computer data storage medium. In one embodiment, network interface 666 is implemented by any type of well-known network interface standard including, but not limited to, an Ethernet interface, a universal serial bus (USB) interface, a Peripheral Component Interconnect (PCI) Express interface, a wireless interface and/or any other suitable type of interface. In one embodiment, the wireless interface operates in accordance with, but is not limited to, the IEEE 802.11 standard and its related family, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.

[00105] While the modules shown in FIG. 6 are depicted as separate blocks within the system 600, the functions performed by some of these blocks may be integrated within a single semiconductor circuit or may be implemented using two or more separate integrated circuits. For example, although cache memory 616 is depicted as a separate block within processor 610, cache memory 616 or selected elements thereof can be incorporated into processor core 612.

[00106] It is noted that the system 600 described herein may include any suitable type of microelectronics packaging and configurations thereof, including, for example, system in a package (SiP), system on a package (SOP), package on package (PoP), interposer package, 3D stacked package, etc. Further, any suitable type of microelectronic components may be provided in the semiconductor packages, as described herein. For example, microcontrollers, microprocessors, baseband processors, digital signal processors, memory dies, field gate arrays, logic gate dies, passive component dies, MEMSs, surface mount devices, application specific integrated circuits, baseband processors, amplifiers, filters, combinations thereof, or the like may be packaged in the semiconductor packages, as disclosed herein. The semiconductor devices (for example, the semiconductor devices described in connection with any of FIGS. 1-5), as disclosed herein, may be provided in any variety of electronic device including consumer, industrial, military, communications, infrastructural, and/or other electronic devices.

[00107] In various embodiments, the devices, as described herein, may be used in connection with one or more processors. The one or more processors may include, without limitation, a central processing unit (CPU), a digital signal processor(s) (DSP), a reduced instruction set computer (RISC), a complex instruction set computer (CISC), a microprocessor, a microcontroller, a field programmable gate array (FPGA), or any combination thereof. The processors may also include one or more application specific integrated circuits (ASICs) or application specific standard products (ASSPs) for handling specific data processing functions or tasks. In certain embodiments, the processors may be based on an Intel® Architecture system and the one or more processors and any chipset included in an electronic device may be from a family of Intel® processors and chipsets, such as the Intel® Atom® processor(s) family or Intel-64 processors (for example, Sandy Bridge®, Ivy Bridge®, Haswell®, Broadwell®, Skylake®, etc.)·

[00108] Additionally or alternatively, the devices, as described herein, may be used in connection with one or more additional memory chips. The memory may include one or more volatile and/or non-volatile memory devices including, but not limited to, magnetic storage devices, read-only memory (ROM), random access memory (RAM), dynamic RAM (DRAM), static RAM (SRAM), synchronous dynamic RAM (SDRAM), double data rate (DDR) SDRAM (DDR-SDRAM), RAM-BUS DRAM (RDRAM), flash memory devices, electrically erasable programmable read-only memory (EEPROM), non-volatile RAM (NVRAM), universal serial bus (USB) removable memory, or combinations thereof.

[00109] In example embodiments, the electronic device in which the disclosed devices are used and/or provided may be a computing device. Such a computing device may house one or more boards on which the devices may be disposed. The board may include a number of components including, but not limited to, a processor and/or at least one communication chip. The processor may be physically and electrically connected to the board through, for example, electrical connections of the devices. The computing device may further include a plurality of communication chips. For instance, a first communication chip may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth, and a second communication chip may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, and others. In various example embodiments, the computing device may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, combinations thereof, or the like. In further example embodiments, the computing device may be any other electronic device that processes data.

[00110] Example 1 may include a selector, comprising: a first interconnect; a first device having first current-voltage characteristics, the first device disposed on a portion of the first interconnect; a second interconnect on the first device; a first conductor on the second interconnect; a third interconnect on the first conductor; a second conductor on the first interconnect; a fourth interconnect on the second conductor; and a second device having second current-voltage characteristics, the second device on the fourth interconnect and in electrical contact with the third interconnect, wherein the first device and the second device are electrically connected in parallel.

[00111] Example 2 may include the selector of example 1 and/or some other example herein, wherein the first current-voltage characteristics and the second current-voltage characteristics are substantially asymmetric with respect to a positive voltage bias and a negative voltage bias.

[00112] Example 3 may include the selector of example 1 and/or some other example herein, wherein the selector has third current-voltage characteristics that are substantially symmetric with respect to a positive voltage bias and a negative voltage bias.

[00113] Example 4 may include the selector of example 1 and/or some other example herein, wherein at least the first device or the second device comprises an insulator metal transition (IMT) device.

[00114] Example 5 may include the selector of example 4 and/or some other example herein, wherein the IMT device comprises one or more of (1) a material including vanadium and oxygen, (2) a material including titanium and oxygen, (3) a material including lanthanum, cobalt, and oxygen, (4) a material including niobium and oxygen, or (4) a material including samarium nickel and oxygen.

[00115] Example 6 may include the selector of example 4 and/or some other example herein, wherein the IMT device comprises a first electrode, an insulator, and a second electrode.

[00116] Example 7 may include the selector of example 4 and/or some other example herein, wherein the IMT device comprises one or more of (1) a first structure comprising a copper electrode, an oxide, and an inert electrode, (2) a second structure comprising a silver electrode, an oxide, and an inert electrode, (3) a third structure comprising a copper electrode, a chalcogenide, and an inert electrode, or (4) a fourth structure comprising a silver electrode, a chalcogenide, and an inert electrode.

[00117] Example 8 may include the selector of example 4 and/or some other example herein, wherein the first device or the second device comprises a diode.

[00118] Example 9 may include the selector of example 8 and/or some other example herein, wherein the diode comprises a P-N diode or a P-I-N diode.

[00119] Example 10 may include a selector, comprising: a first device having first current- voltage characteristics, the first device electrically connected between a first interconnect layer and a second interconnect layer; a second device having second current- voltage characteristics, the second device electrically connected between the first interconnect layer and a third interconnect layer; wherein the first device and the second device are electrically connected in parallel.

[00120] Example 11 may include the selector of example 10 and/or some other example herein, wherein the first interconnect layer is a first interconnect layer N and the second interconnect layer is a second interconnect layer N-l, and the third interconnect layer is a third interconnect layer N+l.

[00121] Example 12 may include the selector of example 10 and/or some other example herein, wherein the second interconnect layer is a first interconnect layer N and the second interconnect layer is a second interconnect layer N-l, and the third interconnect layer is third interconnect layer N- 1.

[00122] Example 13 may include the selector of example 10 and/or some other example herein, wherein the first interconnect layer is a first interconnect layer N and the second interconnect layer is a second interconnect layer N+l, and the third interconnect layer is a third interconnect layer N+l.

[00123] Example 14 may include the selector of example 10 and/or some other example herein, wherein the first current-voltage characteristics and the second current-voltage characteristics are substantially asymmetric with respect to a positive voltage bias and a negative voltage bias.

[00124] Example 15 may include the selector of example 10 and/or some other example herein, wherein the selector has third current-voltage characteristics that are substantially symmetric with respect to positive voltage bias and a negative voltage bias.

[00125] Example 16 may include the selector of example 10 and/or some other example herein, wherein the first device or the second device comprises an insulator metal transition (IMT) device.

[00126] Example 17 may include the selector of example 16 and/or some other example herein, wherein the IMT device comprises one or more of (1) a material including vanadium and oxygen, (2) a material including titanium and oxygen, (3) a material including lanthanum, cobalt, and oxygen, (4) a material including niobium and oxygen, or (5) a material including samarium nickel and oxygen. [00127] Example 18 may include the selector of example 16 and/or some other example herein, wherein the IMT device comprises a first electrode, an insulator, and a second electrode.

[00128] Example 19 may include the selector of example 16 and/or some other example herein, wherein the IMT device comprises one or more of (1) a first structure comprising a copper electrode, an oxide, and an inert electrode, (2) a second structure comprising a silver electrode, an oxide, and an inert electrode, (3) a third structure comprising a copper electrode, a chalcogenide, and an inert electrode, or (4) a fourth structure comprising a silver electrode, a chalcogenide, and an inert electrode.

[00129] T Example 20 may include the selector of example 16 and/or some other example herein, wherein the first device or the second device comprises a diode.

[00130] Example 21 may include the selector of example 20 and/or some other example herein, wherein the diode comprises a P-N diode or a P-I-N diode.

[00131] Example 22 may include a electronic device comprising: a selector, comprising: a first interconnect; a first device having first current-voltage characteristics, the first device disposed on a portion of the first interconnect; a second interconnect on the first device; a first conductor on the second interconnect; a third interconnect on the first conductor; a second conductor on the first interconnect; a fourth interconnect on the second conductor; and a second device having second current- voltage characteristics, the second device on the fourth interconnect and in electrical contact with the third interconnect, wherein the first device and the second device are electrically connected in parallel.

[00132] Example 23 may include the electronic device of example 22 and/or some other example herein, wherein the first current- voltage characteristics and the second current-voltage characteristics are substantially asymmetric with respect to a positive voltage bias and a negative voltage bias.

[00133] Example 24 may include the electronic device of example 22 and/or some other example herein, wherein the selector has third current-voltage characteristics that are substantially symmetric with respect to a positive voltage bias and a negative voltage bias.

[00134] Example 25 may include the electronic device of example 22 and/or some other example herein, wherein at least the first device or the second device comprises an insulator metal transition (IMT) device.

[00135] Example 26 may include the electronic device of example 25 and/or some other example herein, wherein the IMT device comprises one or more of (1) a material including vanadium and oxygen, (2) a material including titanium and oxygen, (3) a material including lanthanum, cobalt, and oxygen, (4) a material including niobium and oxygen, or (4) a material including samarium nickel and oxygen.

[00136] Example 27 may include the electronic device of example 25 and/or some other example herein, wherein the IMT device comprises a first electrode, an insulator, and a second electrode.

[00137] Example 28 may include the electronic device of example 25 and/or some other example herein, wherein the IMT device comprises one or more of (1) a first structure comprising a copper electrode, an oxide, and an inert electrode, (2) a second structure comprising a silver electrode, an oxide, and an inert electrode, (3) a third structure comprising a copper electrode, a chalcogenide, and an inert electrode, or (4) a fourth structure comprising a silver electrode, a chalcogenide, and an inert electrode.

[00138] Example 29 may include the electronic device of example 25 and/or some other example herein, wherein the first device or the second device comprises a diode.

[00139] Example 30 may include the electronic device of example 29 and/or some other example herein, wherein the diode comprises a P-N diode or a P-I-N diode.

[00140] Example 31 may include an electronic device comprising: a selector, comprising: a first device having first current-voltage characteristics, the first device electrically connected between a first interconnect layer and a second interconnect layer; a second device having second current-voltage characteristics, the second device electrically connected between the first interconnect layer and a third interconnect layer; wherein the first device and the second device are electrically connected in parallel.

[00141] Example 32 may include the electronic device of example 31 and/or some other example herein, wherein the first interconnect layer is a first interconnect layer N and the second interconnect layer is a second interconnect layer N-l, and the third interconnect layer is a third interconnect layer N+l.

[00142] Example 33 may include the electronic device of example 31 and/or some other example herein, wherein the second interconnect layer is a first interconnect layer N and the second interconnect layer is a second interconnect layer N-l, and the third interconnect layer is third interconnect layer N-l.

[00143] Example 34 may include the electronic device of example 31 and/or some other example herein, wherein the first interconnect layer is a first interconnect layer N and the second interconnect layer is a second interconnect layer N+l, and the third interconnect layer is a third interconnect layer N+l.

[00144] Example 35 may include the electronic device of example 31 and/or some other example herein, wherein the first current- voltage characteristics and the second current-voltage characteristics are substantially asymmetric with respect to a positive voltage bias and a negative voltage bias.

[00145] Example 36 may include the electronic device of example 31 and/or some other example herein, wherein the selector has third current-voltage characteristics that are substantially symmetric with respect to positive voltage bias and a negative voltage bias.

[00146] Example 37 may include the electronic device of example 31 and/or some other example herein, wherein the first device or the second device comprises an insulator metal transition (IMT) device.

[00147] Example 38 may include the electronic device of example 37 and/or some other example herein, wherein the IMT device comprises one or more of (1) a material including vanadium and oxygen, (2) a material including titanium and oxygen, (3) a material including lanthanum, cobalt, and oxygen, (4) a material including niobium and oxygen, or (5) a material including samarium nickel and oxygen.

[00148] Example 39 may include the electronic device of example 37 and/or some other example herein, wherein the IMT device comprises a first electrode, an insulator, and a second electrode.

[00149] Example 40 may include the electronic device of example 37 and/or some other example herein, wherein the IMT device comprises one or more of (1) a first structure comprising a copper electrode, an oxide, and an inert electrode, (2) a second structure comprising a silver electrode, an oxide, and an inert electrode, (3) a third structure comprising a copper electrode, a chalcogenide, and an inert electrode, or (4) a fourth structure comprising a silver electrode, a chalcogenide, and an inert electrode.

[00150] Example 41 may include the electronic device of example 37 and/or some other example herein, wherein the first device or the second device comprises a diode.

[00151] Example 42 may include the electronic device of example 41 and/or some other example herein, wherein the diode comprises a P-N diode or a P-I-N diode.

[00152] Various features, aspects, and embodiments have been described herein. The features, aspects, and embodiments are susceptible to combination with one another as well as to variation and modification, as will be understood by those having skill in the art. The present disclosure should, therefore, be considered to encompass such combinations, variations, and modifications.

[00153] The terms and expressions which have been employed herein are used as terms of description and not of limitation, and there is no intention, in the use of such terms and expressions, of excluding any equivalents of the features shown and described (or portions thereof), and it is recognized that various modifications are possible within the scope of the claims. Other modifications, variations, and alternatives are also possible. Accordingly, the claims are intended to cover all such equivalents.

[00154] While the disclosure includes various embodiments, including at least a best mode, it is to be understood that many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the foregoing description. Accordingly, the disclosure is intended to embrace all such alternatives, modifications, and variations, which fall within the scope of the included claims. All matters disclosed herein or shown in the accompanying drawings are to be interpreted in an illustrative and non-limiting sense.

[00155] This written description uses examples to disclose certain embodiments of the disclosure, including the best mode, and also to enable any person skilled in the art to practice certain embodiments of the disclosure, including making and using any apparatus, devices or systems and the performance of any incorporated methods and processes. The patentable scope of certain embodiments of the disclosure is defined in the claims, and may include other examples that occur to those skilled in the art. Such other examples are intended to be within the scope of the claims if they have structural elements that do not differ from the literal language of the claims, or if they include equivalent structural elements with insubstantial differences from the literal language of the claims.