[0001] This relates generally to a divider and, more particularly, to a single stage latch divider.

BACKGROUND

[0002] There are numerous types of dividers that have been employed at various frequency ranges. For many very high frequency ranges (i.e., above 30 GHz), dividers in CMOS have been developed. However, many of these designs use multiple stages. When the frequency range of interest increases, though, these multi-stage divider arrangements can introduces parasitics (i.e., parasitic inductances) that can adversely affect performance. Thus, there is a need for a more compact divider that is adapted to operate at very high frequencies (i.e., 120GHz).

[0003] Some examples of conventional circuits are PCT Publ. No. WO/2009/115865; US

Publ. No. 2008/0303561; Kim et al, "A 75GHz PLL Front-End Integration in 65nm SOI CMOS Technology," 2007 IEEE Symposium on VLSI Circuits Digest of Technical Papers, pp. 174-175; Lee et al, "A 40-GHz Frequency Divider in 0.18-μιη CMOS Technology," IEEE J. of Solid State Circuits, Vol. 39, No. 4, April 2004, pp. 594-601; Kim et al, "A 20-GHz Phase-Locked Loop for 40Gb/s Serializing Transmitter in 0.13-μιη CMOS," IEEE J. of Solid State Circuits, Vol. 41, No. 4, April 2006, pp. 899-908; and The et al, "A 0.18-μιη CMOS 3.2-10 GHz Quadrature VCO of IEEE 802.15.4a UWB Transceivers," Asia Pacific Microwave Conference, 2009, December 2009, pp. 245-248.

SUMMARY

[0004] An example embodiment of the invention provides an apparatus that comprises an inductor; a plurality of sets of cross-coupled transistors, wherein each transistor from each set of cross-coupled transistors is coupled to the inductor; an input circuit that receives an input signal, that is coupled to each transistor from the sets of cross-coupled transistors, and that is coupled to the resonator, wherein the input signal has a first frequency; a control circuit that is coupled to the each transistor from at least one of the sets of cross-coupled transistors and that receives a control signal; and a plurality of output terminals, wherein each output terminal is coupled to the inductor, and wherein the output terminals provide an output signal having a second frequency, and wherein the second frequency is a fraction of the first frequency.

[0005] In an example embodiment, the inductor has a center tap, wherein the center tap receives a supply voltage.

[0006] In an example embodiment, the inductor further comprises: a first inductor that receives a supply voltage; and a second inductor that receives the supply voltage.

[0007] In an example embodiment, the each set of cross-coupled transistors further comprises: a first transistor having a first passive electrode, a second passive electrode, and a control electrode; and a second transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the first passive electrode of the first transistor is coupled to the control electrode of the second transistor, and wherein the control electrode of the first transistor is coupled to the first passive electrode of the second transistor, and wherein the second passive electrode of the first transistor is coupled to the second passive electrode of the second transistor.

[0008] In an example embodiment, the input circuit further comprises a third transistor having a first passive electrode, a second passive electrode, and a control electrode, and wherein the first passive electrode of the third transistor is coupled to the second passive electrodes of the first and second transistors from at least one of the sets of cross-coupled transistors, and wherein the control electrode of the third transistor receives at least a portion of the input signal.

[0009] In an example embodiment, the control circuit further comprises a plurality of portions, wherein each portion is coupled to at least one transistor from at least one of the sets of cross-coupled further comprises: a fourth transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the control electrode of the fourth transistor receives the control signal; and a fifth transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the control electrode of the fifth transistor receives the control signal, and wherein the first passive electrode of the fifth transistor is coupled to the first passive electrode of the fourth transistor.

[0010] In an example embodiment, an apparatus is provided. The apparatus comprises an LC resonator having: an inductor that receives a supply voltage; a first transistor having a first passive electrode, a second passive electrode, a control electrode, and a first parasitic capacitance, wherein the first passive electrode of the first transistor is coupled to the inductor; and a transistor having a first passive electrode, a second passive electrode, a control electrode, and a second parasitic capacitance, wherein the first passive electrode of the second transistor is coupled to the inductor, and wherein the second passive electrode of the first transistor is coupled to the second passive electrode of the first passive electrode, and wherein the first and second parasitic capacitances of the first and second transistors and the inductance of the inductor form an LC tank; a latch that is coupled to the control electrodes of the first and second transistors; an input circuit that receives an input signal, that is coupled to the latch, and that is coupled to the second passive electrodes of each of the first and second transistors, wherein the input signal has a first frequency; a control circuit that is coupled to the resonator and that receives a control signal; and a plurality of output terminals, wherein each output terminal is coupled to the resonator, and wherein the output terminals provide an output signal having a second frequency, and wherein the second frequency is a fraction of the first frequency.

[0011] In an example embodiment, the latch further comprises: a third transistor having a first passive electrode, a second passive electrode, and a control electrode; and a fourth transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the first passive electrode of the third transistor is coupled to the control electrode of the fourth transistor, and wherein the control electrode of the third transistor is coupled to the first passive electrode of the fourth transistor, and wherein the second passive electrode of the third transistor is coupled to the second passive electrode of the fourth transistor.

[0012] In an example embodiment, the input circuit further comprises a fifth transistor having a first passive electrode, a second passive electrode, and a control electrode, and wherein the first passive electrode of the fifth transistor is coupled to the second passive electrodes of the third and fourth transistors, and wherein the control electrode of the fifth transistor receives at least a portion of the input signal.

[0013] In an example embodiment, the control circuit further comprises a plurality of portions, wherein each portion further comprises: a sixth transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the first passive electrode of the sixth transistor is coupled to the resonator, and wherein the control electrode of the sixth transistor receives the control signal; and a seventh transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the control electrode of the seventh transistor receives the control signal, and wherein the first passive electrode of the seventh transistor is coupled to the first passive electrode of the sixth transistor.

[0014] In an example embodiment, an apparatus is provided. The apparatus comprises a input circuit having: a first NMOS transistor that receive a first portion of a differential input signal at its gate, wherein the differential input signal has a first frequency; and a second NMOS transistor that receives a second portion of the differential input signal at its gate; a latch that is coupled to the drain of the first NMOS transistor; a first output terminal that is coupled to the latch and that provides a first portion of a differential output signal, wherein the differential output signal has a second frequency, and wherein the second frequency is a fraction of the first frequency; a second output terminal that is coupled to the latch and that provides a second portion of the differential output signal; an LC resonator that is coupled to each of the first and second output terminals, wherein the LC resonator includes; an inductor that receives a supply voltage; and a plurality of MOS transistors that are coupled to the inductor and that each have a parasitic capacitance, wherein the parasitic capacitances of the plurality of MOS transistors and the inductance of the inductor form an LC tank; and a control circuit that is coupled to at least one of the plurality of MOS transistors and that receives a control signal.

[0015] In an example embodiment, the inductor further comprises: a first inductor that receives a supply voltage and that is coupled to the first output terminal; and a second inductor that receives the supply voltage and that is coupled to the second output terminal.

[0016] In an example embodiment, the latch further comprises: a third NMOS transistor that is coupled to the first output terminal at its drain, the second output terminal at its gate, and the drain of the first NMOS transistor at its source; and a fourth NMOS transistor that is coupled to the second output terminal at its drain, the first output terminal at its gate, and the drain of the first NMOS transistor at its source.

[0017] In an example embodiment, plurality of MOS transistors further comprises: a fifth

NMOS transistor that is coupled to the first output terminal at its drain, the second output terminal at its gate, the drain of the second NMOS transistor at its source, and the second output terminal at its gate; a sixth NMOS transistor that is coupled to the second output terminal at its drain, the first output terminal at its gate, and the drain of the second NMOS transistor at its source, and the first output terminal at its gate; a seventh NMOS transistor that is coupled to the first output terminal at its drain, the second output terminal at its gate, and the drain of the second NMOS transistor at its source; and an eighth NMOS transistor that is coupled to the second output terminal at its drain, the first output terminal at its gate, and the drain of the second NMOS transistor at its source.

[0018] In an example embodiment, the control circuit further comprises a first portion and a second portion, and wherein the first portion of the control circuit includes: a PMOS transistor that is coupled to the second output terminal at its source, the gate of the seventh NMOS transistor at its drain, and that receives the control signal at its gate and the supply voltage at its body; and a ninth NMOS transistor that is coupled to the gate of the seventh NMOS transistor at its drain and that receives the control signal at its gate.

[0019] In an example embodiment, the PMOS transistor further comprises a first PMOS transistor, and wherein the second portion of the control circuit further comprises: a second PMOS transistor that is coupled to the first output terminal at its source, the gate of the eighth NMOS transistor at its drain, and that receives the control signal at its gate and the supply voltage at its body; and a tenth NMOS transistor that is coupled to the gate of the eighth NMOS transistor at its drain and that receives the control signal at its gate.

[0020] In an example embodiment, the first frequency is about 120GHz.

BRIEF DESCRIPTION OF THE DRAWINGS

[0021] FIG. 1 illustrates a latch divider in accordance with an example embodiment of the principles of the invention; and

[0022] FIG. 2 depicts the performance of the latch divider of FIG. 1.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

[0023] In FIG. 1, the reference numeral 100 generally designates a latch divider in accordance with an example embodiment. The divider 100 generally comprises an LC resonator 102, an input circuit 104, and a control circuit 108. The resonator 102 generally comprises inductors LI and L2 that are coupled to output terminals (which provide output signals OUTP and OUTM) and that receive an supply voltage VDD; alternatively, inductors LI and L2 can be replaced with a single inductor having a center tap that receives the supply voltage VDD. The resonator 102 and latch 104 each includes a pair of cross-coupled transistors Q1/Q2 and Q11/Q12, respectively (which can, for example be NMOS transistors). The input circuit 108 generally comprises transistors Q5 and Q6 (which can, for example, be NMOS transistors) that are each coupled to one of the latch 104 and resonator 102. The control circuit 110 generally includes two portions that respectively include transistors Q7 and Q7 and transistors Q9 and Q10. Transistors Q5, Q6, Q8, and Q10 can also, for example, be NMOS transistors, while transistors Q7 and Q9 can, for example, be PMOS transistors.

[0024] In operation, a differential input signal INP and INM (which can, for example, have a frequency of about 120GHz) can be divided by divider 100 to a differential output signal OUTP and OUTM so as to have a frequency that is a fraction of the frequency of the differential input signal (i.e., one-half). Typically, the LC resonator 102 uses the parasitic capacitances from the gates of transistors Ql and Q2 and the inductances of inductors LI and L2 as an LC tank. Additionally, to tune the LC tank so as to extend the division frequency range, the control signal CNTL can be asserted to turn on transistors Q3 and Q4 (which also have parasitic capacitances that are substantially in parallel to parasitic capacitances of transistors Q3 and Q4). This LC tank operates in conjunction with latch 104 like a voltage controlled oscillator. The gates (or control electrodes) of transistors Q9 and Q10 receive the differential input signal INP and INM so that input circuit 102 can operate as a transconductance circuit, and the corresponding output signals from this transconductance circuit assist in controlling the latch 104 and resonator 102.

[0025] FIG. 2 depicts the operation of the divider 100. As shown, a differential input signal INP and INM (which is sinusoidal and which has a frequency of about 120GHz) is provided. The differential output signal OUTP and OUTM (which is substantially sinusoidal) has a period TOUT which is approximately double the period for the input signal INP and INM, indicating that the division ratio for divider 100 is about one -half.

[0026] Those skilled in the art to which the invention relates will appreciate that modifications may be made to the described example implementations, and that many other embodiments are possible, within the scope of the claimed invention.