LAYOUT AND TREATMENT METHOD THEREFOR, STORAGE MEDIUM AND PROGRAM PRODUCT

WIPO Patent Application WO/2023/097908

A1

The present application relates to the technical field of semiconductors. Provided are a layout and a treatment method therefor, a storage medium and a program product. The present application is to improve the integration level of a layout of a semiconductor device, and is used for solving the technical problem of the integration level of a semiconductor device being low. The layout has a first storage area and a second storage area, and the layout comprises a substrate array pattern and a storage pattern, wherein the substrate array pattern comprises a plurality of plug patterns which are arranged at intervals; and the storage pattern comprises a magnetic tunnel junction pattern located in the first storage area, and a capacitor pattern located in the second storage area, the magnetic tunnel junction pattern partially overlapping with the plug pattern located in the first storage area, and the capacitor pattern partially overlapping with the plug pattern located in the second storage area. When the layout is used for production, a magnetic random access memory can be prepared by using a preparation process for a dynamic random access memory, such that the storage density of the magnetic random access memory is increased, thereby improving the integration level of a semiconductor device.

WANG XIAOGUANG (CN)
LI HUIHUI (CN)
CHANG WEI (CN)
CAO KANYU (CN)

PCT/CN2022/078088

June 08, 2023

February 25, 2022

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CHANGXIN MEMORY TECH INC (CN)
BEIJING SUPERSTRING ACADEMY OF MEMORY TECH (CN)

H01L27/02

US10008539B2	2018-06-26
CN111653563A	2020-09-11
CN102569248A	2012-07-11
CN109841595A	2019-06-04

LEADER PATENT & TRADEMARK FIRM (CN)

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