BACKGROUND

The present disclosure, in some embodiments thereof, relates to a digital module in an integrated circuit (IC), more specifically, but not exclusively, to circuitry to propagate a data input at a low voltage region to a next state output located in a high voltage region with minimum delay overhead.

In chip design, it is sometimes required to pass signals from a low voltage region to a higher voltage region. A level shifting circuit may be used to enable signals to pass from the low voltage region to the higher voltage region. Adding a level shifting cell may add to the power consumption, added area on an integrated circuit (IC) and may also add to the delay of a signal path of the integrated circuit. If the delay of a signal path is critical, then reducing the delay becomes a primary task of the IC design team.

SUMMARY

It is an object of the present invention to provide an apparatus and a method for a digital module in an integrated circuit (IC) to propagate a data input at a low voltage region of the digital module to a next state output located in a high voltage region the digital module with minimum delay overhead.

An integrated circuit including a module with a low voltage circuit and a high voltage circuit. The low voltage circuit includes a flip-flop, a multiplexor (mx) including multiple inputs, a flip flop data input (D), a flip flop scan enable (SE) input and a flip flop scan in (SI) input. The low voltage circuit further includes a transmission gate or pass gate having a gate input electronically connected to the output of the multiplexor (mx) and a gate output node (n1). A clocking circuit adapted to receive a common clock signal and having an output terminal (ck) and an inverse of the output terminal (ckb). The plurality of inputs electronically connected to the output clock terminal (ck) and another of at least one input is electronically connected to the inverse output terminal (ckb). The high voltage circuit includes a level shifting circuit that further including a clock shift input electronically connected to the inverse output terminal (ckb). A level input electronically connected to the gate output node (n1) and a second level input node (n2). A second level input electronically connected to the output clock terminal (ck) and a next stage output (Q). An input stage electronically connected to the gate output node (n1) and a second input electronically connected to the second level input node (n2). . The operation of the level shifting circuit and its connection to the output stage circuit, propagates a datum from the data (D) input to the next stage output (Q). The flip flop may be a D-type flip flop. By virtue of the flip flop and the level shifting circuit electronically connected to both the inverse output terminal (ckb) and the output terminal (ck), to enable parallel connection and operation of the flip flop and the level shifting circuit at substantially the same time.

The clocking circuit comprises a first input to a NAND gate connected to the common clock signal. An odd number of serially connected inverter gates connected between the common clock signal and a second input of the NAND gate. An inverter with an input connected to the output of the NAND gate. The output of the inverter provides the output clock terminal (ck) and the input provides the inverse output terminal (ckb).

The level shifting circuit comprises a NAND gate with a first input connected to the inverse output terminal (ckb) and a second input connected to the gate output node (n1). An inverter with an input connected to the gate output node (n1). A NOR gate with a first input connected to the output (fb) of the invertor and a second input connected to the output clock terminal (ck). An inverting gate input of a first switch connected to the output of the NOR gate. The switch portion of the first switch operatively connects between a supply voltage (VDDH) and the input power supply to the NAND gate. A second inverting gate input of a second switch connected to the output of the NAND gate (n3). The switch portion of the second switch operatively connects between the supply voltage (VDDH) and the input power supply to the NOR gate.

The output stage circuit comprises the gate output node (n1) commonly connected to an inverting gate of a first switch and a non-inverting gate of a second switch. An inverting gate of a third switch connected to the second level input node (n2). The respective third switch portions of the third switch, the second switch and the first switch connect in series between the supply voltage (VDDH) and a ground. An output (Q) of the output stage is provided from the point where the second switch portion connects to the first switch portion.

The multiplexor comprises a first transmission gate with a first input connected to the flip flop scan in (SI) input. The output of the first transmission gate is the flip flop SI input ANDED with the output clock terminal (ck) to provide the first gate output function at a terminal F1, where F1=SI.ck. A second transmission gate with an input connected to an output of a non-inverting gate. A third transmission gate with an input connected to the gate output node (n1) and the input of the non-inverting gate. The output of the first transmission gate connects to node nl and the output of the second transmission gate connects to a terminal F2. The terminal F2 connects in a series switch path between the switch path portion of an output of the flip flop and a second switch path portion of a second output of the flip-flop. The series switch path is between a supply voltage (VDDL) and a ground.

The switch path portion of the output includes a first switch and a second switch. The switch path portion of the second output includes a third switch and a fourth switch. A first inverting gate input of the first switch connects to the terminal F1 and the non-inverting gate terminal of the fourth switch. A second inverting gate input of the second switch is connected to a non-inverting gate of a fifth switch and the output of a second inverter gate (seb). The input of the second inverter gate is connected to the flip flop scan enable (SE) input and an inverting gate input of an eight switch. Data input (D) connects to an inverting gate input of a seventh switch and a non-inverting gate input of a sixth switch. The switch path portion includes the switch portion of the first and second switched connected between the supply voltage (VDDL) and the terminal F2. The second switch path portion includes the switch portions of the third and fourth switches connected between the terminal F2 and the ground. The switch path portions of the seventh and eight switches are connected in series and to the terminal F2. The switch path portions of the fifth and sixth switches are connected in series between the terminal F2 and the ground.

A method for a digital module included in an integrated circuit (IC). The digital module includes a low voltage region that includes a latch circuit with a data (D) input and a high voltage region. The high voltage region includes a level shifting circuit and an output stage. The method upon receiving a clock output (CP), generates a clock pulse (ck) to enable a high voltage rise path of the output stage. Enabling the high voltage path allows a propagation of a datum on the data (D) input to a next state output (Q) of the output stage. Upon the data (D) input rising, the latch circuit is operated until an ending of the clock pulse (ck). The latch is operated in parallel with the operation of the level shifting circuit at substantially the same time responsive to the clock pulse (ck). Responsive to the clock pulse (ck) ending, the high-rise voltage path of the output stage is disabled if Q=0 and remains enabled if Q=1. A benefit of the digital module is by virtue of a connection of a level shifting circuit located in a high voltage region of the digital module to a latch. The latch being included in a low voltage region of the digital module. A further benefit by modifying the level shifting circuit and by utilizing other functional features and connections provided by the level shifting circuit. Where the other functional features and connections may not be obvious if the level shifting circuit is located serially between the low voltage and the higher voltage region, which may add to a delay of a critical signal path of the integrated circuit (IC).

The foregoing and other objects are achieved by the features of the independent claims. Further implementation forms are apparent from the dependent claims, the description and the figures.

Unless otherwise defined, all technical and/or scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the disclosure pertains. Although methods and materials similar or equivalent to those described herein can be used in the practice or testing of embodiments of the disclosure, exemplary methods and/or materials are described below. In case of conflict, the patent specification, including definitions, will control. In addition, the materials, methods, and examples are illustrative only and are not intended to be necessarily limiting.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

Some embodiments of the disclosure are herein described, by way of example only, with reference to the accompanying drawings. With specific reference now to the drawings in detail, it is stressed that the particulars shown are by way of example and for purposes of illustrative discussion of embodiments of the disclosure. In this regard, the description taken with the drawings makes apparent to those skilled in the art how embodiments of the disclosure may be practiced.

In the drawings:

FIG. 1 shows a block diagram of a layout of an implementation of multiple digital modules, in accordance with some embodiments;

FIG. 2 shows a block diagram of further details of an implementation of a digital module, in accordance with some embodiments; FIG. 3 shows further circuit details of multiplexor-pass gate circuit (MPGC) and an output stage circuit, in accordance with some embodiments;

FIG. 4 shows further circuit details of a clocking circuit and a level shifter circuit (LSC), in accordance with some embodiments;

FIG. 5 shows a timing diagram of operation a digital module, in accordance with some embodiments; and

FIG. 6 shows a flowchart of a method, in accordance with some embodiments.

DETAILED DESCRIPTION

The present disclosure, in some embodiments thereof, relates to a digital module in an integrated circuit (IC), more specifically, but not exclusively, to circuitry to propagate a data input at a low voltage region to a next state output located in a high voltage region with minimum delay overhead.

By way of introduction, in digital integrated circuits (ICs) level shifting circuits are added to enable passing of signals from a low voltage region to a higher voltage region of the IC. Adding a level shifting circuit may add to power consumption, added circuit area of an integrated circuit (IC) and may add to a delay of a signal path of the integrated circuit. Adding to the delay may be because the level shifting circuit is located between the low voltage and the higher voltage region of the IC. If the delay of a signal path is critical, then reducing the delay becomes a primary task of the IC design team to minimize the delay. A benefit described in detail below is by connecting differently and modifying the level shifting circuit by utilizing other functional features and connections thereto that are provided by the level shifting circuit. The other functional features and connections thereto may not be obvious if the level shifting circuit is located between the low voltage and the higher voltage region of the IC.

Before explaining at least one embodiment of the disclosure in detail, it is to be understood that the disclosure is not necessarily limited in its application to the details of construction and the arrangement of the components and/or methods set forth in the following description and/or illustrated in the drawings and/or the Examples. The disclosure is capable of other embodiments or of being practiced or carried out in various ways. Aspects of the present disclosure are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the disclosure. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer readable program instructions.

The flowchart and block diagrams in the Figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts or carry out combinations of special purpose hardware and computer instructions.

Reference is now made to FIG. 1, which shows a block diagram of a layout of an implementation of multiple digital modules 20, in accordance with some embodiments. Multiple digital modules 20 may be included along with other modules (not shown) in an integrated circuit 10 layout. Low voltage region 1, includes a data (D) input to a flop circuit 11. The output of flop circuit 11 connects to the input of a logic circuit 12. The output of logic gate 12 connects to the input of level shift circuit 24 that is included in high voltage region 2. The Q output of level shift circuit 24 is provided in high voltage region 2 by an output stage (not shown). Digital module 20 therefore, provides a path for a propagation of the data (D) signal from low voltage region 1 to high voltage region 2.

Reference is now made to FIG. 2, which shows a block diagram of further details of an implementation of a digital module 20, in accordance with some embodiments. Digital module 20 is shown with three inputs into multiplexor-pass gate circuit (MPGC) 21. The three inputs are a data input (D), scan input (SI) and scan enable (SE). Input to clocking circuit 22 is the normal clock (CP). Two outputs from clocking circuit 22 are clock output (ck) and the logic inverse of clock output (ck) labelled as clock output (ckb). Clock outputs ck and ckb connect to level shifter circuit (LSC) 24 and to multiplexor-pass gate circuit (MPGC) 21. An output of multiplexor-pass gate circuit (MPGC) 21 connects at a node nl and to an input of output stage 26. Output stage 26 has a Q output. Node nl connects to another input of level shifter circuit (LSC) 24. An output of level shifter circuit (LSC) 24 connects to a node 2 of output stage 26. Multiplexor-pass gate circuit (MPGC) 21 and scan circuitry (not shown) are located and connected in low voltage region 1. Output stage 26 and level shifter circuit (LSC) 24 are located and connected in high voltage region 2. Level shifter circuit (LSC) 24 by virtue of its connection to nodes nl, ckb and n2 is operated by ckb, hence no additional delay is included on the data (D) input to data output Q path of digital module 20.

Reference is now made to FIG. 3, which shows further circuit details of multiplexorpass gate circuit (MPGC) 21 and output stage 26, in accordance with some embodiments. Scan input SI connects to the input of a transmission gate or pass gate pgl, output of pass gate pgl is node FL In operation, pass gate pgl is clocked by clock output ck and the inverse of clock output ck (ckb). Pass gate pgl prevents SI propagation into the flop (switches s4-sl 1) and being sampled when ck is high, needlessly extending the minimum delay requirement of the SI input. F1 is maintained at previous value (just prior to ck rise) by its capacitance for the short duration of ck pulse.

Two outputs from clocking circuit 22 are clock output (ck) and the logic inverse or compliment of clock output (ck) labelled as clock output (ckb) are applied to pass gate pgl. When ck logic is logic level 1, the value of scan input SI (logic 1 or logic 0) passes through pass gate pgl. When ck is logic is logic level 0, the path between the input and the of pass gate pgl is closed circuit and the value of scan input SI (logic 1 or logic 0) passes through pass gate pgl. Use of pass gates in general by nature of their circuit structure are able to pass strong logic zeros (0) and strong logic ones (1). Switches mentioned above and in the description that follows may be a field effect transistor, bipolar transistor or any controlled switch known in the art.

Output F1 connects to the inverting gate and non-inverting gates of switches s6 and si 1 respectively. Switch s6 is connected in series with switch s7 between low voltage supply VDLL and node F2. Switch slO is connected in series with switch sl l between node F2 and ground. Low voltage supply VDLL also connects directly to node F2. Scan enable (SE) input connects to the inverting gate of switch s4 and the non-inverting gate of switch slO. Scan enable (SE) input further connects to the input of inverter gate 31, the output of inverter gate 31 connects to the non-inverting gate of switch s9 and the inverting gate input of switch s7. Data D input connects the inverting gate of switch s5 and the non-inverting gate of switch s8. Switch s8 is connected in series with switch s9 between node F2 and ground. Switch slO is connected in series with switch si 1 between node F2 and ground.

Output stage 26 includes switches si, s2 and s3 wired in series. The connection between switches s2 and s3 is the Q output of output stage 26 and high voltage region 2. The inverting gate of switch s2 connects to the input of non-inverting gate 32, node nl and the non-inverting gate of switch s3. Output node n2 in level shifter circuit (LSC) 24 (not shown) connects to the inverting gate of switch si. The output of non-inverting gate 32 connects to the input of pass gate pg2 which feeds back (sustains) nl. The output of pass gate pg2 is connected to node nl. The output of pass gate pg3 connects to node F2. Pass gates pg2 and pg3 forms a multiplexor function of multiplexor-pass gate circuit (MPGC) 21, in Boolean algebra terms: n1 = A + B where

B = F2. ck

Operation of switches si, s2 and s3 allows the application of high voltage supply VDDH or substantially zero volts to appear on the Q output.

Reference is now made to FIG. 4, which shows further circuit details of clocking circuit 22 and a level shifter circuit (LSC) 24, in accordance with some embodiments. Clocking circuit 22 includes a two input NAND gate 42, where one input connects to clock pulse ck and another input which connect a serially connected string of inverting gates 41. The number of inverting gates 41 in the serially connected string is shown as three or may be any odd number beginning with just one inverter gate 41. The output of NAND gate 42 to give clock output ckb, connects to the input of inverter gate 43 and to an input of NAND gate 44 located in level shifter circuit (LSC) 24. The other input of NAND gate 44 connects to node nl in output stage 26(not shown) and to the input of inverter gate 46. The output of inverter gate 46 (fb) gives clock output ck to one input of a NOR gate 45. The other input of NOR gate 45 connects to node nl . The output of NAND gate 44 connects to the inverted input of switch s 13 at node n3. The output of NOR gate 45 connects to the inverted input of switch sl2 at node n2. Switches sl2 and sl3 when turned ON apply high voltage supply VDDH to the supply connection of N AND gate 44 and NOR gate 45 respectively. In sum, by virtue of flop circuit 11 and level shifting circuit 24 electronically connected in parallel to both the inverse output terminal (ckb) and the output terminal (ck), enables a parallel operation of flop circuit 11 and the level shifting circuit 24 at substantially the same time.

Reference is now made to figures FIG. 5 and Fig.6 that respectively show a timing diagram of the operation for digital module 20 and a flowchart of a method 600, in accordance with some embodiments. An upper graph 50 and a lower graph 52 of signal level versus time is shown. Input to clocking circuit 22 is clock CP. Two outputs from clocking circuit 22 are clock output ck and the logic inverse of clock output ck; clock output ckb. In upper graph 50 clock input CP is shown in solid line and clock pulse ck is shown by dashed line (short dash followed by long dash). In lower graph 52 are three traces of nodes nl and n2, both shown by solid line. The third trace is of data D input shown by dashed line. The Q output is not shown but is the inverse of node nl but delayed. At decision step 601, following a clock input CP rise (shown in upper graph 50 as arrow 51), clock pulse ck is generated at step 603 (shown by dashed line in upper graph 50).

The rise of clock pulse ck will pull node n2 down and enable the high voltage rise path of output stage 26 at step 605. The high voltage rise path of output stage 26 occurs after two inversions of clocking circuit 22. The latch (switches s4-sl 1) included in multiplexor-pass gate circuit (MPGC) 21 operates at the same time as output stage 26 in step 605. Therefore, the operation of MPGC 21 is in parallel with the operation of level shifting circuit 24 at substantially the same time responsive to the clock pulse (ck) and its inverse; clock output ckb by virtue of their parallel connections to both MPGC21 and LSC 24.

At the time of the high voltage rise path of output stage 26, if data D input changes by rising at decision step 611, node nl will fall and Q will rise or is asserted with almost no extra delay, at step 617. Data D input that arrives sooner is not critical hence, there is no need to worry about its propagation delay. If data D input does not change by rising at decision step 611, Q is de-asserted at step 613. Therefore, when at decision step 607 clock pulse ck is “on” forms a loop. The loop includes asserting Q if data D rises at decision step 611, and if not, Q is de-asserted at step 613. Either of steps 613 or 617 maintains the loop at decision step 607 when clock pulse ck is “on”. If clock pulse ck is not “on”, decision step 609 is initiated, in other words, clock pulse ck has ended. At decision step 609, the high voltage path of output stage 26 is disabled (step 615) only at the end of clock pulse ck at which time data D input was sampled low (node nl is high) and Q is zero. If Q is one, or output stage 26 is disabled (step 615), a return to decision step 601 continues. However, if data D and Q are asserted at the time of step 607, then high voltage path of output stage 26 stays ON, until the end of the next ck clock pulse.

In sum, node n2 falls after each clock pulse ck rise. Node n2 rises at the end of the ck pulse if data D input was low. Node n2 remains low if data D input was sampled high. Node n2 being pulled down by the clock pulse ck and not by the data D input, allows the data D input a faster path that avoids the level shifter circuit 24 delay overhead. Node n2 serves to prevent leakage of the high voltage region 2 when data D input and next stage output Q are zero. When data D input and next stage output Q are zero, node nl is a 1, but is a weak 1 that requires the functionality and leakage protection level of level shifter circuit 24.

In other words, the reason for a propagation delay of level shifter circuit 24 not significantly affecting the propagation from the data D input of the low voltage region 1 to the next stage output Q of the high voltage region 2, is that the data D input arrives after the clock pulse ck. The level shifter circuit 24 does take some time but this time taken is less than a time of a flop. However, the level shift of the level shifter circuit 24 takes place before the data D input arrival. Control of the data D input entering the latch (switches s4-sl 1) is by the timing of the clock ck with respect to the clock CP input. If the data D input is early, it does not matter because the clock pulse ck has already switched the high enabling level input node n2 of output stage 26.

Other systems, methods, features, and advantages of the present disclosure will be or become apparent to one with skill in the art upon examination of the following drawings and detailed description. It is intended that all such additional systems, methods, features, and advantages be included within this description, be within the scope of the present disclosure, and be protected by the accompanying claims.

The descriptions of the various embodiments of the present disclosure have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

As used herein the term “about” refers to ± 10 %.

The terms "comprises", "comprising", "includes", "including", “having” and their conjugates mean "including but not limited to". This term encompasses the terms "consisting of' and "consisting essentially of'.

The phrase "consisting essentially of means that the composition or method may include additional ingredients and/or steps, but only if the additional ingredients and/or steps do not materially alter the basic and novel characteristics of the claimed composition or method.

As used herein, the singular form "a", "an" and "the" include plural references unless the context clearly dictates otherwise. For example, the term "a compound" or "at least one compound" may include a plurality of compounds, including mixtures thereof.

The word “exemplary” is used herein to mean “serving as an example, instance or illustration”. Any embodiment described as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments and/or to exclude the incorporation of features from other embodiments.

The word “optionally” is used herein to mean “is provided in some embodiments and not provided in other embodiments”. Any particular embodiment of the disclosure may include a plurality of “optional” features unless such features conflict.

Throughout this application, various embodiments of this disclosure may be presented in a range format. It should be understood that the description in range format is merely for convenience and brevity and should not be construed as an inflexible limitation on the scope of the disclosure. Accordingly, the description of a range should be considered to have specifically disclosed all the possible subranges as well as individual numerical values within that range. For example, description of a range such as from 1 to 6 should be considered to have specifically disclosed subranges such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6 etc., as well as individual numbers within that range, for example, 1, 2, 3, 4, 5, and 6. This applies regardless of the breadth of the range. Whenever a numerical range is indicated herein, it is meant to include any cited numeral (fractional or integral) within the indicated range. The phrases “ranging/ranges between” a first indicate number and a second indicate number and “ranging/ranges from” a first indicate number “to” a second indicate number are used herein interchangeably and are meant to include the first and second indicated numbers and all the fractional and integral numerals therebetween.

It is appreciated that certain features of the disclosure, which are, for clarity, described in the context of separate embodiments, may also be provided in combination in a single embodiment. Conversely, various features of the disclosure, which are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable subcombination or as suitable in any other described embodiment of the disclosure. Certain features described in the context of various embodiments are not to be considered essential features of those embodiments, unless the embodiment is inoperative without those elements.

It is the intent of the applicant(s) that all publications, patents and patent applications referred to in this specification are to be incorporated in their entirety by reference into the specification, as if each individual publication, patent or patent application was specifically and individually noted when referenced that it is to be incorporated herein by reference. In addition, citation or identification of any reference in this application shall not be construed as an admission that such reference is available as prior art to the present invention. To the extent that section headings are used, they should not be construed as necessarily limiting. In addition, any priority document(s) of this application is/are hereby incorporated herein by reference in its/their entirety.