Title:
LIMITER CIRCUIT, AND POWER AMPLIFICATION CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2023/153526
Kind Code:
A1
Abstract:
The present invention achieves a limiter circuit and a power amplification circuit with which it is possible for an output power of an amplifying transistor to be effectively limited in accordance with an amplitude of an input signal. A limiter circuit (3) is capable of being connected to an amplifying transistor (Tr1) for amplifying and outputting a high frequency signal, and controls a voltage applied to the amplifying transistor (Tr1) on the basis of the high frequency signal. The limiter circuit comprises: an input signal detecting transistor (Tr2) for detecting the power of the high frequency signal; and a voltage limiting transistor (Tr3) for limiting the voltage applied to the amplifying transistor (Tr1) on the basis of a current (Isense) flowing to the input signal detecting transistor (Tr2).
Inventors:
TAKAHASHI YOSHIFUMI (JP)
Application Number:
PCT/JP2023/005045
Publication Date:
August 17, 2023
Filing Date:
February 14, 2023
Export Citation:
Assignee:
MURATA MANUFACTURING CO (JP)
International Classes:
H03G11/04; H03F1/02; H03F3/24
Foreign References:
| JP2015507898A | 2015-03-12 | |||
| JPS62274906A | 1987-11-28 |
Attorney, Agent or Firm:
SAKAI INTERNATIONAL PATENT OFFICE (JP)
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