LIMITER CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT THEREOF

Title:

LIMITER CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT THEREOF

Document Type and Number:

WIPO Patent Application WO/2004/112142

Kind Code:

A1

Abstract:

A rectangular parallelepiped protrusion part (21) having a height H_B and a width W_B is formed on a silicon substrate, and a gate oxide film is formed on portions of the top and side wall surfaces of the protrusion part (21). A source and a drain are formed on the two opposite sides of a gate electrode (26), thereby forming a MOS transistor. A differential amplifier circuit comprising MOS transistors (61,62) is used to configure a limiter circuit. In this way, the limiter circuit can exhibit a greater gain.

Inventors:

OHMI TADAHIRO (JP)
NISHIMUTA TAKEFUMI (JP)
MIYAGI HIROSHI (JP)
SUGAWA SHIGETOSHI (JP)
TERAMOTO AKINOBU (JP)

Application Number:

PCT/JP2004/008219

Publication Date:

December 23, 2004

Filing Date:

June 11, 2004

Export Citation:

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Assignee:

TOYOTA JIDOSHOKKI KK (JP)
NIIGATA SEIMITSU CO LTD (JP)
OHMI TADAHIRO (JP)
NISHIMUTA TAKEFUMI (JP)
MIYAGI HIROSHI (JP)
SUGAWA SHIGETOSHI (JP)
TERAMOTO AKINOBU (JP)

International Classes:

H01L21/316; H01L21/336; H01L21/8238; H01L27/092; H01L29/78; H03G7/00; H03G11/00; H03K5/08; (IPC1-7): H01L27/092; H03G11/00; H03K5/00; H01L29/78; H01L21/336

Foreign References:

JP2002118255A	2002-04-19
JP2002261097A	2002-09-13
JPH06303065A	1994-10-28

Attorney, Agent or Firm:

Osuga, Yoshiyuki (Nibancho Bldg. 8-20, Nibancho, Chiyoda-k, Tokyo 84, JP)

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