Title:
LOGIC ANALYZER CIRCUIT, INTEGRATED CIRCUIT, AND INTEGRATED CIRCUIT SYSTEM
Document Type and Number:
WIPO Patent Application WO/2023/224024
Kind Code:
A1
Abstract:
This logic analyzer circuit comprises: a trace capture circuit that acquires N signals to be observed when a change occurs in at least one of the N signals from a circuit to be observed; and a buffer that stores signal data acquired by the trace capture circuit. The signal data has a timestamp of an M bit width indicating the time of acquisition, and state change data of N bit widths corresponding to respective values of the N signals to be observed. The signal data is binary-format data of an (M+N)-bit fixed length.
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| WO/1996/026451 | BIT ERROR MEASURING INSTRUMENT |
Inventors:
MASUDA SHU (JP)
MORI ATSUHIRO (JP)
MORI ATSUHIRO (JP)
Application Number:
PCT/JP2023/018224
Publication Date:
November 23, 2023
Filing Date:
May 16, 2023
Export Citation:
Assignee:
MITSUBISHI ELECTRIC CORP (JP)
International Classes:
G01R31/3177; G01R31/28; G01R31/3187; H03M7/30; H03M7/40; H03M7/46
Domestic Patent References:
| WO2008020513A1 | 2008-02-21 |
Foreign References:
| US20170045582A1 | 2017-02-16 | |||
| JP2006090727A | 2006-04-06 | |||
| US7009533B1 | 2006-03-07 | |||
| JPH07128372A | 1995-05-19 | |||
| JPH07244078A | 1995-09-19 | |||
| JP2020529064A | 2020-10-01 | |||
| JPS63111550A | 1988-05-16 |
Attorney, Agent or Firm:
FUKAMI PATENT OFFICE, P.C. (JP)
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