Title:
LOW-LATENCY SEGMENTED QUASI-CYCLIC LOW-DENSITY PARITY-CHECK (QC-LDPC) DECODER
Document Type and Number:
WIPO Patent Application WO/2023/272768
Kind Code:
A1
Abstract:
Systems and methods which provide parallel processing of multiple message bundles for a codeword undergoing a decoding process are described. Embodiments provide low-latency segmented quasi-cyclic low-density parity-check (QC-LDPC) decoder configurations in which decoding process tasks are allocated to different segments of the low-latency segmented QC-LDPC decoder for processing multiple bundles of messages in parallel. A segmented shifter of a low-latency segmented QC-LDPC decoder implementation may be configured to process multiple bundles of a plurality of edge paths in parallel. Multiple bundles of messages of a same check node cluster (CNC) are processed in parallel. Additionally, multiple bundles of messages of a plurality of CNCs are processed in parallel.
Inventors:
LAM HING-MO (CN)
CHAN HIN-TAT (CN)
TSUI YING-LUN (CN)
ZHANG ZHONGHUI (CN)
KWAN MAN-WAI (CN)
TSANG KONG-CHAU (CN)
CHAN HIN-TAT (CN)
TSUI YING-LUN (CN)
ZHANG ZHONGHUI (CN)
KWAN MAN-WAI (CN)
TSANG KONG-CHAU (CN)
Application Number:
PCT/CN2021/104984
Publication Date:
January 05, 2023
Filing Date:
July 07, 2021
Export Citation:
Assignee:
HONG KONG APPLIED SCIENCE & TECH RESEARCH INST CO LTD (CN)
International Classes:
H03M13/11
Foreign References:
| CN105680877A | 2016-06-15 | |||
| CN110710111A | 2020-01-17 | |||
| CN106452455A | 2017-02-22 | |||
| US20140181624A1 | 2014-06-26 |
Other References:
MEDIATEK INC.: "Implementation considerations on flexible and efficient LDPC decoders", 3GPP DRAFT; R1-1609337_IMPLEMENTATION CONSIDERATIONS ON FLEXIBLE AND EFFICIENT LDPC DECODERS, 3RD GENERATION PARTNERSHIP PROJECT (3GPP), MOBILE COMPETENCE CENTRE ; 650, ROUTE DES LUCIOLES ; F-06921 SOPHIA-ANTIPOLIS CEDEX ; FRANCE, vol. RAN WG1, no. Lisbon, Portugal; 20161010 - 20161014, 9 October 2016 (2016-10-09), Mobile Competence Centre ; 650, route des Lucioles ; F-06921 Sophia-Antipolis Cedex ; France , XP051149380
ZTE, ZTE MICROELECTRONICS: "Complexity, throughput and latency considerations on LDPC codes for eMBB", 3GPP DRAFT; R1-1701599 COMPLEXITY, THROUGHPUT AND LATENCY CONSIDERATIONS ON LDPC CODES FOR EMBB_FINAL, 3RD GENERATION PARTNERSHIP PROJECT (3GPP), MOBILE COMPETENCE CENTRE ; 650, ROUTE DES LUCIOLES ; F-06921 SOPHIA-ANTIPOLIS CEDEX ; FRANCE, vol. RAN WG1, no. Athens, Greece; 20170213 - 20170217, 12 February 2017 (2017-02-12), Mobile Competence Centre ; 650, route des Lucioles ; F-06921 Sophia-Antipolis Cedex ; France , XP051208766
GUOHUI WANG ; MICHAEL WU ; YANG SUN ; JOSEPH R. CAVALLARO: "A massively parallel implementation of QC-LDPC decoder on GPU", APPLICATION SPECIFIC PROCESSORS (SASP), 2011 IEEE 9TH SYMPOSIUM ON, IEEE, 5 June 2011 (2011-06-05), pages 82 - 85, XP031956458, ISBN: 978-1-4577-1212-8, DOI: 10.1109/SASP.2011.5941084
ZTE, ZTE MICROELECTRONICS: "Complexity, throughput and latency considerations on LDPC codes for eMBB", 3GPP DRAFT; R1-1701599 COMPLEXITY, THROUGHPUT AND LATENCY CONSIDERATIONS ON LDPC CODES FOR EMBB_FINAL, 3RD GENERATION PARTNERSHIP PROJECT (3GPP), MOBILE COMPETENCE CENTRE ; 650, ROUTE DES LUCIOLES ; F-06921 SOPHIA-ANTIPOLIS CEDEX ; FRANCE, vol. RAN WG1, no. Athens, Greece; 20170213 - 20170217, 12 February 2017 (2017-02-12), Mobile Competence Centre ; 650, route des Lucioles ; F-06921 Sophia-Antipolis Cedex ; France , XP051208766
GUOHUI WANG ; MICHAEL WU ; YANG SUN ; JOSEPH R. CAVALLARO: "A massively parallel implementation of QC-LDPC decoder on GPU", APPLICATION SPECIFIC PROCESSORS (SASP), 2011 IEEE 9TH SYMPOSIUM ON, IEEE, 5 June 2011 (2011-06-05), pages 82 - 85, XP031956458, ISBN: 978-1-4577-1212-8, DOI: 10.1109/SASP.2011.5941084
Attorney, Agent or Firm:
CHINA TRUER IP (CN)
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