Title:
MANUFACTURING METHOD FOR SEMICONDUCTOR STRUCTURE, AND SEMICONDUCTOR STRUCTURE
Document Type and Number:
WIPO Patent Application WO/2023/272782
Kind Code:
A1
Abstract:
The present disclosure provides a manufacturing method for a semiconductor structure, and a semiconductor structure. The manufacturing method for the semiconductor structure comprises: forming a plurality of capacitor holes on a substrate, and the bottom ends of the capacitor holes exposing part of the substrate; forming a lower electrode layer on the surfaces of the capacitor holes; forming, on the surface of the lower electrode layer, a dielectric layer continuously covering the surface of the lower electrode layer; continuously covering a first upper electrode layer on the surface of the dielectric layer by means of a first film forming process; and by means of a second film forming process, forming, in the circumferential direction of the capacitor holes, a second upper electrode layer continuously covering the surface of the first upper electrode layer, and forming, in the axial direction of the capacitor holes, a second upper electrode layer that does not continuously cover the surface of the first upper electrode layer.
Inventors:
WU YULEI (CN)
Application Number:
PCT/CN2021/106440
Publication Date:
January 05, 2023
Filing Date:
July 15, 2021
Export Citation:
Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
H01L27/108; H01L21/8242
Foreign References:
| CN108511424A | 2018-09-07 | |||
| CN110970401A | 2020-04-07 | |||
| CN104716019A | 2015-06-17 | |||
| US20040051131A1 | 2004-03-18 | |||
| US20110204427A1 | 2011-08-25 |
Attorney, Agent or Firm:
BOXIN CHINA INTELLECTUAL PROPERTY (CN)
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