MANUFACTURING METHOD FOR SOLAR CELL

WIPO Patent Application WO/2020/022044

A1

In the present invention, the main surface of a semiconductor substrate 11, the outer shape of which is square or square-like, is configured to have a textured structure formed from a plurality of ridges and a plurality of valleys. The plurality of valleys includes first and second valleys respectively oriented in a first and a second direction, which follow the main sides of the outer edges of the semiconductor substrate 11. In this manufacturing method for a solar cell which includes the semiconductor substrate 11, a semiconductor layer 13p of a first conductivity type is formed on the main surface of the substrate that has the textured structure, then a lift-off layer LF is formed on the semiconductor layer 13p, and thereafter the lift-off layer LF and the semiconductor layer 13p are patterned. Next, a semiconductor layer 13n of a second conductivity type is formed on the main surface of the substrate that includes the patterned lift-off layer LF and semiconductor layer 13p, and then the semiconductor layer 13n is removed with an etching solution along with the lift-off layer LF. The etching speed of the etching solution with respect to the lift-off layer LF is greater than the etching speed with respect to the semiconductor layer 13p.

WO/2013/045574	PHOTOVOLTAIC SEMICONDUCTOR CHIP
WO/2016/098368	METHOD FOR PRODUCING PHOTOVOLTAIC DEVICE
WO/2015/033864	METHOD FOR MANUFACTURING SOLAR CELL

NAKANO KUNIHIRO (JP)
KUCHIYAMA TAKASHI (JP)

PCT/JP2019/026990

January 30, 2020

July 08, 2019

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KANEKA CORP (JP)

H01L31/0236; H01L31/0747

WO2015060432A1	2015-04-30
WO2017217219A1	2017-12-21
WO2016129481A1	2016-08-18
WO2015058105A1	2015-04-23

JP2005353998A	2005-12-22
JP2010532817A	2010-10-14
JP2001352083A	2001-12-21

MAEDA & PARTNERS (JP)

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