Title:
MASK
Document Type and Number:
WIPO Patent Application WO/2021/190396
Kind Code:
A1
Abstract:
Provided is a mask (1000), comprising a first boundary area (21) and a plurality of exposure pattern areas (10), wherein the first boundary area (21) comprises a region surrounding the plurality of exposure pattern areas (10); and the first boundary area (21) is provided with a plurality of first overlay mark units (210), each of the first overlay mark units (210) comprising a plurality of overlay marks (201). The plurality of overlay marks (201) are arranged in sequence in the direction of extension of adjacent horizontal or longitudinal first boundary lines (1). The plurality of first overlay mark units (210) are symmetrical in pairs, with the center line of the mask (1000) being the axis of symmetry, and two symmetrical first overlay mark units (210) form one overlay mark group (200). The arrangement directions of the overlay marks (201) in the two first overlay mark units (210) of the same overlay mark group (200) are parallel and mutually staggered. The problem of a related mask layout limiting the number of chips of a wafer (2000) is solved, the area of a boundary region (20) is reduced, and the space between exposure fields is also reduced, thereby increasing the utilization rate of the wafer (2000), and improving the efficiency of chip production.
Inventors:
XIA YUNSHENG (CN)
Application Number:
PCT/CN2021/081608
Publication Date:
September 30, 2021
Filing Date:
March 18, 2021
Export Citation:
Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
G03F1/42; G03F9/00
Foreign References:
| CN112731759A | 2021-04-30 | |||
| US6114072A | 2000-09-05 | |||
| CN102096328A | 2011-06-15 | |||
| CN101183213A | 2008-05-21 | |||
| CN1677616A | 2005-10-05 | |||
| CN104297989A | 2015-01-21 | |||
| US20010048145A1 | 2001-12-06 |
Attorney, Agent or Firm:
BEIJING INTELLEGAL INTELLECTUAL PROPERTY AGENT LTD. (CN)
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