Background

[0001 ] A semiconductor device may contain a memory, such as a dynamic random access memory (DRAM). For a DRAM, each memory cell may include a transistor and a capacitor. In this manner, the capacitor may be charged or discharged to store a "1 " bit or a "0" bit. For purposes of enhancing performance of a computer system, the DRAM may be placed in the same die or in the same package as central processing unit (CPU) cores of the system. Such memories are referred to as "embedded DRAMs," or "eDRAMs."

Brief Description Of The Drawings

[0002] Figs. 1 , 2, 3, 4 and 5 are schematic diagrams of integrated circuit (IC) structures illustrating fabrication of a metal-insulator-metal (MIM) capacitor array for an embedded memory according to an example implementation.

[0003] Figs. 6A and 6B illustrate a technique to fabricate a MIM capacitor array according to an example implementation.

[0004] Fig. 7 is a schematic diagram of a semiconductor package according to an example implementation.

[0005] Figs. 8 and 9 are schematic diagrams of systems according to example implementations.

Detailed Description

[0006] Reference will now be made to the drawings wherein like structures may be provided with like suffix reference designations. In order to show the structures of various implementations more clearly, the drawings included herein are diagrammatic representations of semiconductor/circuit structures. Thus, the actual appearance of the fabricated integrated circuit structures, for example in a photomicrograph, may appear different while still incorporating the claimed structures of the illustrated implementations. Moreover, the drawings may only show the structures useful to understand the illustrated implementations. Additional structures known in the art may not have been included to maintain the clarity of the drawings. For example, not every layer of a semiconductor device is necessarily shown.“An implementation”, “various implementations” and the like indicate implementation(s) so described may include particular features, structures, or characteristics, but not every implementation necessarily includes the particular features, structures, or characteristics. Some implementations may have some, all, or none of the features described for other implementations.“First”,“second”,“third” and the like describe a common object and indicate different instances of like objects are being referred to. Such adjectives do not imply objects so described must be in a given sequence, either temporally, spatially, in ranking, or in any other manner. “Connected” may indicate elements are in direct physical or electrical contact with each other and“coupled” may indicate elements co-operate or interact with each other, but they may or may not be in direct physical or electrical contact.

[0007] Multiple patterning techniques, such as pitch halving, may be used to scale semiconductor components to pitches beyond the limits of the lithography mask. As the pitches are ever decreasing, semiconductor components may experience adverse effects from adjacent components.

[0008] For example, due to the ever-decreasing pitch, a memory cell of an

embedded memory, such as an embedded dynamic random access memory

(eDRAM), may experience soft errors due to the electric fields of adjacent cells. In this manner, the memory cells of an eDRAM may contain metal-insulator-metal (MIM) double wall capacitors. The inner wall, or electrode, of the double wall capacitor may be surrounded by an outer wall, or electrode, of the capacitor; and the inner and outer electrodes may be separated by a relatively high-k dielectric material. Depending on the voltage that is applied across the inner and outer electrodes, the capacitor may be charged or discharged to store a particular value for its given memory cell. The applied voltage across the inner and outer electrodes creates a corresponding electric field. As the memory cell pitch decreases, there may be an ever increasing problem of the electric fields from adjacent memory cells interfering with each other, thereby potentially leading to soft errors.

[0009] In accordance with example implementations, a memory array contains metal ground shields between capacitors of the array. These ground shields, in turn, serve to inhibit, if not block, electric field interference, i.e., inhibit, if not prevent, an electric field generated due to the operation of a first capacitor, from interfering with the data content stored in an adjacent capacitor.

[0010] As a more specific example, Figs. 1 to 5 depict structures involved in the fabrication of two adjacent double wall capacitors for a memory array (an eDRAM array, for example), in accordance with some implementations. In accordance with example implementations the memory array is formed in a metal-insulator-metal (MIM) part of a die as part of the die's backend of the line (BEOL) portion. The structures depicted in Figs. 1 to 4 depict the fabrication and progression of a final structure 500 (Fig. 5) that includes a pair of double wall MIM capacitors and an intervening, electric field inhibiting ground shield that is disposed in between the pair of capacitors.

[0011 ] Referring to Fig. 1 , the fabrication occurs in a vertical direction (for the depicted orientation) along a vertical Y axis of a set 101 of orthogonal lateral X and vertical Y axes. In this context, the X and Y axes being "orthogonal" refers to an angle between the axes being in a range of 80 to 100 degrees.

[0012] Fig. 1 depicts an intermediate structure 120, which contains an etch stop layer 108 (a silicon nitride or other nitride material, as examples) and a dielectric layer 104, which has been deposited on the layer 108. As examples, the dielectric layer 104 may be silicon oxide, silicon nitride, silicon oxynitride, fluorine doped silicon dioxide, carbon doped silicon dioxide or an organic polymer. Fig. 1 also depicts dielectric spacers 102 (four dielectric spacers 102-1 , 102-2, 102-3 and 102-4), which are have formed on the dielectric layer 104 for purposes of defining the lateral boundaries (along the X axis 101 ) of trenches that, as described below, corresponding to a pair of MIM capacitors and a ground shield that extends between the MIM capacitors. It is noted that, in accordance with example implementations, the die contains a metal layer beneath the structure that forms electrical ground contacts (not shown) for the capacitors.

[0013] In accordance with some implementations, the dielectric spacers 102 may be formed by forming a dielectric layer (a dielectric material, such as one of the above- mentioned dielectric materials) on the dielectric layer 104 and then using a multiple patterning technique, such as pitch halving, to form the dielectric spacers 102 at distances corresponding to trench diameters for the double wall capacitors. For the particular example depicted in Fig. 1 , the dielectric spacers 102-2 and 102-3 are spaced apart along the X axis 101 by a half pitch distance Di for purposes of forming the lateral boundaries of the ground shield. Moreover, the spacers 102-1 and 102-1 are spaced apart along the X axis 101 by a full pitch distance D ₂ , which defines the lateral diameter of one of the pair of double wall MIM capacitors. In a similar manner the spacers 102-3 and 102-4 are spaced apart by a full pitch distance to define the lateral diameter of the other double wall MIM capacitor.

[0014] In accordance with example implementations, the dielectric spacers 102 define the boundaries for dry etching corresponding trenches in the dielectric layer 104 for the pair of double wall MIM capacitors and the intervening ground shield.

[0015] More specifically, Fig. 2 depicts an intermediate structure 200 formed from the structure 120 of Fig. 1. In this manner, the structure 200 includes trenches formed from the dry etching of the dielectric layer 104: a vertically extending trench 204 (i.e., the trench 204 is generally elongated along the Y axis 101 such that the trench 204 extends in a positive direction along the Y axis 101 from a bottom end of the trench 204 to a top end of the trench 204) for a first double wall MIM capacitor (herein called the "first capacitor"); and a vertically extending trench 230 formed for a second double wall MIM capacitor (herein called the "second capacitor"). Thus, the first and second MIM capacitors are laterally offset from each other along the X axis 101. The structure 200 also includes a trench 220 for an intervening ground shield between the first and second capacitors. Moreover, the structure 200 of Fig. 2 contains metal layers and a high-k dielectric material that form the electrodes and insulators for the first and second capacitors, as well as the ground shield.

[0016] More specifically, in accordance with example implementations, to form the structure 200, after the dry etching of the dielectric layer 104 to form the trenches 204, 220 and 230, a conformal metal layer 250 is deposited. As examples, the metal layer 205, as well as the other metal layers described herein may contain one of the following metals: copper, silver, nickel, aluminum, titanium, gold, gold-germanium, nickel-platinum, nickel-aluminum, cobalt or any other metal. As examples, the metal layer 250 may be deposited using chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD).

[0017] Because the trench 220 for the ground shield has a narrower width than the trenches 204 and 230 (due to the half pitch spacing between the spacers 102-2 and 102-3, as depicted in Fig. 1 ), the metal layer 250 partially fills the trenches 204 and 230 and completely fills the trench 220 corresponding to the ground shield. Thus, the metal layer 250 includes a portion 250-1 that contacts the dielectric layer 104 inside the trench 204 to form an outer electrode for the first capacitor; a portion 250-2 that contacts the dielectric layer 104 inside the trench 230 to form an outer electrode for the second capacitor and a portion 250-2 that contacts the dielectric layer 104 and fills the trench 220 to form the ground shield.

[0018] As also depicted in Fig. 2, the intermediate structure 200 may further include a conformal high-k dielectric layer 244 that is formed on and contacts the metal layer 250. The high-k dielectric layer 244 includes a portion 244-1 that extends inside the trench 204 and contacts the metal layer 250 to form the insulator between the two electrodes of the first capacitor; and the high-k dielectric layer 244 includes a portion 244-2 that extends inside the trench 230 and contacts the metal layer 250 to form the insulator between the two electrodes of the second capacitor. In this context, a "high- k" dielectric layer refers to a layer containing a dielectric material that has a dielectric constant greater than the dielectric constant of silicon dioxide (a dielectric constant greater than "4," for example). As examples, the high-k dielectric layer 244 may contain such high-k materials as a hafium-based material (nitride hafium silicate (HfSiON, for example), or another high-K material.

[0019] Another conformal metal layer 240 (one of the metals mentioned herein) may be deposited on the high-k dielectric layer 244, using CVD or ALD, resulting in a portion 240-2 of the metal layer 240 inside the first trench 204 to form the inner electrode of the first capacitor, and a portion 240-3 of the metal layer 240 inside the trench 230 to form the inner electrode of the second capacitor. Moreover, as depicted in Fig. 2, a portion of the metal layer 240-1 forms the top layer of the structure 200. [0020] Referring to Fig. 3, in accordance with example implementations, the high-k dielectric material 244 and the metal layers 240 and 250 may be patterned to form a structure 300. In this manner, the patterning may involve subtractive patterning (a patterning involving applying a mask and then dry etching, for example) to remove parts of the structure 200 (Fig. 2), as depicted at reference numerals 310, 314 and 320, for purposes of forming metal connections with the inner electrodes of the first and second capacitors and a metal connection with the ground shield. In this manner, through the inner electrodes and ground shield may be connected to a metal layer (described below) for purposes of connecting the inner electrodes and ground shield to ground.

[0021 ] As depicted in Fig. 3, in the structure 300, vertical sidewalls 330 of the metal layer 250 are exposed. This exposure, in turn, may cause shorting between the capacitor electrodes (i.e. , between the supply and ground), if not for the additional process steps described below. Referring to Fig. 4, for purposes of preventing electrical shorting dielectric spacers 410 are formed on the sidewalls 330. In this manner, each dielectric spacer 410 has a surface contacting the sidewall 310.

[0022] Referring to Fig. 5, next, a third metal layer 510 is deposited to form a structure 500. As depicted in Fig. 5, the third metal layer 510 contacts the portion 240-1 of the second metal layer 240, thereby forming an electrical contact with the inner electrodes of the capacitors. Moreover, as also depicted in Fig. 5, the third metal layer 510 contacts the first metal layer 250 of the ground shield. As such, the inner walls of the capacitors and the ground shield may be electrically connected together (connected to ground, for example).

[0023] Referring to Fig. 6A, thus, in accordance with example implementations, a process 600 may be used to fabricate pitch halving may be used (block 604) to form dielectric spacers from a first dielectric material that is deposited on a second dielectric material. The dielectric spacers may then be polished (block 608), and next, the second dielectric layer may be dry etched (block 612) using the dielectric spacers to form first, second and third trenches in the dielectric layer. The process 600 includes depositing (block 616) a first metal layer in the first, second and third trenches to form an outer conductor for the first capacitor in the first trench, a ground shield in the second trench, and an outer conductor for the second capacitor in the third trench. A third dielectric layer may then be deposited (block 620) in the first and third trenches to form a high-k dielectric material for the first and second capacitors.

[0024] Referring to Fig. 6B, the technique 600, in accordance with example implementations, includes depositing (block 624) a second metal to form an inner electrode for the first capacitor in the first trench and an inner electrode for the second capacitor in the third trench. The technique 600 includes, pursuant to block 628, dry etching the first metal, the second metal and the third dielectric material to form second metal contact regions for the first and second capacitors, and exposing the first metal of the ground shield. Pursuant to block 632, a fourth dielectric material may then be deposited, and the fourth dielectric material may be dry etched (block 636) to form spacers on exposed sidewalls of the first metal inner conductor. Finally, pursuant to block 640, a third metal may be deposited (block 640) to contact a second metal of the first capacitor, the second capacitor and the ground shield.

[0025] Referring to Fig. 7, in accordance with example implementation

implementations, the techniques that are described herein may be used to fabricate a MIM capacitor-based memory 734 having ground shields, as described herein. The memory 734 may be, for example, an embedded memory (an eDRAM, for example), that is fabricated on a semiconductor die in which one or multiple processor cores 726 are fabricated. The die 710 may be packages as part of a semiconductor package 700. In accordance with further example implementations, the processor cores 726 and memory 734 may be fabricated in separate dies inside the

semiconductor package 700. Moreover, in accordance with example

implementations, the memory 734 may be part of the back end of the line (BEOL) components 730 of the die 710; and the processor cores 726 may be part of the front end of the line (FEOL) components 720 of the die 710, along with other components, such as transistors 724.

[0026] Referring now to Fig. 8, in accordance with example implementations, a system may include integrated circuits, which MIM capacitor-based memories having ground shields, as described herein. For example, the system may contain various semiconductor packages, such as semiconductor packages containing a baseband processor 805, an application processor 810 and a security processor 850, where the processors of these semiconductor packages include MIM capacitor-based memories having ground shields and communicate with each other.

[0027] In accordance with example implementations, the system of Fig. 8 may be, as examples, a smartphone, a wireless communicator, or any other loT device. The baseband processor 805 may be configured to communicate with the application processor 810, and the application processor 810 may be, for example, a main CPU of the system to execute an operating system (OS) and other system software, in addition to user applications such as many well-known social media and multimedia apps. The application processor 810 may further be configured to perform a variety of other computing operations for the device.

[0028] In turn, the application processor 810 may provide output and/or receive input through a user interface/display 820 (e.g., touch screen display). In addition, the application processor 810 may store and retrieve data to/from in its embedded MIM capacitor memory, as well as possibly store/retrieve data to/from other external memories, such as a memory system that includes a non-volatile memory, namely a flash memory 830 and a volatile memory, such as a DRAM 835. In some

implementations, the flash memory 830 may include a secure portion in which secrets and other sensitive information may be stored. The application processor 810 may also communicate with one or multiple input capture devices 845, such as one or multiple image capture devices that can record video and/or still images.

[0029] The system of Fig. 8 may also include a universal integrated circuit card (UICC) 840, which includes a subscriber identity module. In accordance with example implementations, the UICC 840 may include a secure storage 842 to store secure user information.

[0030] In accordance with example implementations, the security processor 850 may be a Trusted Platform Module (TPM). Moreover, the system may include one or multiple sensors 825, such as one or multiple axis accelerometers that provide input to the application processor 810 to enable input of a variety of sensed information, such as motion and other environmental information. In addition, the system may include one or multiple authentication devices 895, which may be used to receive, for example, user biometric input for use in authentication operations.

[0031 ] Among its other features, the system of Fig. 8 may further include a near field communication (NFC) contactless interface 860 for purposes of providing NFC communication using an NFC antenna 865. A power management integrated circuit (PMIC) 815 may communicate with the application processor 810 to perform platform level power management. To this end, the PMIC 815 may issue power management requests to the application processor 810 to enter certain low power states as desired. Furthermore, based on platform constraints, the PMIC 815 may also control the power level of other components of system.

[0032] To enable communications to be transmitted and received, such as in one or multiple Internet of Things (loT) networks, various circuitries may be coupled between the baseband processor 805 and an antenna 890. Specifically, a radio frequency (RF) transceiver 870 and a wireless local area network (WLAN) transceiver 875 may be present. In general, the RF transceiver 870 may be used to receive and transmit wireless data and calls according to a given wireless communication protocol such as 3G or 4G wireless communication protocol such as in accordance with a code division multiple access (CDMA), global system for mobile communication (GSM), long term evolution (LTE) or other protocol. In addition a GPS sensor 880 may be present, with location information being provided to the security processor 850 for use as described herein when context information is to be used in a pairing process.

Other wireless communications, such as receipt or transmission of radio signals (e.g., AM/FM) and other signals may also be provided. In addition, via WLAN transceiver 875, local wireless communications, such as according to a Bluetooth™, or IEEE 802.11 standard, can also be realized.

[0033] Referring to Fig. 9, in accordance with further example implementations, a multiprocessor system, such as a point-to-point interconnect system (a server system, for example) may include integrated circuits, which MIM capacitor-based memories having ground shields, as described herein. For example, the

multiprocessor system may contain various semiconductor packages, such as semiconductor packages containing processors 970 and 980, which communicate with each other using a point-to-point interconnect 950.

[0034] In accordance with example implementations, each of processors 970 and 980 may be multicore processors such as SoCs, including first and second processor cores (i.e. , processor cores 974a and 974b and processor cores 984a and 984b), although potentially many more cores may be present in the processors. In addition, processors 970 and 980 each may include a secure engine 975 and 985 to perform security operations such as attestations, loT network onboarding or so forth.

[0035] In accordance with example implementations, one or multiple integrated circuits or semiconductor devices may include non-planar transistors having conformal metal contacts, as disclosed herein. These integrated circuits may include integrated circuits containing the processor 910, the processor 970, the memory 935, the memory 932, the memory 932, the memory 934 or the memory 928, as just a few examples.

[0036] First processor 970 further includes a memory controller hub (MCH) 972 and point-to-point (P-P) interfaces 976 and 978. Similarly, second processor 980 includes a MCH 982 and P-P interfaces 986 and 988. MCH’s 972 and 982 couple the processors to respective memories, namely a memory 932 and a memory 934, which may be portions of main memory (e.g., a DRAM) locally attached to the respective processors. First processor 970 and second processor 980 may be coupled to a chipset 990 via P-P interconnects 952 and 954, respectively. Chipset 990 includes P- P interfaces 994 and 998.

[0037] Furthermore, chipset 990 includes an interface 992 to couple chipset 990 with a high performance graphics engine 938 by a P-P interconnect 939. In turn, chipset 990 may be coupled to a first bus 916 via an interface 996. Various input/output (I/O) devices 914 may be coupled to first bus 916, along with a bus bridge 918 which couples first bus 916 to a second bus 920. Various devices may be coupled to second bus 920 including, for example, a keyboard/mouse 922, communication devices 926 and a data storage unit 928 such as a non-volatile storage or other mass storage device. As seen, data storage unit 928 may include code 930, in one implementation. As further seen, data storage unit 928 also includes a trusted storage 929 to store sensitive information to be protected. Further, an audio I/O 924 may be coupled to second bus 920.

[0038] In accordance with example implementations, the technique 600 of Figs. 6A and 6B may be implemented by executing machine executable instructions, or "program code," which is stored on non-transitory media. In this manner, the program code, when executed by one or multiple central processing unit(s), (one or multiple processing cores, and so forth) may cause the processor to fabricate at least one integrated circuit to perform one or multiple operations. Implementations (e.g., code for implementing the process 600 of Figs. 6A and 6B) may be implemented in code and may be stored on a non-transitory storage medium having stored thereon instructions which can be used to program a system to perform the instructions.

Implementations also may be implemented in data and may be stored on a non- transitory storage medium, which if used by at least one machine, causes the at least one machine to fabricate at least one integrated circuit to perform one or more operations. As examples, the storage media may include semiconductor storage devices, magnetic storage devices, optical storage devices, and so forth. As more specific examples, the storage media may include floppy disks, optical disks, solid state drives (SSDs), compact disk read-only memories (CD-ROMs), compact disk rewritable (CD-RWs), and magneto-optical disks, semiconductor devices such as read-only memories (ROMs), random access memories (RAMs) such as dynamic random access memories (DRAMs), static random access memories (SRAMs), erasable programmable read-only memories (EPROMs), flash memories, electrically erasable programmable read-only memories (EEPROMs), magnetic or optical cards, or any other type of media suitable for storing electronic instructions.

[0039] The following examples pertain to further implementations.

[0040] Example 1 includes an apparatus that includes a first capacitor, a second capacitor, a second trench, a third metal and a fourth metal. The first capacitor includes a first trench, a first metal, a second metal and a dielectric material. The first trench extends from a first end of the first trench to a second end of the first trench along an axis. The first metal is in the first trench and extends along the axis to a first distance from the first end of the first trench; the second metal is in the first trench surrounding the second metal; and the dielectric material is between the first metal and the second metal. The second trench is between the first trench and the first capacitor, where the second trench extends from a first end of the second trench to a second end of the second trench along the axis. The third metal is in the second trench. The third metal extends along the axis to a second distance from the first end of the second trench, and the second distance is greater than the first distance. The fourth metal is in contact with the first metal and the third metal.

[0041 ] In Example 2 the subject matter of Example 1 can optionally include the apparatus further including a dielectric layer. The dielectric layer has a first removed portion that corresponds to the first trench and a second removed portion that corresponds to the second trench. The third metal contacts the dielectric layer.

[0042] In Example 3, the subject matter of Examples 1 -2 may further include a metal layer including the fourth metal, where the metal layer is elongated along an axis that is orthogonal to the axis along which the first trench extends.

[0043] In Example 4, the subject matter of Examples 1 -3 may optionally include the second trench including a sidewall to define the second trench. The sidewall contacts the third metal.

[0044] In Example 5, the subject matter of Examples 1 -4 may optionally include the dielectric material in contact with the first metal and the second metal.

[0045] In Example 6, the subject matter of Examples 1 -5 may optionally include the first metal including a first portion that extends along the axis; and a second portion that extends along another axis orthogonal to the axis. The second portion of the first metal includes a first surface that contacts the dielectric material and a second surface that contacts the fourth metal.

[0046] In Example 7, the subject matter of Examples 1 -6 may optionally include the dielectric material between the first metal and the second being a first dielectric material, and the second metal may include a sidewall portion outside of the first trench. The apparatus may further include a second dielectric material between the second metal and the fourth metal. The second dielectric material includes a first surface that contacts the sidewall portion of the second metal and a second surface that contacts the fourth metal.

[0047] In Example 8, the subject matter of Examples 1 -7 may optionally include the second dielectric material including silicon and oxygen.

[0048] In Example 9, the subject matter of Examples 1 -8 may optionally include the third metal completely filling the trench.

[0049] In Example 10, the subject matter of Examples 1 -9 may optionally include the dielectric material between the first metal and the second metal having a dielectric constant greater than four.

[0050] In Example 11 , the subject matter of Examples 1-10 may further include a third capacitor; and a fourth metal between the first trench and the third capacitor.

The fourth metal extends along the axis.

[0051 ] In Example 12, the subject matter of Examples 1-11 may optionally include the first and second capacitors being double walled capacitors.

[0052] In Example 13, the subject matter of Examples 1-12 may optionally include the first metal including copper; silver; nickel; aluminum; titanium; gold; gold and germanium; nickel and platinum; nickel and aluminum; or cobalt.

[0053] In Example 14, the subject matter of Examples 1-13 may optionally include the second metal including copper; silver; nickel; aluminum; titanium; gold; gold and germanium; nickel and platinum; nickel and aluminum; or cobalt.

[0054] In Example 15, the subject matter of Examples 1-14 may optionally include the third metal including copper; silver; nickel; aluminum; titanium; gold; gold and germanium; nickel and platinum; nickel and aluminum; or cobalt.

[0055] In Example 16, a computing system may include a first semiconductor package that includes a first processor and a memory, where the memory includes an apparatus according to any of Examples 1 to 15. The computing system may include a second semiconductor package other than the first semiconductor package, where the second semiconductor package includes a second processor to communicate with the first processor.

[0056] In Example 17, an apparatus includes a semiconductor package; a plurality of transistors in the semiconductor package; and a memory in the semiconductor package. The memory includes a first capacitor, a second capacitor and a third metal. The first capacitor includes a first electrode, a second electrode and a dielectric material. The first electrode includes a first metal, where the first metal is elongated along a first direction, the first metal has a first dimension along a second direction, and the second direction is orthogonal to the first direction. The second electrode includes a second metal, where the second metal is elongated along the first direction. The dielectric material is between the first and second electrodes. The second capacitor is offset from the first capacitor in the second direction. The third metal is between the first capacitor and the second capacitor, where the third metal is elongated along the first direction, the third metal has a second dimension along the second direction and the second dimension is greater than the first dimension of the first electrode.

[0057] In Example 18, the subject matter of Example 17 may optionally include the first capacitor being a double walled capacitor, and the second capacitor being a double walled capacitor.

[0058] In Example 19, the subject matter of Examples 17-18 may optionally include the memory further including a dielectric layer, a first trench and a second trench.

The dielectric layer may include a first wall that is elongated in the first direction and defines a boundary of the first trench; and the dielectric layer may include a second wall that is elongated in the first direction and defines a boundary of the second trench. The third metal contacts the second wall.

[0059] In Example 20, the subject matter of Examples 17-19 may optionally include third metal spanning across the second trench in the second direction.

[0060] In Example 21 , the subject matter of Examples 17-20 may optionally include a fourth metal elongated along the second direction. The fourth metal contacts the first metal and the third metal. [0061 ] In Example 22, the subject matter of Examples 14-18 may optionally include the second metal including a sidewall; and the memory may further include another dielectric material. The other dielectric material includes a first surface that contacts the sidewall and a second surface that contacts the fourth metal.

[0062] Example 23 includes a method that includes forming a first channel, a second channel and a third channel in a dielectric layer. The second channel is between the first channel and the second channel. The technique includes depositing a metal on the dielectric layer, where the depositing includes depositing the metal in the first channel to form a conductor for a first capacitor, depositing the metal in the third channel to form a conductor for a second capacitor, and depositing metal in the second channel to fill the second channel.

[0063] In Example 24, the subject matter of Example 23 may optionally include depositing the metal in the second channel including forming an electromagnetic shield between the first and second capacitors.

[0064] In Example 25, the subject matter of Examples 23-24 may optionally include forming a dielectric material on the dielectric layer; using pitch halving to pattern the dielectric material to form a patterned dielectric material; and etching the

semiconductor substrate using the patterned dielectric material to form the first, second and third channels.

[0065] The foregoing description of the implementations of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. This description and the claims following include terms, such as left, right, top, bottom, over, under, upper, lower, first, second, etc. that are used for descriptive purposes only and are not to be construed as limiting. For example, terms designating relative vertical position refer to a situation where a device side (or active surface) of a substrate or integrated circuit is the "top" surface of that substrate; the substrate may actually be in any orientation so that a "top" side of a substrate may be lower than the "bottom" side in a standard terrestrial frame of reference and still fall within the meaning of the term "top." The term "on" as used herein (including in the claims) does not indicate that a first layer "on" a second layer is directly on and in immediate contact with the second layer unless such is specifically stated; there may be a third layer or other structure between the first layer and the second layer on the first layer. The implementations of a device or article described herein can be manufactured, used, or shipped in a number of positions and orientations. Persons skilled in the relevant art can appreciate that many modifications and variations are possible in light of the above teaching. Persons skilled in the art will recognize various equivalent combinations and substitutions for various components shown in the Figures. It is therefore intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.