Technical Field

[0001] Embodiments of the invention are in the field of semiconductor devices and, in particular, transistors.

Background

[0002] A FinFET is a transistor built around a thin strip of semiconductor material (referred to as the “fin”). The transistor includes the standard field effect transistor (FET) nodes/components: a gate, a gate dielectric, a source region, and a drain region. The conductive channel of the device resides on the outer sides of the fin beneath the gate dielectric. Specifically, current runs along both“sidewalls” of the fin as well as along the top side of the fin. Because the conductive channel essentially resides along the three different outer, planar regions of the fin, such a FinFET is typically referred to as a“tri-gate” FinFET. Other types of FinFETs exist (such as“double-gate” FinFETs in which the conductive channel principally resides only along both sidewalls of the fin and not along the top side of the fin).

Brief Description of the Drawings

[0003] Features and advantages of embodiments of the present invention will become apparent from the appended claims, the following detailed description of one or more example embodiments, and the corresponding figures. Where considered appropriate, reference labels have been repeated among the figures to indicate corresponding or analogous elements.

[0004] Figure 1 depicts an embodiment of a highly stable gate dielectric on a high mobility channel FinFET.

[0005] Figure 2 depicts an embodiment of a highly stable gate dielectric on a high mobility channel FinFET.

[0006] Figure 3 depicts an embodiment of a highly stable gate dielectric on a high mobility channel FinFET.

[0007] Figure 4 depicts an embodiment of a highly stable gate dielectric on a high mobility gate-all-around device. [0008] Figure 5 includes a method in an embodiment for forming a highly stable gate dielectric on a high mobility channel FinFET.

[0009] Figures 6, 7, 8 depict systems that have increased stability and faster performance due to their inclusion of devices including a highly stable gate dielectric on a high mobility channel device.

[0010] Figure 9 includes an embodiment of a package with an embodiment of a highly stable gate dielectric on a high mobility channel FinFET.

[0011] Figure 10 depicts an embodiment of a highly stable gate dielectric on a high mobility channel FinFET.

[0012] Figure 11 depicts an embodiment of a highly stable gate dielectric on a high mobility channel FinFET.

Detailed Description

[0013] Reference will now be made to the drawings wherein like structures may be provided with like suffix reference designations. In order to show the structures of various embodiments more clearly, the drawings included herein are diagrammatic representations of semiconductor/circuit structures. Thus, the actual appearance of the fabricated integrated circuit structures, for example in a photomicrograph, may appear different while still incorporating the claimed structures of the illustrated embodiments. Moreover, the drawings may only show the structures useful to understand the illustrated embodiments. Additional structures known in the art may not have been included to maintain the clarity of the drawings. For example, not every layer (e.g., barrier layer, seed layer, etch stop layer) of a semiconductor device is necessarily shown.“An embodiment”,“various embodiments” and the like indicate embodiment s) so described may include particular features, structures, or characteristics, but not every embodiment necessarily includes the particular features, structures, or characteristics. Some embodiments may have some, all, or none of the features described for other embodiments.“First”,“second”,“third” and the like describe a common object and indicate different instances of like objects are being referred to. Such adjectives do not imply objects so described must be in a given sequence, either temporally, spatially, in ranking, or in any other manner. “Connected” may indicate elements are in direct physical or electrical contact with each other and“coupled” may indicate elements co-operate or interact with each other, but they may or may not be in direct physical or electrical contact. [0014] Stability of the above mentioned gate dielectrics (which often include gate oxides) is critical for transistors and other switching devices (e.g., diodes). Conventional gate oxides for silicon (Si) channel devices include Si0 ₂ . Si0 ₂ is a high quality oxide that tends to form at the interface of Si channels and high-K gate dielectrics that are deposited on the channels. The Si0 ₂ grows during thermal processing steps (e.g., anneals) necessary to process logic and memory devices, such as transistors. As such, the oxide is a“native oxide” that forms naturally during such processing steps. This native oxide is advantageous for Si channels because Si0 ₂ is a stable high quality gate dielectric.

[0015] However, Applicant has identified a problem that exists with forming gate dielectrics on non-Si channels with high mobility carriers (e.g., Ge based channels or channels including group III-V materials such as GaAs). The native oxides (e.g., arsenic oxide, indium oxide, or gallium oxide) for such channels are not stable and not of high quality. More specifically, Si0 ₂ is “stable” and of “high quality” because the Si has relatively few“dangling bonds” that are not bonded to oxygen. There is enough oxygen to satisfy the bond locations for the Si. As a result, the Si is not in need of satisfying those bonds with, for example, carriers in the channel. High thermal levels (e.g., more than 600 degrees Celsius) help distribute oxygen among the Si to ensure the Si bond sites are satisfied.

[0016] In contrast, Applicant determined that with III-V and/or IV (e.g., Ge) channels there may be oxygen poor conditions that cannot be alleviated with high temperature steps because such channels have thermal limits of, for example, less than 650 degrees Celsius (i.e., high mobility channels require lower processing temperatures as compared to Si channels so high temperature anneals common for Si channels cannot be used to stabilize the oxides and make them reliable for high mobility channels). As a result, the gate oxides that form on these high mobility channels are“unstable” over time and of“low quality” because oxygen does not fully satisfy the dangling bonds of the channel material. As a consequence, over time those oxides inconsistently access and release carriers from the channel to weakly satisfy those bonds.

[0017] Applicant has determined this gate oxide instability has detrimental effects on device performance. For example, the poorly bonded gate oxide (e.g., oxygen deficient) may undesirably lead to hysteresis within the threshold voltage (¼ _¾ ) curve (V _gate vs. I _drain ) for the device. Furthermore, the poorly bonded gate oxide may undesirably lead to permanent elevations of V _th over time. These effects may result in lower battery life for devices (e.g., devices included in the Internet of Things (IoT)) as well as inconsistent performance for such devices.

[0018] Fortunately, Applicant determined using rare earth oxides and/or silicides in the gate stack of non-Si channel devices leads to stable high quality gate dielectrics.

[0019] As used herein,“rare earth elements” include Lanthanides such as cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu). The lanthanide (or lanthanoid) series of chemical elements comprises the fifteen metallic chemical elements with atomic numbers 57 through 71, from lanthanum through lutetium.“Rare earth elements” also include Group 3B elements such as scandium (Sc), yttrium (Y), and lanthanum (La).

[0020] Applicant determined rare earth elements are highly electronegative and form strong, stable bonds to oxygen. Using such elements in a gate dielectric with a non-Si channel results in a gate oxide that is more reliable than other oxides (e.g., Al ₂ 0 ₃ , Si0 ₂ , AlSiOx, Hf0 ₂ , Zr0 ₂ , TaSiOx, HfSiOx) and does not require high temperature anneals to remain stable over time.

[0021] Applicant further determined a very high dielectric constant material is not always desired directly on the channel of a transistor and a lower dielectric constant material is needed. For instance, a gate oxide with a rare earth element may have a high dielectric constant (e.g., K > 15). Such an electronegative gate oxide may cause undesirable phonon scattering. However, Applicant determined adding Si to a rare earth element oxide lowers the dielectric constant and thus reduces carrier scattering in the channel. Thus, in certain embodiments rare earth oxides and silicates can be used in the gate stack to have a more stable oxide at lower temperatures. Doing so fulfills lower processing temperature budgets of non-Si channels. Eliminating/reducing high temperature steps also limits the growth of unwanted native oxides.

[0022] As used herein, a silicate is a compound containing an anionic silicon compound. As used herein, a silicide is a compound that has silicon with more electropositive elements. [0023] Figure 1 includes a device 100 comprising a channel 104 including a member selected from the group consisting of germanium, a group III-V material, or combinations thereof. For example, channel 104 may include Ge, InGaAs, InP, InAs, and the like. Device 100 further includes a first gate dielectric layer 105, comprising a first oxide, on the channel 104. Device 100 further includes a second gate dielectric layer 106, comprising a second oxide, on the first gate dielectric layer 105. Device 100 further includes a gate 107 on the second dielectric layer 106. Channel 104 may be a portion of a fin that is located over a subfin 103 and within a trench formed in material 102 (e.g., an oxide). Subfin 103 may include a material (e.g., SiGe, Si, InGaAs, InP, InAlAs, GaAs and suitable combinations thereof) that has a bandgap that is higher than the bandgap of the channel material (e.g., Ge). This helps reduce leakage current into substrate 101 (e.g., a Si substrate). Gate 107 may include various materials in various embodiments. For example, gate 107 may include a relatively high work function material (Pt, Pd, W and suitable combinations thereof) for a PMOS device or a relatively low work function material (Al, Ti, Ta, Hf, Zr, and their alloys and suitable combinations thereof) for an NMOS device.

[0024] At least one of the first and second oxides includes a material selected from the group consisting of a Group 3B element, a lanthanide element, or combinations thereof. For example, in device 100 the first oxide 105 includes oxygen bonded to Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Sc, Y, La, or combinations thereof.

[0025] In an embodiment the first oxide 105 includes silicon bonded to the material to lower the dielectric constant of the material adjacent channel 103, which will reduce phonon scattering.

[0026] In an embodiment the second oxide 106 does not include a material such as Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Sc, Y, La and suitable combinations thereof. However, the second oxide may include an oxide such as, for example, Hf0 ₂ , Zr0 ₂ , HfSiOx, ZrSiOx, HfAlSiOx, Ta ₂ O , TaSiOx and suitable combinations thereof.

[0027] In an embodiment both of the first and second oxides 105, 106 are disposed on at least two sides of the channel 104. For example, for device 100 first and second oxides 105, 106 are disposed on three sides (two sidewalls and a top) of the channel 104 to form a tri-gate FinFET. However, in other embodiments the channel region is comprised of at least one of a nanowire and a nanoribbon, and both of the first and second oxides are disposed on four sides (two sidewalls and top and bottom) of the channel. In such an instance the device is a“gate all around” (GAA) device. For example, in an embodiment both of the first and second gate oxides 105, 106 completely surround the channel within the plane that is orthogonal to a long axis 109 of the channel 104.

[0028] Further, embodiments such as the embodiment of Figure 1 allows one to keep temperatures relatively low (no extremely high temperature anneals). This may provide a benefit of better formation of gate oxide under the nanoribbon or nanowire. In other words, low temperature atomic layer deposition (ALD) of oxides is conformal and results in a uniform deposition of oxide on all sides of the channel material (tri-gate, wire, or ribbon). The benefit of the low temperature deposition is both uniformity of a thin oxide layer and the low temperature deposition inhibits the formation of a undesired native oxide (Ge, indium, arsenic, or gallium oxides).

[0029] Of course, in other embodiments the above first and second gate oxides may be used with a planar transistor (i.e., the first and second gate oxides are above the top surface of the channel).

[0030] In the embodiment of device 100 the first oxide 105 directly contacts both the channel 104 and the second oxide 106. However, in other embodiments there may be one or more layers between layers 105, 104 and/or layers 105, 106.

[0031] In an embodiment a majority of the first oxide has a first dielectric constant and a majority of the second oxide has a second dielectric constant that is greater than the first dielectric constant. This accounts for a reality that transitions between layers may not be entirely precise in real world semiconductor processing. Thus, in device 100 the middle most portion of layer 105 may be compared to a middle most portion of layer 106 wherein the middle most portion of layer 106 has a higher dielectric constant than that of the middle most portion of layer 105. This helps reduce phonon scattering (due to the lower dielectric constant being adjacent channel 104) while still increasing gate capacitance. In other words, Si0 ₂ has been used as a conventional gate oxide material. As transistors have decreased in size, the thickness of the Si0 ₂ gate dielectric has steadily decreased to increase the gate capacitance and thereby drive current, raising device performance. As the thickness scales ever lower, leakage currents due to tunneling increase drastically, leading to high power consumption and reduced device reliability. Replacing the Si0 ₂ gate dielectric with a high-k (also referred to herein as high K) material allows increased gate capacitance without the associated leakage effects. The embodiment described immediately above both increases gate capacitance (due to layer 106) and controls phonon scattering (due to layer 105).

[0032] In an embodiment, enough Si is added to layer 105 to lower its K value to below 15 and, in some embodiments, at 8 or below (e.g., 5, 6, 7) while the K value for layer 106 is kept above 15 (e.g., 20, 21, 22 or more).

[0033] In an embodiment at least one of the first and second oxides includes a graded amount of rare earth material. For example, in an embodiment device 100 includes a version of layer 105 including inner portion 105’ and outer portion 105” separated by dashed line 108. Portion 105’ may include a smaller % material composition of rare earth element(s) than layer 105” to diminish phonon scattering. In other words, in an embodiment first oxide portion 105’ includes a first portion having a first percentage composition of the rare earth material and a second portion 105” having a second percentage composition of the material that is greater than the first percentage, and the first portion 105’ is directly between the channel 104 and the second portion 105”.

[0034] In an embodiment area 105’ has a first % material composition of rare earth elements (and a first K level), area 105” has a second % material composition of rare earth elements and a second K level that is greater than the first % material composition and greater than the first K level, and area 106 has a third % material composition of rare earth elements and a third K level that is greater than the second % material composition and is greater than the second K level.

[0035] In an embodiment area 105’ has a first % material composition of rare earth elements (and a first K level and first Si % material composition), area 105” has a second % material composition of rare earth elements and a second K level that is greater than the first % material composition and greater than the first K level (and a second Si % material composition that is lower than the first Si % material composition), and area 106 has a third % material composition of rare earth elements and a third K level that is greater than the second % material composition and is greater than the second K level (and a third Si % material composition, such as 0%, that is lower than the second Si % material composition).

[0036] Figure 2 includes a device 200 comprising a channel 204 including a member selected from the group consisting of germanium, a group III-V material, or combinations thereof. For example, channel 204 may include Ge, InGaAs, InP, InAs, and combinations thereof, and the like. Device 200 further includes a first gate dielectric layer 205, comprising a first oxide, on the channel 204. Device 200 further includes a second gate dielectric layer 206, comprising a second oxide, on the first gate dielectric layer 205. Device 200 further includes a gate 207 on the second dielectric layer 206. Channel 204 may be a portion of a fin that is located over a subfin 203 and within a trench formed in material 202 (e.g., an oxide). Subfin 204 may include a material (e.g., SiGe, Si, InGaAs, InP, InAlAs, GaAs and suitable combinations thereof) that has a bandgap that is higher than the bandgap of the channel material (e.g., Ge). This helps reduce leakage current into substrate 201 (e.g., a Si substrate). Gate 207 may include various materials in various embodiments. For example, gate 207 may include a relatively high work function material (Pt, Pd, W and suitable combinations thereof) for a PMOS device or a relatively low work function material (Al, Ti, Ta, Hf, Zr, and their alloys and suitable combinations thereof) for an NMOS device.

[0037] At least one of the first and second oxides includes a material selected from the group consisting of a Group 3B element, a lanthanide element, or combinations thereof. For example, in device 200 the second oxide 206 includes oxygen bonded to Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Sc, Y, La, or combinations thereof.

[0038] In an embodiment the second oxide 206 includes silicon bonded to the rare earth material to lower the dielectric constant of the oxide.

[0039] In an embodiment the first oxide 205 does not include a material such as Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Sc, Y, La and suitable combinations thereof. However, the first oxide may include an oxide such as, for example, Hf0 ₂ , Zr0 ₂ , HfSiOx, ZrSiOx, HfAlSiOx, Ta ₂ O , TaSiOx and suitable combinations thereof.

[0040] While certain stoichiometries are recited herein (Ta ₂ O ) not all embodiments are so limited and more generally a embodiments of a specific stoichiometry should be read to be a subset of a more general arrangement such as a material including Ta, O (in varying composition percentages with respective with each other) and possibly other elements.

[0041] In an embodiment both of the first and second oxides 205, 206 are disposed on at least two sides of the channel 204. For example, for device 200 first and second oxides 205, 206 are disposed on three sides (two sidewalls and a top) of the channel 204 to form a tri-gate FinFET. However, in other embodiments the channel region is comprised of at least one of a nanowire and a nanoribbon, and both of the first and second oxides are disposed on four sides (two sidewalls and top and bottom) of the channel. In such an instance the device is a GAA device. For example, in an embodiment both of the first and second gate oxides 205, 206 completely surround the channel within the plane that is orthogonal to a long axis 209 of the channel 204. As explained above, this provides the ability to keep temperatures low and is a benefit to forming gate oxide under the ribbon or wire. Low temperature ALD deposition of oxides is conformal and results in a uniform deposition of oxide on all sides of the channel material (tri-gate, wire, or ribbon). The benefit of the low temperature deposition is both uniformity of a thin oxide layer and the low temperature deposition inhibits the formation of a undesired native oxide (Ge, indium, arsenic, or gallium oxides). Of course, in other embodiments the above first and second gate oxides may be used with a planar transistor (i.e., the first and second gate oxides are above the top surface of the channel).

[0042] In the embodiment of device 200 the first oxide 205 directly contacts both the channel 204 and the second oxide 206. However, in other embodiments there may be one or more layers between layers 205, 204 and/or layers 205, 206.

[0043] In an embodiment a majority of the first oxide has a first dielectric constant and a majority of the second oxide has a second dielectric constant that is greater than the first dielectric constant. This accounts for a reality that transitions between layers may not be entirely precise in real world semiconductor processing. Thus, in device 200 the middle most portion of layer 205 may be compared to a middle most portion of layer 206 wherein the middle most portion of layer 206 has a higher dielectric constant than that of the middle most portion of layer 205. This helps reduce phonon scattering (due to the lower dielectric constant being adjacent channel 204) while still increasing gate capacitance. The embodiment described immediately above both increases gate capacitance (due to layer 206) and controls phonon scattering (due to layer 205). [0044] In an embodiment, enough Si is added to layer 205 to lower its K value to below 15 and, in some embodiments, at 8 or below (e.g., 5, 6, 7) while the K value for layer 206 is kept above 15 (e.g., 20, 21, 22 or more).

[0045] In an embodiment at least one of the first and second oxides includes a graded amount of rare earth material. For example, in an embodiment device 200 includes a version of layer 206 including inner portion 206’ and outer portion 206” separated by dashed line 208. Portion 206’ may include a smaller % material composition of rare earth element(s) than layer 206” to diminish phonon scattering. In other words, in an embodiment oxide portion 206’ includes a first portion having a first percentage composition of the rare earth material and a second portion 206” having a second percentage composition of the material that is greater than the first percentage, and the first portion 206’ is directly between the channel 204 and the second portion 206”.

[0046] In an embodiment area 206’ has a first % material composition of rare earth elements (and a first K level), area 206” has a second % material composition of rare earth elements and a second K level that is greater than the first % material composition and greater than the first K level, and area 206’” has a third % material composition of rare earth elements and a third K level that is greater than the second % material composition and is greater than the second K level.

[0047] In an embodiment area 206’ has a first % material composition of rare earth elements (and a first K level and first Si % material composition), area 206” has a second % material composition of rare earth elements and a second K level that is greater than the first % material composition and greater than the first K level (and a second Si % material composition that is lower than the first Si % material composition), and area 206’” has a third % material composition of rare earth elements and a third K level that is greater than the second % material composition and is greater than the second K level (and a third Si % material composition, such as 0%, that is lower than the second Si % material composition).

[0048] Figure 3 includes a device 300 comprising a channel 304 including a member selected from the group consisting of germanium, a group III-V material, or combinations thereof. For example, channel 304 may include Ge, InGaAs, InP, InAs, combinations thereof, and the like. Device 300 further includes a first gate dielectric layer 305, comprising a first oxide, on the channel 304. Device 300 further includes a second gate dielectric layer 306, comprising a second oxide, on the first gate dielectric layer 305. Device 300 further includes a gate 307 on the second dielectric layer 306. Channel 304 may be a portion of a fin that is located over a subfin 303 and within a trench formed in material 302 (e.g., an oxide). Subfin 304 may include a material (e.g., SiGe, Si, InGaAs, InP, InAlAs, GaAs) that has a bandgap that is higher than the bandgap of the channel material (e.g., Ge). This helps reduce leakage current into substrate 301 (e.g., a Si substrate). Gate 307 may include various materials in various embodiments. For example, gate 307 may include a relatively high work function material (Hf, Pt, Pd, W) for a PMOS device or a relatively low work function material (Al, Ti, Ta, Hf, Zr, and their alloys) for an NMOS device.

[0049] At least one of the first and second oxides includes a material selected from the group consisting of a Group 3B element, a lanthanide element, or combinations thereof. For example, in device 300 first oxide 305 includes oxygen bonded to Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Sc, Y, La, or combinations thereof and second oxide 306 includes oxygen bonded to Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Sc, Y, La, or combinations thereof.

[0050] In an embodiment the first oxide 305 includes silicon bonded to the rare earth material to lower the dielectric constant of the oxide and second oxide 306 does not include a material such as Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Sc, Y, La.

[0051] In an embodiment the first oxide 305 includes silicon bonded to the rare earth material to lower the dielectric constant of the oxide.

[0052] In an embodiment both of the first and second oxides 305, 306 are disposed on at least two sides of the channel 304. For example, for device 300 first and second oxides 305, 306 are disposed on three sides (two sidewalls and a top) of the channel 304 to form a tri-gate FinFET. However, in other embodiments (See Figure 4) the channel region is comprised of at least one of a nanowire and a nanoribbon, and both of the first and second oxides are disposed on four sides (two sidewalls and top and bottom) of the channel. In such an instance the device is a GAA device. For example, in an embodiment both of the first and second gate oxides 405 (which includes the same materials as oxide 305), 406 (which includes the same materials as oxide 306) (and gate 407 in device 400) completely surround the channel 404 within the plane that is orthogonal to a long axis 309 of the channel 304.

[0053] As explained above, this provides the ability to keep temperatures low and is a benefit to forming gate oxide under the ribbon or wire. Low temperature ALD deposition of oxides is conformal and results in a uniform deposition of oxide on all sides of the channel material (tri-gate, wire, or ribbon). The benefit of the low temperature deposition is both uniformity of a thin oxide layer and the low temperature deposition inhibits the formation of a undesired native oxide (Ge, indium, arsenic, or gallium oxides). Of course, in other embodiments the above first and second gate oxides may be used with a planar transistor (i.e., the first and second gate oxides are above the top surface of the channel).

[0054] Returning to Figure 3, in the embodiment of device 300 the first oxide 305 directly contacts both the channel 304 and the second oxide 306. However, in other embodiments there may be one or more layers between layers 305, 304 and/or layers 305, 306.

[0055] In an embodiment a majority of the first oxide has a first dielectric constant and a majority of the second oxide has a second dielectric constant that is greater than the first dielectric constant. This accounts for a reality that transitions between layers may not be entirely precise in real world semiconductor processing. Thus, in device 300 the middle most portion of layer 305 may be compared to a middle most portion of layer 306 wherein the middle most portion of layer 306 has a higher dielectric constant than that of the middle most portion of layer 305. This helps reduce phonon scattering (due to the lower dielectric constant being adjacent channel 304) while still increasing gate capacitance. The embodiment described immediately above both increases gate capacitance (due to layer 306) and controls phonon scattering (due to layer 305).

[0056] In an embodiment, enough Si is added to layer 305 to lower its K value to below 15 and, in some embodiments, at 8 or below (e.g., 5, 6, 7) while the K value for layer 306 is kept above 15 (e.g., 20, 21, 22 or more).

[0057] In an embodiment at least one of the first and second oxides includes a graded amount of rare earth material. For example, in an embodiment device 300 includes a version of layer 305 including inner portion 305’ and outer portion 305” separated by dashed line 308. Portion 305’ may include a smaller % material composition of rare earth element(s) than portion 305” to diminish phonon scattering. In other words, in an embodiment oxide portion 305’ includes a first portion having a first percentage composition of the rare earth material and a second portion 305” having a second percentage composition of the material that is greater than the first percentage, and the first portion 305’ is directly between the channel 304 and the second portion 305”.

[0058] In an embodiment area 305’ has a first % material composition of rare earth elements (and a first K level), area 305” has a second % material composition of rare earth elements and a second K level that is greater than the first % material composition and greater than the first K level, and area 306 has a third % material composition of rare earth elements and a third K level that is greater than the second % material composition and is greater than the second K level.

[0059] In an embodiment area 305’ has a first % material composition of rare earth elements (and a first K level and first Si % material composition), area 305” has a second % material composition of rare earth elements and a second K level that is greater than the first % material composition and greater than the first K level (and a second Si % material composition (which could be 0% in some embodiments) that is lower than the first Si % material composition), and area 306 has a third % material composition of rare earth elements and a third K level that is greater than the second % material composition and is greater than the second K level (and a third Si % material composition, such as 0%, that is lower than the second Si % material composition and/or the first Si % material).

[0060] Figure 5 includes a method 500. Block 501 includes forming a trench within at least one of a dielectric layer and a substrate. These may include, for example, oxide and nitride interlayer dielectrics (Si0 ₂ , SiN, and SiON). Block 502 includes forming a fin within the trench. Block 503 includes forming a channel on the fin (which includes on top of or within the fin), the channel including a member selected from the group consisting of germanium, a group III-V material, or combinations thereof. Block 504 includes forming a first gate oxide on the channel and a second gate oxide on the first gate oxide, wherein at least one of the first and second gate oxides includes oxygen bonded to a material selected from the group consisting of cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), scandium (Sc), yttrium (Y), lanthanum (La), or combinations thereof. Block 505 includes forming a gate on the second gate oxide.

[0061] Due to the formation of native oxides (Ge, Ar, In, or Ga containing oxides) which are undesirable in some embodiments, it is beneficial to keep annealing and processing temperatures under 450 degrees C for less than a total of 5 hours after the deposition of the gate oxide. Thus, in the process flow described above, the high temperature steps of epitaxial source and drain growth (along with dopant activation anneals) are performed prior to the formation of the gate oxide and metal gate depositions. After the formation of the gate, the rest of the process is referred to as“back end” processing (i.e., metal contacts, interconnects, and isolating dielectrics) and is all typically below 450 degrees Celsius.

[0062] Figure 9 includes a package system in an embodiment. The system includes a processor die 901 (a first package) on a package substrate 903. A memory die (a second package) 902 couples to the substrate 903 by way of interposer system 907. Underfill material 916 exists between die 901 and substrate 903. Substrate 903 may include controlled collapse chip connection (C4) interconnects 906. Further, to prevent warping of die 901, die 901 may couple to a metal stiffener 904. Die 901 may include a die stack (e.g., multiple dies which may have the same function or differing functions) that may be molded as one unit that functions as a single die. For example, one die of the stack may have a first logic function while another die of the stack has another logic function that differs from the first logic function.

[0063] In the embodiment of Figure 9, die 901 includes a device such as the device of Figures 1-4. In another embodiment die 902 includes a device such as the device of any of Figures 1-4. In an embodiment die 901 includes a device such as the device of any of Figures 1-4 and die 902 includes a device such as the device of any of Figures 1-4.

[0064] In an embodiment element 904 is not a stiffener but instead is a heat spreader (or is both a stiffener and a heat spreader). A heat spreader is a heat exchanger that moves heat between a heat source and a secondary heat exchanger whose surface area and geometry are more favorable than the source. Such a spreader may be a plate made of copper, which has a high thermal conductivity. By definition, heat is "spread out" over this geometry, so that the secondary heat exchanger may be more fully utilized. This has the potential to increase the heat capacity of the total assembly.

[0065] Figure 10 includes a more“real world” depiction of an embodiment 1200. Source node 1202 couples to source contact 1204 and drain node 1203 couples to drain contact 1205. Gate 1207 includes a dielectric layer 1212 (analogous to layer 105 or 205 or 305 described above), a dielectric layer 1213 (analogous to layer 106 or 206 or 306 described above), and a workfunction metal 1214 (analogous to layer 107, 207, 307 described above). Gate 1207 is over channel 1206. Gate 1207 is adjacent spacer (e.g., a nitride) 1227.

[0066] In an embodiment the source contact 1204 includes a bottom surface 1228 that is between the source contact and the source 1202. In Figure 10 the source and drain nodes 1202, 1203 were epitaxially grown and are raised above channel 1206. The bottom surface 1228 of contact 1204 includes a middle portion 1230 and two lateral edges 1231, 1232. The two lateral edges are closer to the fin 1201 than the middle portion. For example, surface 1228 is concave in that it narrows as it moves away from the fin. In an embodiment a salicide layer 1233 exists between the source contact 1204 and the source 1202 (and/or between drain contact and drain).

[0067] Figure 11 includes an embodiment with a cross-section of a fin taken along the short axis of the fin. Fin 1301 is separated from other fins by dielectric 1334. Fin 1301 couples to a gate stack with dielectric layer 1311 (analogous to layers 105, 205, 305 described above), dielectric layer 1312 (a mixture of layers 1311 and 1313), dielectric layer 1313 (analogous to layers 106, 206, 306 described above), and metal layer 1314. Layers 1311 and 1334 may have no clear line of distinction between them. In another embodiment layers 1311, 1312 may be analogous to graded layers such as layers 105’, 105”. Again, not every layer (e.g., seed or barrier layers and the like) of embodiments is necessarily found in the figures described herein.

[0068] Various embodiments include a semiconductive substrate. Such a substrate may be a bulk semiconductive material this is part of a wafer. In an embodiment, the semiconductive substrate is a bulk semiconductive material as part of a chip that has been singulated from a wafer. In an embodiment, the semiconductive substrate is a semiconductive material that is formed above an insulator such as a semiconductor on insulator (SOI) substrate. In an embodiment, the semi conductive substrate is a prominent structure such as a fin that extends above a bulk semiconductive material.

[0069] Referring now to Figure 6, shown is a block diagram of an example system with which embodiments can be used. As seen, system 900 may be a smartphone or other wireless communicator or any other Internet of Things (IoT) device. A baseband processor 905 (which may include one or more switching devices such as any of the highly stable gate oxide-based transistors described herein) is configured to perform various signal processing with regard to communication signals to be transmitted from or received by the system. In turn, baseband processor 905 is coupled to an application processor 910 (which may include one or more switching devices such as any of the highly stable gate oxide-based transistors described herein), which may be a main CPU of the system to execute an OS and other system software, in addition to user applications such as many well-known social media and multimedia apps. Application processor 910 may further be configured to perform a variety of other computing operations for the device.

[0070] In turn, application processor 910 can couple to a user interface/display 920 (e.g., touch screen display) (which may include one or more switching devices such as any of the highly stable gate oxide-based transistors described herein). In addition, application processor 910 may couple to a memory system including a non-volatile memory, namely a flash memory 930 (which may include one or more switching devices such as any of the highly stable gate oxide-based transistors described herein) and a system memory, namely a DRAM 935 (which may include one or more switching devices such as any of the highly stable gate oxide-based transistors described herein). In some embodiments, flash memory 930 may include a secure portion 932 in which secrets and other sensitive information may be stored. As further seen, application processor 910 also couples to a capture device 945 such as one or more image capture devices that can record video and/or still images.

[0071] A universal integrated circuit card (UICC) 940 comprises a subscriber identity module, which in some embodiments includes a secure storage 942 (which may include one or more switching devices such as any of the highly stable gate oxide-based transistors described herein) to store secure user information. System 900 may further include a security processor 950 (e.g., Trusted Platform Module (TPM)) (which may include one or more switching devices such as any of the highly stable gate oxide-based transistors described herein) that may couple to application processor 910. A plurality of sensors 925 (which may include one or more switching devices such as any of the highly stable gate oxide-based transistors described herein), including one or more multi-axis accelerometers may couple to application processor 910 to enable input of a variety of sensed information such as motion and other environmental information. In addition, one or more authentication devices 995 may be used to receive, for example, user biometric input for use in authentication operations.

[0072] As further illustrated, a near field communication (NFC) contactless interface 960 is provided that communicates in a NFC near field via an NFC antenna 965. While separate antennae are shown, understand that in some implementations one antenna or a different set of antennae may be provided to enable various wireless functionalities.

[0073] A power management integrated circuit (PMIC) 915 (which may include one or more switching devices such as any of the highly stable gate oxide-based transistors described herein) couples to application processor 910 to perform platform level power management. To this end, PMIC 915 may issue power management requests to application processor 910 to enter certain low power states as desired. Furthermore, based on platform constraints, PMIC 915 may also control the power level of other components of system 900.

[0074] To enable communications to be transmitted and received such as in one or more IoT networks, various circuitries may be coupled between baseband processor 905 and an antenna 990. Specifically, a radio frequency (RF) transceiver 970 (which may include one or more switching devices such as any of the highly stable gate oxide-based transistors described herein) and a wireless local area network (WLAN) transceiver 975 (which may include one or more switching devices such as any of the highly stable gate oxide-based transistors described herein) may be present. In general, RF transceiver 970 may be used to receive and transmit wireless data and calls according to a given wireless communication protocol such as 3 G or 4G wireless communication protocol such as in accordance with a code division multiple access (CDMA), global system for mobile communication (GSM), long term evolution (LTE) or other protocol. In addition a GPS sensor 980 (which may include one or more switching devices such as any of the highly stable gate oxide-based transistors described herein) may be present, with location information being provided to security processor 950 for use as described herein when context information is to be used in a pairing process. Other wireless communications such as receipt or transmission of radio signals (e.g., AM/FM) and other signals may also be provided. In addition, via WLAN transceiver 975, local wireless communications, such as according to a Bluetooth™ or IEEE 802.11 standard can also be realized.

[0075] Referring now to Figure 7, shown is a block diagram of a system in accordance with another embodiment of the present invention. Multiprocessor system 1000 is a point-to-point interconnect system such as a server system, and includes a first processor 1070 (which may include one or more switching devices such as any of the highly stable gate oxide-based transistors described herein) and a second processor 1080 (which may include one or more switching devices such as any of the highly stable gate oxide-based transistors described herein) coupled via a point-to-point interconnect 1050. Each of processors 1070 and 1080 may be multicore processors such as SoCs, including first and second processor cores (i.e., processor cores l074a and l074b and processor cores l084a and l084b), although potentially many more cores may be present in the processors. In addition, processors 1070 and 1080 each may include a secure engine 1075 and 1085 to perform security operations such as attestations, IoT network onboarding or so forth.

[0076] First processor 1070 further includes a memory controller hub (MCH) 1072 and point-to-point (P-P) interfaces 1076 and 1078. Similarly, second processor 1080 includes a MCH 1082 and P-P interfaces 1086 and 1088. MCH’s 1072 and 1082 couple the processors to respective memories, namely a memory 1032 (which may include one or more switching devices such as any of the highly stable gate oxide-based transistors described herein) and a memory 1034 (which may include one or more switching devices such as any of the highly stable gate oxide-based transistors described herein), which may be portions of main memory (e.g., a DRAM) locally attached to the respective processors. First processor 1070 and second processor 1080 may be coupled to a chipset 1090 (which may include one or more switching devices such as any of the highly stable gate oxide-based transistors described herein) via P-P interconnects 1052 and 1054, respectively. Chipset 1090 includes P-P interfaces 1094 and 1098.

[0077] Furthermore, chipset 1090 includes an interface 1092 to couple chipset 1090 with a high performance graphics engine 1038, by a P-P interconnect 1039. In turn, chipset 1090 may be coupled to a first bus 1016 via an interface 1096. Various input/output (I/O) devices 1014 may be coupled to first bus 1016, along with a bus bridge 1018 which couples first bus 1016 to a second bus 1020. Various devices may be coupled to second bus 1020 including, for example, a keyboard/mouse 1022, communication devices 1026 and a data storage unit 1028 (which may include one or more switching devices such as any of the highly stable gate oxide-based transistors described herein) such as a non-volatile storage or other mass storage device. As seen, data storage unit 1028 may include code 1030, in one embodiment. As further seen, data storage unit 1028 also includes a trusted storage 1029 to store sensitive information to be protected. Further, an audio I/O 1024 may be coupled to second bus 1020.

[0078] Embodiments may be used in environments where IoT devices may include wearable devices or other small form factor Internet of Things (IoT) devices. Referring now to Figure 8, shown is a block diagram of a wearable module 1300 in accordance with another embodiment. In one particular implementation, module 1300 may be an Intel® Curie™ module that includes multiple components adapted within a single small module that can be implemented as all or part of a wearable device. As seen, module 1300 includes a core 1310 (of course in other embodiments more than one core may be present) (which may include one or more switching devices such as any of the highly stable gate oxide-based transistors described herein). Such core may be a relatively low complexity in-order core, such as based on an Intel Architecture® Quark™ design. In some embodiments, core 1310 may implement a Trusted Execution Environment (TEE). Core 1310 couples to various components including a sensor hub 1320, which may be configured to interact with a plurality of sensors 1380 (which may include one or more switching devices such as any of the highly stable gate oxide-based transistors described herein), such as one or more biometric, motion environmental or other sensors. A power delivery circuit 1330 (which may include one or more switching devices such as any of the highly stable gate oxide-based transistors described herein) is present, along with a non-volatile storage 1340 (which may include one or more switching devices such as any of the highly stable gate oxide-based transistors described herein). In an embodiment, this circuit may include a rechargeable battery and a recharging circuit, which may in one embodiment receive charging power wirelessly. One or more input/output (IO) interfaces 1350, such as one or more interfaces compatible with one or more of ETSB/SPI/I2C/GPIO protocols, may be present. In addition, a wireless transceiver 1390, which may be a Bluetooth™ low energy or other short-range wireless transceiver is present to enable wireless communications as described herein. ETnderstand that in different implementations a wearable module can take many other forms. Wearable and/or IoT devices have, in comparison with a typical general purpose CPU or a GPU, a small form factor, low power requirements, limited instruction sets, relatively slow computation throughput, or any of the above.

[0079] The following examples pertain to further embodiments.

[0080] Example 1 includes a device comprising: a channel including a member selected from the group consisting of germanium, a group III-V material, or combinations thereof; a first gate dielectric layer, comprising a first oxide, on the channel; a second gate dielectric layer, comprising a second oxide, on the first gate dielectric layer; and a gate on the second dielectric layer; wherein at least one of the first and second oxides includes a material selected from the group consisting of a Group 3B element, a lanthanide element, or combinations thereof.

[0081] Example 1 includes two different layers. In an embodiment there can be intermixing at the interface of the two layers. This intermixing occurs because to form distinct layers, the deposition tool will turn off one gas that forms one oxide and will turn on the second gas to form the second layer. There could be an intermixing of elements at the oxide interface that extends a distance of 1 nm or so.

[0082] Layers such as the first and second layers described above may be identified using, for example, elemental analysis like XPS, EDX, or TEM to show that there is a local maximum where the defining element (e.g., Al for Al ₂ 0 ₃ , or Hf for Hf0 ₂ ) has a peak that is more dominant than any other oxides bordering that oxide. As an example, if oxide layer one (like layer 205) is a gadolinium oxide (Gd ₂ 0 ₃ ) and oxide layer two is a Zr0 ₂ (like layer 206), then elementary analysis that scans through the oxide layers will reveal a dominant peak of Gd in the first oxide and a Zr peak in the second oxide. There can be some intermixing but the naming element for the oxide is dominant. Thus, while Figures 1-4 are abstract in the real world the divisions between layers may be less distinct than is drawn in those figures.

[0083] Example 2 includes the device of example 1 wherein the first oxide includes oxygen bonded to the material.

[0084] Example 3 includes the device of example 2 wherein the first oxide includes silicon bonded to the material. [0085] Example 4 includes the device of example 2 wherein the second oxide does not include the material.

[0086] Example 5 includes the device of example 1 wherein the second oxide includes oxygen bonded to the material.

[0087] Example 6 includes the device of example 5 wherein the first oxide does not include the material.

[0088] Example 7 includes the device of example 1 wherein: the first oxide includes oxygen bonded to the material; and the second oxide includes oxygen bonded to an additional material selected from the group consisting of a Group 3B element, a lanthanide element, or combinations thereof.

[0089] Example 8 includes the device of example 7 wherein the first oxide includes silicon bonded to the material.

[0090] Example 9 includes the device of example 1 wherein both of the first and second oxides are disposed on at least two sides of the channel.

[0091] Example 10 includes the device of example 1, wherein (a) the channel region is comprised of at least one of a nanowire and a nanoribbon, and (b) both of the first and second oxides are disposed on four sides of the channel.

[0092] Example 11 includes the device of example 1 wherein the first oxide directly contacts both the channel and the second oxide.

[0093] Example 12 includes the device of example 1 wherein the channel includes a group III-V material.

[0094] Example 13 includes the device of example 1 wherein a majority of the first oxide has a first dielectric constant and a majority of the second oxide has a second dielectric constant that is greater than the first dielectric constant.

[0095] Example 14 includes the device of example 1 wherein the at least one of the first and second oxides includes a graded amount of the material. [0096] Example 15 includes the device of example 1 wherein (a) the at least one of the first and second oxides includes a first portion having a first percentage composition of the material and a second portion having a second percentage composition of the material that is greater than the first percentage, and (b) the first portion is directly between the channel and the second portion.

[0097] Example 16 includes a transistor comprising: a channel including a III-V material; a first gate oxide on the channel; a second gate oxide on the first gate oxide; and a gate on the second dielectric layer; wherein at least one of the first and second gate oxides includes oxygen bonded to a material selected from the group consisting of cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), scandium (Sc), yttrium (Y), lanthanum (La), or combinations thereof; wherein the first gate oxide directly contacts both the channel and the second gate oxide.

[0098] Example 17 includes the transistor of example 16 wherein the first gate oxide includes the material.

[0099] Example 18 includes the transistor of example 16 wherein the second gate oxide includes the material.

[0100] Example 19 includes the transistor of example 16 wherein: the first gate oxide includes the material; and the second gate oxide includes oxygen bonded to an additional material selected from the group consisting of cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), scandium (Sc), yttrium (Y), lanthanum (La), or combinations thereof.

[0101] Example 20 includes the transistor of example 19 wherein the first gate oxide includes silicon bonded to the material.

[0102] Example 21 includes the transistor of example 16 wherein: a plane is orthogonal to a long axis of the channel; and both of the first and second gate oxides completely surround the channel within the plane. [0103] Example 22 includes the device of example 21 wherein (a) the at least one of the first and second gate oxides includes a first portion having a first percentage composition of the material and a second portion having a second percentage composition of the material that is greater than the first percentage, and (b) the first portion is directly between the channel and the second portion.

[0104] Example 23 includes a system comprising: a memory; and a processor coupled to the memory, wherein at least one of the processor and the memory includes a device according to any one of examples 1 to 22.

[0105] Example 24 includes a method comprising: forming a trench within at least one of a dielectric layer and a substrate; forming a fin with within the trench; forming a channel on the fin, the channel including a member selected from the group consisting of germanium, a group III-V material, or combinations thereof; forming a first gate oxide on the channel and a second gate oxide on the first gate oxide, wherein at least one of the first and second gate oxides includes oxygen bonded to a material selected from the group consisting of cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), scandium (Sc), yttrium (Y), lanthanum (La), or combinations thereof; and forming a gate on the second gate oxide.

[0106] Example 25 includes the method of example 24 comprising bonding silicon to the material.

[0107] Example 26 includes a device comprising: a channel including a member selected from the group consisting of germanium, a group III-V material, or combinations thereof; a first gate oxide on the channel; a second gate oxide on the first gate oxide; and a gate on the second dielectric layer; wherein at least one of the first and second gate oxides includes oxygen bonded to praseodymium (Pr).

[0108] Example 27 includes a device comprising: a channel including a member selected from the group consisting of germanium, a group III-V material, or combinations thereof; a first gate oxide on the channel; a second gate oxide on the first gate oxide; and a gate on the second dielectric layer; wherein at least one of the first and second gate oxides includes oxygen bonded to neodymium (Nd). [0109] Example 28 includes a device comprising: a channel including a member selected from the group consisting of germanium, a group III-V material, or combinations thereof; a first gate oxide on the channel; a second gate oxide on the first gate oxide; and a gate on the second dielectric layer; wherein at least one of the first and second gate oxides includes oxygen bonded to promethium (Pm).

[0110] Example 29 includes a device comprising: a channel including a member selected from the group consisting of germanium, a group III-V material, or combinations thereof; a first gate oxide on the channel; a second gate oxide on the first gate oxide; and a gate on the second dielectric layer; wherein at least one of the first and second gate oxides includes oxygen bonded to samarium (Sm).

[0111] Example 30 includes a device comprising: a channel including a member selected from the group consisting of germanium, a group III-V material, or combinations thereof; a first gate oxide on the channel; a second gate oxide on the first gate oxide; and a gate on the second dielectric layer; wherein at least one of the first and second gate oxides includes oxygen bonded to europium (Eu).

[0112] Example 31 includes a device comprising: a channel including a member selected from the group consisting of germanium, a group III-V material, or combinations thereof; a first gate oxide on the channel; a second gate oxide on the first gate oxide; and a gate on the second dielectric layer; wherein at least one of the first and second gate oxides includes oxygen bonded to gadolinium (Gd).

[0113] Example 32 includes a device comprising: a channel including a member selected from the group consisting of germanium, a group III-V material, or combinations thereof; a first gate oxide on the channel; a second gate oxide on the first gate oxide; and a gate on the second dielectric layer; wherein at least one of the first and second gate oxides includes oxygen bonded to terbium (Tb).

[0114] Example 33 includes a device comprising: a channel including a member selected from the group consisting of germanium, a group III-V material, or combinations thereof; a first gate oxide on the channel; a second gate oxide on the first gate oxide; and a gate on the second dielectric layer; wherein at least one of the first and second gate oxides includes oxygen bonded to dysprosium (Dy). [0115] Example 34 includes a device comprising: a channel including a member selected from the group consisting of germanium, a group III-V material, or combinations thereof; a first gate oxide on the channel; a second gate oxide on the first gate oxide; and a gate on the second dielectric layer; wherein at least one of the first and second gate oxides includes oxygen bonded to holmium (Ho).

[0116] Example 35 includes a device comprising: a channel including a member selected from the group consisting of germanium, a group III-V material, or combinations thereof; a first gate oxide on the channel; a second gate oxide on the first gate oxide; and a gate on the second dielectric layer; wherein at least one of the first and second gate oxides includes oxygen bonded to erbium (Er).

[0117] Example 36 includes a device comprising: a channel including a member selected from the group consisting of germanium, a group III-V material, or combinations thereof; a first gate oxide on the channel; a second gate oxide on the first gate oxide; and a gate on the second dielectric layer; wherein at least one of the first and second gate oxides includes oxygen bonded to thulium (Tm).

[0118] Example 37 includes a device comprising: a channel including a member selected from the group consisting of germanium, a group III-V material, or combinations thereof; a first gate oxide on the channel; a second gate oxide on the first gate oxide; and a gate on the second dielectric layer; wherein at least one of the first and second gate oxides includes oxygen bonded to ytterbium (Yb).

[0119] Example 38 includes a device comprising: a channel including a member selected from the group consisting of germanium, a group III-V material, or combinations thereof; a first gate oxide on the channel; a second gate oxide on the first gate oxide; and a gate on the second dielectric layer; wherein at least one of the first and second gate oxides includes oxygen bonded to lutetium (Lu).

[0120] Example 39 includes a device comprising: a channel including a member selected from the group consisting of germanium, a group III-V material, or combinations thereof; a first gate oxide on the channel; a second gate oxide on the first gate oxide; and a gate on the second dielectric layer; wherein at least one of the first and second gate oxides includes oxygen bonded to scandium (Sc). [0121] Example 40 includes a device comprising: a channel including a member selected from the group consisting of germanium, a group III-V material, or combinations thereof; a first gate oxide on the channel; a second gate oxide on the first gate oxide; and a gate on the second dielectric layer; wherein at least one of the first and second gate oxides includes oxygen bonded to yttrium (Y).

[0122] Example 41 includes a device comprising: a channel including a member selected from the group consisting of germanium, a group III-V material, or combinations thereof; a first gate oxide on the channel; a second gate oxide on the first gate oxide; and a gate on the second dielectric layer; wherein at least one of the first and second gate oxides includes oxygen bonded to lanthanum (La).

[0123] Example 42 includes a device comprising: a channel including a member selected from the group consisting of germanium, a group III-V material, or combinations thereof; a first gate oxide on the channel; a second gate oxide on the first gate oxide; and a gate on the second dielectric layer; wherein at least one of the first and second gate oxides includes oxygen bonded to cerium (Ce).

[0124] Example 43 includes a device comprising: a channel including a member selected from the group consisting of germanium, a group III-V material, or combinations thereof; a first gate dielectric layer, comprising a first oxide, on the channel; a second gate dielectric layer, comprising a second oxide, on the first gate dielectric layer; and a gate on the second dielectric layer; wherein the first oxide includes means for a dielectric constant below 15; wherein the second oxide includes means for a dielectric constant above 15, wherein at least one of the first and second oxides includes a material selected from the group consisting of a Group 3B element, a lanthanide element, or combinations thereof.

[0125] Example 44 includes a device comprising: a channel including a member selected from the group consisting of germanium, a group III-V material, or combinations thereof; a first gate dielectric, comprising a first oxide, on the channel; a second gate dielectric, comprising a second oxide, on the first gate dielectric; and a gate on the second dielectric; wherein at least one of the first and second oxides includes a material selected from the group consisting of a Group 3B element, a lanthanide element, or combinations thereof. [0126] Example 45 includes the apparatus according to any of examples 1-8 wherein both of the first and second oxides are disposed on at least two sides of the channel.

[0127] Example 46 includes the apparatus according to any of examples 1-8 wherein (a) the channel region is comprised of at least one of a nanowire and a nanoribbon, and (b) both of the first and second oxides are disposed on four sides of the channel.

[0128] Example 47 includes the apparatus according to any of examples 1-8 and 45-46 wherein the first oxide directly contacts both the channel and the second oxide.

[0129] Example 48 includes the apparatus according to any of examples 1-8 and 45-47 wherein the channel includes a group III-V material.

[0130] Example 49 includes the apparatus according to any of examples 1-8 and 45-48 wherein a majority of the first oxide has a first dielectric constant and a majority of the second oxide has a second dielectric constant that is greater than the first dielectric constant.

[0131] Example 50 includes the apparatus according to any of examples 1-8 and 45-49 wherein the at least one of the first and second oxides includes a graded amount of the material.

[0132] Example 51 includes the apparatus according to any of examples 1-8 and 45-48 wherein (a) the at least one of the first and second oxides includes a first portion having a first percentage composition of the material and a second portion having a second percentage composition of the material that is greater than the first percentage, and (b) the first portion is directly between the channel and the second portion.

[0133] Example 52 includes a package comprising: a package substrate; a first die on the package substrate; a second die on the package substrate; wherein the first die includes a device comprising (a)(i) a channel including a member selected from the group consisting of germanium, a group III-V material, or combinations thereof; (a)(ii) a first gate dielectric layer, comprising a first oxide, on the channel; (a)(iii) a second gate dielectric layer, comprising a second oxide, on the first gate dielectric layer; and (a)(iv) a gate on the second dielectric layer; wherein at least one of the first and second oxides includes a material selected from the group consisting of a Group 3B element, a lanthanide element, or combinations thereof. [0134] Example 52 includes the package of example 52 comprising at least one of (a) a stiffener coupled to the first die, and (b) a heat spreader coupled to the first die.

[0135] Example la includes a device comprising: a channel including at least one of germanium, a group III-V material, and combinations thereof; a first gate dielectric layer, comprising a first oxide, on the channel; a second gate dielectric layer, comprising a second oxide, on the first gate dielectric layer; and a gate on the second dielectric layer; wherein at least one of the first and second oxides includes a material, the material comprising at least one of a Group 3B element, a lanthanide element, and combinations thereof.

[0136] Example 2a includes the device of claim la wherein the first oxide includes: (a) the material, and (b) oxygen bonded to the material.

[0137] Example 3a includes the device of claim 2a wherein the first oxide includes silicon bonded to the material.

[0138] Example 4a includes the device of claim 2a wherein the second oxide does not include the material.

[0139] Example 5a includes the device of claim la wherein the second oxide includes: (a) the material, and (b) oxygen bonded to the material.

[0140] Example 6a includes the device of claim 5a wherein the first oxide does not include the material.

[0141] Example 7a includes the device of claim la wherein: the first oxide includes: (a) the material, and (b) oxygen bonded to the material; and the second oxide includes (a) an additional material, and (b) oxygen bonded to the additional material; the additional material comprises at least one of a Group 3B element, a lanthanide element, and combinations thereof.

[0142] Example 8a includes the device of claim 7a wherein the first oxide includes silicon bonded to the material.

[0143] Example 9a includes the device of claim la wherein: the first oxide is disposed on at least two sides of the channel; the second oxide is disposed on the at least two sides of the channel. [0144] Example lOa includes the device of claim la, wherein: (a) the channel region is included in at least one of a nanowire and a nanoribbon, and (b) both of the first and second oxides are disposed on four sides of the channel.

[0145] Example l la includes the device of claim la wherein the first oxide directly contacts both the channel and the second oxide.

[0146] Example l2a includes the device of claim la wherein the channel includes a group III-V material.

[0147] Example l3a includes the device of claim la wherein: a majority of the first oxide has a first dielectric constant; a majority of the second oxide has a second dielectric constant; the second dielectric constant is greater than the first dielectric constant.

[0148] Example l4a includes the device of claim la wherein the at least one of the first and second oxides includes a graded amount of the material.

[0149] Example l5a includes the device of claim la wherein: the at least one of the first and second oxides includes a first portion having a first percentage composition of the material and a second portion having a second percentage composition of the material; the second percentage composition is greater than the first percentage composition; the first portion is directly between the channel and the second portion.

[0150] Example l6a includes a transistor comprising: a channel including a III-V material; a first gate oxide on the channel; a second gate oxide on the first gate oxide; and a gate on the second dielectric layer; wherein at least one of the first and second gate oxides includes: (a) a material, and (b) oxygen; wherein the material comprises at least one of: cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), scandium (Sc), yttrium (Y), lanthanum (La), and combinations thereof; wherein the first gate oxide directly contacts both the channel and the second gate oxide.

[0151] Example l7a includes the transistor of claim l6a wherein the first gate oxide includes the material. [0152] Example l8a includes the transistor of claim l6a wherein the second gate oxide includes the material.

[0153] Example l9a includes the transistor of claim l6a wherein: the first gate oxide includes the material; and the second gate oxide includes: (a) an additional material, and (b) oxygen; the additional material includes at least one of Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Sc, Y, La, or combinations thereof.

[0154] Example 20a includes the transistor of claim l9a wherein the first gate oxide includes silicon.

[0155] Example 2la includes the transistor of claim l6a wherein: a plane is orthogonal to a long axis of the channel; and both of the first and second gate oxides completely surround the channel within the plane.

[0156] Example 22a includes the device of claim 2la wherein: the at least one of the first and second gate oxides includes a first portion having a first percentage composition of the material and a second portion having a second percentage composition of the material; the second percentage composition is greater than the first percentage composition; and the first portion is directly between the channel and the second portion.

[0157] Example 23a includes a system comprising: a memory; and a processor coupled to the memory, wherein at least one of the processor and the memory includes a device according to any one of claims la to 22a.

[0158] Example 24a includes a package comprising: a package substrate; a first die on the package substrate; a second die on the package substrate; wherein the first die includes a device comprising: (a) a channel including a III-V material; (b) a first gate oxide on the channel; (c) a second gate oxide on the first gate oxide; and (d) a gate on the second dielectric layer; wherein at least one of the first and second gate oxides includes: (a) a material, and (b) oxygen bonded to the material; wherein the material comprises at least one of: cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), scandium (Sc), yttrium (Y), lanthanum (La), or combinations thereof. [0159] Example 25a includes the package of claim 24a comprising at least one of (a) a stiffener coupled to the first die, and (b) a heat spreader coupled to the first die.

[0160] Example lb includes a device comprising: a channel including at least one of germanium, a group III-V material, and combinations thereof; a first gate dielectric layer, comprising a first oxide, on the channel; a second gate dielectric layer, comprising a second oxide, on the first gate dielectric layer; and a gate on the second dielectric layer; wherein at least one of the first and second oxides includes a material, the material comprising at least one of a Group 3B element, a lanthanide element, and combinations thereof.

[0161] Another version of example lb includes a device comprising: a channel including at least one of germanium, a group III-V material, and combinations thereof; a first gate dielectric layer comprising a first oxide, the first gate dielectric layer on the channel; a second gate dielectric layer comprising a second oxide, the second gate dielectric layer on the first gate dielectric layer; and a gate on the second dielectric layer; wherein at least one of the first and second oxides includes a material, the material comprising at least one of a Group 3B element, a lanthanide element, and combinations thereof.

[0162] Another version of example lb includes a device comprising: a channel including at least one of germanium, a group III-V material, and combinations thereof; a first gate dielectric comprising a first oxide, the first gate dielectric on the channel; a second gate dielectric comprising a second oxide, the second gate dielectric on the first gate dielectric; and a gate on the second dielectric; wherein at least one of the first and second oxides includes a material, the material comprising at least one of a Group 3B element, a lanthanide element, and combinations thereof.

[0163] Thus, the gate dielectrics may not necessarily be in a layer. Examples 2b-l5b may not necessarily require the gate dielectrics of example lb be in a layer.

[0164] Example 2b includes the device of claim lb wherein the first oxide includes: (a) the material, and (b) oxygen bonded to the material.

[0165] Example 3b includes the device of claim 2b wherein the first oxide includes silicon bonded to the material. [0166] Example 4b includes the device according to any of claims lb-3b wherein the second oxide does not include the material.

[0167] Example 5b includes the device according to any of claims lb-4b wherein the second oxide includes: (a) the material, and (b) oxygen bonded to the material.

[0168] Example 6 b includes the device of claim 5b wherein the first oxide does not include the material.

[0169] Example 7 b includes the device according to any of claims lb and 3b wherein: the first oxide includes: (a) the material, and (b) oxygen bonded to the material; and the second oxide includes (a) an additional material, and (b) oxygen bonded to the additional material; the additional material comprises at least one of a Group 3B element, a lanthanide element, and combinations thereof.

[0170] Example 8 b includes the device according to any of claims lb, 3b, and 7 wherein the first oxide includes silicon bonded to the material.

[0171] Example 9 b includes the device according to any of claims lb-8b wherein: the first oxide is disposed on at least two sides of the channel; the second oxide is disposed on the at least two sides of the channel.

[0172] Example 10 b includes the device according to any of claims lb-9b, wherein: (a) the channel region is included in at least one of a nanowire and a nanoribbon, and (b) both of the first and second oxides are disposed on four sides of the channel.

[0173] Example 11 b includes the device according to any of claims lb-lOb wherein the first oxide directly contacts both the channel and the second oxide.

[0174] Example 12 b includes the device according to any of claims lb-l lb wherein the channel includes a group III-V material.

[0175] Example 13 b includes the device according to any of claims lb-l2b wherein: a majority of the first oxide has a first dielectric constant; a majority of the second oxide has a second dielectric constant; the second dielectric constant is greater than the first dielectric constant. [0176] Example 14 b includes the device according to any of claims lb-l3b wherein the at least one of the first and second oxides includes a graded amount of the material.

[0177] Example 15 b includes the device according to any of claims lb-l4b wherein: the at least one of the first and second oxides includes a first portion having a first percentage composition of the material and a second portion having a second percentage composition of the material; the second percentage composition is greater than the first percentage composition; the first portion is directly between the channel and the second portion.

[0178] Example 16 b includes a transistor comprising: a channel including a III-V material; a first gate oxide on the channel; a second gate oxide on the first gate oxide; and a gate on the second dielectric layer; wherein at least one of the first and second gate oxides includes: (a) a material, and (b) oxygen; wherein the material comprises at least one of: cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), scandium (Sc), yttrium (Y), lanthanum (La), and combinations thereof; wherein the first gate oxide directly contacts both the channel and the second gate oxide.

[0179] Example 17 b includes the transistor of claim l6b wherein the first gate oxide includes the material.

[0180] Example 18 b includes the transistor according to any of claims l6b-l7b wherein the second gate oxide includes the material.

[0181] Example 19 b includes the transistor of claim l6b wherein: the first gate oxide includes the material; and the second gate oxide includes: (a) an additional material, and (b) oxygen; the additional material includes at least one of Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Sc, Y, La, or combinations thereof.

[0182] Example 20 b includes the transistor according to any of claims l6b-l9b wherein the first gate oxide includes silicon.

[0183] Example 21 b includes the transistor according to any of claims l6b-20b wherein: a plane is orthogonal to a long axis of the channel; and both of the first and second gate oxides completely surround the channel within the plane. [0184] Example 22 b includes the device according to any of claims l6b-2lb wherein: the at least one of the first and second gate oxides includes a first portion having a first percentage composition of the material and a second portion having a second percentage composition of the material; the second percentage composition is greater than the first percentage composition; and the first portion is directly between the channel and the second portion.

[0185] Example 23 b includes a system comprising: a memory; and a processor coupled to the memory, wherein at least one of the processor and the memory includes a device according to any one of claims lb to 22b.

[0186] Example 24 b includes a package comprising: a package substrate; a first die on the package substrate; a second die on the package substrate; wherein the first die includes a device comprising: (a) a channel including a III-V material; (b) a first gate oxide on the channel; (c) a second gate oxide on the first gate oxide; and (d) a gate on the second dielectric layer; wherein at least one of the first and second gate oxides includes: (a) a material, and (b) oxygen bonded to the material; wherein the material comprises at least one of: cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), scandium (Sc), yttrium (Y), lanthanum (La), or combinations thereof.

[0187] Example 25 b includes the package of claim 24b comprising at least one of (a) a stiffener coupled to the first die, and (b) a heat spreader coupled to the first die.

[0188] The foregoing description of the embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. This description and the claims following include terms, such as left, right, top, bottom, over, under, upper, lower, first, second, etc. that are used for descriptive purposes only and are not to be construed as limiting. For example, terms designating relative vertical position refer to a situation where a device side (or active surface) of a substrate or integrated circuit is the "top" surface of that substrate; the substrate may actually be in any orientation so that a "top" side of a substrate may be lower than the "bottom" side in a standard terrestrial frame of reference and still fall within the meaning of the term "top." The term "on" as used herein (including in the claims) does not indicate that a first layer "on" a second layer is directly on and in immediate contact with the second layer unless such is specifically stated; there may be a third layer or other structure between the first layer and the second layer on the first layer. The embodiments of a device or article described herein can be manufactured, used, or shipped in a number of positions and orientations. Persons skilled in the relevant art can appreciate that many modifications and variations are possible in light of the above teaching. Persons skilled in the art will recognize various equivalent combinations and substitutions for various components shown in the Figures. It is therefore intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.