Title:
MEMORY CONTROL CIRCUIT AND CACHE MEMORY
Document Type and Number:
WIPO Patent Application WO/2015/034082
Kind Code:
A1
Abstract:
[Problem] To quickly respond to an access request. [Solution] A memory control circuit is provided with a local buffer (5) for reading, in response to a read request to a specific address of a cache memory (1), data that has an address different from the specific address from the cache memory address and for storing the same, and a control unit for controlling access to the cache memory and the local buffer. The local buffer has a smaller storage capacity than the cache memory and can be accessed at a high speed, and duplicatively stores a portion of data stored in the cache memory.
Inventors:
NOGUCHI HIROKI (JP)
FUJITA SHINOBU (JP)
FUJITA SHINOBU (JP)
Application Number:
PCT/JP2014/073634
Publication Date:
March 12, 2015
Filing Date:
September 08, 2014
Export Citation:
Assignee:
TOSHIBA KK (JP)
International Classes:
G06F12/08; G11C11/15
Foreign References:
| JP2005084999A | 2005-03-31 | |||
| JP2001101075A | 2001-04-13 | |||
| JPH11167520A | 1999-06-22 | |||
| JP2001331793A | 2001-11-30 | |||
| JP2002163150A | 2002-06-07 | |||
| JP2011192345A | 2011-09-29 | |||
| JP2012203487A | 2012-10-22 |
Attorney, Agent or Firm:
KATSUNUMA Hirohito et al. (JP)
Katsunuma Hirohito (JP)
Katsunuma Hirohito (JP)
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