Title:
MEMORY CONTROLLER AND MEMORY CONTROL METHOD
Document Type and Number:
WIPO Patent Application WO/2023/171474
Kind Code:
A1
Abstract:
A memory controller according to an embodiment of the present disclosure is capable of controlling access to a DRAM. The memory controller comprises an RAA counter capable of counting the number of issuances of an ACT command and a command scheduler. The command scheduler is capable of changing tRRD, tFAW, or t32AW to a longer value when the count of the RAA counter exceeds a first threshold value, and resetting the changed value back to the original value when the count of the RAA counter falls below a second threshold value smaller than the first threshold value.
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Inventors:
IKARASHI TAKAHIRO (JP)
Application Number:
PCT/JP2023/007482
Publication Date:
September 14, 2023
Filing Date:
March 01, 2023
Export Citation:
Assignee:
SONY SEMICONDUCTOR SOLUTIONS CORP (JP)
International Classes:
G06F12/00; G11C11/406
Foreign References:
| JPH0319052A | 1991-01-28 | |||
| JP2007199841A | 2007-08-09 | |||
| JP2002189628A | 2002-07-05 | |||
| JP2015133119A | 2015-07-23 | |||
| JP2018081642A | 2018-05-24 | |||
| US20220068361A1 | 2022-03-03 |
Attorney, Agent or Firm:
TSUBASA PATENT PROFESSIONAL CORPORATION (JP)
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