Title:
MEMORY CONTROLLER, NONVOLATILE MEMORY, NONVOLATILE MEMORY SYSTEM, AND NONVOLATILE MEMORY ADDRESS MANAGEMENT METHOD
Document Type and Number:
WIPO Patent Application WO/2007/013372
Kind Code:
A1
Abstract:
For address management of a nonvolatile memory, the whole logical address space is divided into logical address ranges (0 to 15), and the physical address space is divided into physical areas (segments (0 to 15)). The logical address ranges are respectively associated with the physical areas (segments) to manage the addresses. The sizes of the logical address ranges are equalized. The size of the physical area (segment (0)) corresponding to the logical address range (0) in which data of high rewrite frequency such as an FAT is expected to be stored is larger than those of the other physical areas, and the logical address ranges and the physical areas are allocated. Alternatively, the sizes of the physical areas are equalized, and the size of the logical address range (0) is set as a smaller one than those of the other logical address ranges. With this, the actual rewrite frequencies of the physical areas (segments) are equal to one another, and consequently the life of the nonvolatile memory can be prolonged.
Inventors:
NAKANISHI MASAHIRO
KASAHARA TETSUSHI
IZUMI TOMOAKI
MATSUNO KIMINORI
KUNIMUNE DAISUKE
TAMURA KAZUAKI
KONISHI YOSHIYUKI
KASAHARA TETSUSHI
IZUMI TOMOAKI
MATSUNO KIMINORI
KUNIMUNE DAISUKE
TAMURA KAZUAKI
KONISHI YOSHIYUKI
Application Number:
PCT/JP2006/314496
Publication Date:
February 01, 2007
Filing Date:
July 21, 2006
Export Citation:
Assignee:
MATSUSHITA ELECTRIC IND CO LTD (JP)
NAKANISHI MASAHIRO
KASAHARA TETSUSHI
IZUMI TOMOAKI
MATSUNO KIMINORI
KUNIMUNE DAISUKE
TAMURA KAZUAKI
KONISHI YOSHIYUKI
NAKANISHI MASAHIRO
KASAHARA TETSUSHI
IZUMI TOMOAKI
MATSUNO KIMINORI
KUNIMUNE DAISUKE
TAMURA KAZUAKI
KONISHI YOSHIYUKI
International Classes:
G06F12/02; G06F12/00
Domestic Patent References:
| WO2004053888A2 | 2004-06-24 | |||
| WO2004040586A1 | 2004-05-13 | |||
| WO2004040455A2 | 2004-05-13 | |||
| WO2004040586A1 | 2004-05-13 |
Foreign References:
| JP2005107600A | 2005-04-21 | |||
| JP2006209608A | 2006-08-10 | |||
| JP2004326165A | 2004-11-18 | |||
| JP2003323352A | 2003-11-14 | |||
| US6611907B1 | 2003-08-26 |
Other References:
See also references of EP 1912123A4
Attorney, Agent or Firm:
KAWAMIYA, Osamu et al. (IMP Building 3-7, Shiromi 1-chome, Chuo-ku, Osaka-sh, Osaka 01, JP)
Download PDF:
Previous Patent: SCAN TUNNEL SPECTRAL METHOD AND SCAN TUNNEL MICROSCOPE
Next Patent: ALKALINE PRIMARY BATTERY
Next Patent: ALKALINE PRIMARY BATTERY