Title:
MEMORY CONTROLLER, MEMORY, MEMORY SYSTEM, INFORMATION PROCESSING SYSTEM, AND METHOD FOR CONTROL THEREOF
Document Type and Number:
WIPO Patent Application WO/2019/102656
Kind Code:
A1
Abstract:
An objective of the present invention is to reduce a data channel load when writing data. Provided is a memory controller comprising a specific data pattern retaining part, a comparator, and an issuing part. The specific data pattern retaining part retains a specific data pattern. The comparator compares the specific data pattern with write data relating to a write command from a host computer. If the write data matches the specific data pattern, the issuing part issues a specific write request which requests a write of the specific data pattern without supplying the write data to a memory.
Inventors:
IWAKI HIROYUKI (JP)
NAKANISHI KENICHI (JP)
NAKANISHI KENICHI (JP)
Application Number:
PCT/JP2018/029355
Publication Date:
May 31, 2019
Filing Date:
August 06, 2018
Export Citation:
Assignee:
SONY SEMICONDUCTOR SOLUTIONS CORP (JP)
International Classes:
G06F12/00; G06F12/02
Foreign References:
| US20170076768A1 | 2017-03-16 | |||
| JP2007241618A | 2007-09-20 |
Attorney, Agent or Firm:
MARUSHIMA, Toshikazu (JP)
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