MEMORY DEVICE USING SEMICONDUCTOR ELEMENT

WIPO Patent Application WO/2022/239192

A1

According to the present invention, an N+ layer 3a that is connected to a source line SL, a first Si column 2a that is a P+ layer, and a second Si column 2b that is a P layer are arranged on a substrate 1, the Si columns standing in the vertical direction. In addition, an N+ layer 3b, which is connected to a bit line BL, is arranged on the second Si column. In addition, a first gate insulating layer 4a is arranged so as to surround the first Si column 2a; and a second gate insulating layer 4b is arranged so as to surround the second Si column 2b. In addition, a first gate conductor layer 5a is arranged so as to surround the first insulating layer 4a, while being connected to a plate line PL; and a second gate conductor layer 5b is arranged so as to surround the second insulating layer 4b, while being connected to a word line WL. A data-holding operation for holding a hole group generated inside a channel region 7 by an impact ionization phenomenon or a gate-induced drain leakage current, and a data-erasing operation for removing the hole group from the inside of the channel region 7 are carried out by controlling voltages to be applied to the source line SL, the plate line PL, the word line WL and the bit line BL.

HARADA NOZOMU (JP)
SAKUI KOJI (JP)

PCT/JP2021/018236

November 17, 2022

May 13, 2021

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UNISANTIS ELECT SINGAPORE PTE (SG)
HARADA NOZOMU (JP)
SAKUI KOJI (JP)

G11C16/04; G11C11/401; H01L21/8242; H01L27/10; H01L27/108

JP2008218556A	2008-09-18
JP2006080280A	2006-03-23

TANAKA Shinichiro et al. (JP)

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