TECHNICAL FIELD

[0001] This disclosure generally relates to memory devices.

BACKGROUND

[0002] Modern electronics devices, such as non-volatile memories, may make use of various devices, for example, for the storage of bits. The memory devices can be distributed in arrays, for example, on the surface of the chip. One-bit memory cells can be grouped in small units called words which can be accessed together as a single memory address. Memory can be manufactured having a word length that is usually a power of two, such as 1, 2, 4 or 8 bits.

BRIEF DESCRIPTION OF THE FIGURES

[0003] Reference will now be made to the accompanying drawings, which are not necessarily drawn to scale, and wherein:

[0004] FIG. 1 shows a diagram of a memory device, in accordance with one or more example embodiments of the disclosure.

[0005] FIG. 2 shows an example diagram of a current voltage characteristic for device, for example, a device shown and discussed in connection with FIG. 1, in accordance with one or more example embodiments of the disclosure.

[0006] FIG. 3 shows a diagram of an example memory device, in accordance with one or more example embodiments of the disclosure.

[0007] FIG. 4 shows an example flow diagram for the fabrication of a portion of the device disclosed herein, in accordance with one or more example embodiments of the disclosure.

[0008] FIG. 5 depicts an example of a system, in accordance with one or more example embodiments of the disclosure.

DETAILED DESCRIPTION

[0009] Embodiments of the disclosure are described more fully hereinafter with reference to the accompanying drawings, in which example embodiments of the disclosure are shown. This disclosure may, however, be embodied in many different forms and should not be construed as limited to the example embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Like numbers refer to like, but not necessarily the same or identical, elements throughout.

[0010] The following embodiments are described in sufficient detail to enable at least those skilled in the art to understand and use the disclosure. It is to be understood that other embodiments would be evident based on the present disclosure and that process, mechanical, material, dimensional, process equipment, and parametric changes may be made without departing from the scope of the present disclosure.

[0011] In the following description, numerous specific details are given to provide a thorough understanding of various embodiments of the disclosure. However, it will be apparent that the disclosure may be practiced without these specific details. In order to avoid obscuring the present disclosure, some well-known system configurations and process steps may not be disclosed in full detail. Likewise, the drawings showing embodiments of the disclosure are semi-diagrammatic and not to scale and, particularly, some of the dimensions are for the clarity of presentation and may be exaggerated in the drawings. In addition, where multiple embodiments are disclosed and described as having some features in common, for clarity and ease of illustration, description, and comprehension thereof, similar and like features will ordinarily be described with like reference numerals even if the features are not identical.

[0012] The term“horizontal” as used herein may be defined as a direction parallel to a plane or surface (for example, surface of a substrate), regardless of its orientation. The term “vertical,” as used herein, may refer to a direction orthogonal to the horizontal direction as just described. Terms, such as“on,”“above,”“below,”“bottom,”“top,”� �side” (as in“sidewall”), “higher,” “lower,” “upper,” “over,” and“under,” may be referenced with respect to a horizontal plane, where the horizontal plane can include an x-y plane, a x-z plane, or a y-z plane, as the case may be. The term“processing” as used herein includes deposition of material or photoresist, patterning, exposure, development, etching, cleaning, ablating, polishing, and/or removal of the material or photoresist as required in formation a described structure.

[0013] “An embodiment,”“various embodiments,” and the like indicate embodiment(s) so described may include particular features, structures, or characteristics, but not every embodiment necessarily includes the particular features, structures, or characteristics. Some embodiments may have some, all, or none of the features described for other embodiments. “First,”“second,”“third,” and the like can describe a common object and indicate different instances of like objects are being referred to. Such adjectives do not imply objects so described must be in a given sequence, either temporally, spatially, in ranking, or in any other manner.“Connected” may indicate elements are in direct physical or electrical contact with each other and“coupled” may indicate elements co-operate or interact with each other, but they may or may not be in direct physical or electrical contact. Also, while similar or same numbers may be used to designate same or similar parts in different figures, doing so does not mean all figures including similar or same numbers constitute a single or same embodiment.

[0014] Described herein are systems, methods, and apparatuses for using negative differential resistance (NDR) materials in circuits to store memory states for memory devices. In an embodiment, such NDR materials can have a voltage dependent volatile resistance state change. In an embodiment, when a voltage that is applied to such NDR materials exceeds a given magnitude (also referred to as threshold voltage herein), the resistance of the NDR materials can become lower than the resistance of the NDR material under an applied voltage of lower magnitude than the threshold voltage. In an embodiment, when a voltage that is applied to such NDR materials is less than the threshold voltage, the resistance of the NDR materials can resemble a resistive insulator.

[0015] In an embodiment, in a device or circuit with NDR, in some part of the current- voltage (also referred to as I-V herein) curve, the current can decrease as the voltage increases. In an embodiment, the I-V curve can be non-monotonic (that is the I-V curve can have peaks and troughs) with regions of negative slope representing negative differential resistance. In an embodiment, such NDR devices can be classified as N-type NDR (NNDR) devices and S-type NDR (SNDR) devices.

[0016] In an embodiment, NNDR devices can represent voltage controlled negative resistance devices. In such devices the current can represent a single valued, continuous function of the voltage, but the voltage can be a multivalued function of the current. In an embodiment, the I-V curve of such a device can be shaped generally like the letter "N". In an embodiment, as the voltage on the device is increased, the current increases (positive resistance) until it reaches a maximum, then decreases in the region of negative resistance to a minimum, then increases again. In an embodiment, some example devices with this type of negative resistance include the tunnel diode, resonant tunneling diode, lambda diode, Gunn diode, and dynatron oscillators. In an embodiment, SNDR devices can represent current controlled negative resistance devices. In such devices, the voltage can be a single valued function of the current, but the current can be a multivalued function of the voltage. In an embodiment, the I-V curve of such devices can be shaped generally like the letter "S". Devices with this type of negative resistance include a threshold switch, an IMP ATT diode, UJT, SCRs, thyristors, and the like.

[0017] In an embodiment, materials that can display such NDR behavior and can be used in connection with the disclosure include, but are not necessarily limited to, niobium dioxide NbCT, tantalum oxides TaOx (x from 1 to 2.3), vanadium(IV) oxide VO2, nickel (II) oxide NiO, and chalcogenides (for example, Si-Te-As-Ge tetrachalcogenides and the like). In an embodiment, chalcogenides can refer to compound consisting of at least one chalcogen anion and at least one more electropositive element.

[0018] In an embodiment, the memory devices described herein can include a circuit including both an SNDR and an NDDR device. In an embodiment, an SNDR device or an NNDR device used herein can include a device having a general structure of a first electrode (for example, a metal or a doped semiconductor), an SNDR or NNDR material, and a second electrode (for example, a metal or a doped semiconductor).

[0019] In an embodiment, the circuit can further include a transistor connected to a wordline at the gate of the transistor and a transistor connected to a bitline at either the source or the drain of the transistor. In an embodiment, the transistor can further be electronically connected to both the NNDR and the SNDR device at another of the source or the drain of the transistor. In an embodiment, the circuit can be configured such that the NNDR device can be connected to a voltage source (also referred to as Vdd or Vcc herein). In another embodiment the SNDR device can be connected to one terminal or electrode of the NNDR device and have another terminal or electrode of the SNDR device that is grounded.

[0020] In an embodiment, the circuit can be configured to store different memory states (“0” or“1”) based on different on-off states of the SNDR and NNDR devices. In an embodiment, the circuit can be configured to turn on the SNDR device by placing the SNDR device in a low resistance state (LRS) when writing a“1” on a bitline, while placing the NNDR device in a high resistance state (HRS). Such a configuration can be referred to as an Sl state herein. In another embodiment, for example, when reading from the memory device, the circuit can be configured to turn off the SNDR device by placing the SNDR device in a LRS, while placing the NNDR device in a LRS, thereby turning the NNDR device on. Such a configuration can be referred to as an SO state herein.

[0021] In an embodiment, the transistor used in connection with the circuit described herein can be a transistor fabricated using back-end-of-line (BEOL) or front-end-of-line (FEOL) techniques. In an embodiment, such a BEOL transistor can include a channel that includes zinc oxide ZnO, indium oxides InOx, indium tin oxides ITO, aluminum zinc oxides AZO, indium zinc oxides IZO, indium gallium zinc oxides IGZO, gallium zinc oxides GZO, tin oxides SnO, cobalt oxides CoO, copper oxides CuO and/or Cu ₂ 0, titanium oxide TiOx, and the like. In an embodiment, the use of BEOL or FEOL transistors in connection with the circuits described herein can lead to memory devices that are more dense than memory devices without such transistors.

[0022] In an embodiment, the circuit described herein can be configured such that the transistor saturation current can hold either the NNDR or the SNDR device in an on-state while the transistor leaks little current. In an embodiment, this can be because the NNDR and/or the SNDR devices can have a relatively low threshold voltage.

[0023] In an embodiment, the circuit described herein, which can be used as at least a portion of a memory element in a memory device can have improved scalability in comparison with other memory devices, for example, memory devices using capacitors. In an embodiment, devices the area of a memory device using the circuit described herein can have memory element reduction of approximately ten times with respect to memory devices using several (for example, six) silicon frontend transistors devices.

[0024] FIG. 1 shows a diagram of a memory device 100, in accordance with one or more example embodiments of the disclosure. In one embodiment, the device 100 can include an N- type Negative Differential Resistance (NNDR) element 102. In an embodiment, the NNDR element 102 can include a two-terminal device. In an embodiment, the NNDR element 102 can include a first electrode. In one embodiment, the NNDR element 102 can include a NNDR material. In one embodiment, the NNDR element 102 can include a second electrode.

[0025] In an embodiment, the NNDR material used for the NNDR element 102 can include, but are not necessarily limited to, niobium dioxide Nb0 ₂ , tantalum oxides TaOx (x from 1 to 2.3), vanadium(IV) oxide V0 ₂ , nickel (II) oxide NiO, and chalcogenides (for example, Si-Te-As-Ge tetrachalcogenides and the like). In an embodiment, chalcogenides can refer to compound consisting of at least one chalcogen anion and at least one more electropositive element.

[0026] In an embodiment, the first electrode and second electrode can include a conductive material. In an embodiment, the conductive materials used for the first electrode and second electrode can include, but are not limited to, metals, for example, copper, tungsten, tantalum, titanium, hafnium, zirconium, aluminum, silver, tin, lead, metal alloys, metal carbides, for example, hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, aluminum carbide, other conductive materials, or any combination thereof, and the like. In an embodiment, the first electrode and second electrode can include a metallic, semi-metallic, or intermetallic material. In various embodiments, the first electrode and second electrode can comprise a metallic material. Non-limiting examples include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the first electrode and second electrode can comprise a semi-metallic material. Non-limiting examples include arsenic, antimony, bismuth, a-tin (gray tin) and graphite, and mercury telluride (HgTe). Semi-metallic materials may also be any mixtures of such materials. In various embodiments, the first electrode and second electrode can comprise an intermetallic material. Non-limiting examples include gold and aluminum intermetallic s, copper and tin intermetallics, tin and nickel intermetallics, tin and silver intermetallic s, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the first electrode and second electrode may be deposited by any suitable mechanism including, but not limited to, PVD, CVD, MOCVD, metal foil lamination, sputtering, metal paste deposition, combinations thereof, or the like.

[0027] In another embodiment, the device 100 can include an S-type Negative Differential Resistance (SNDR) element 104. In an embodiment, the SNDR element 104 can include a two-terminal device. In an embodiment, the SNDR element 104 can include a first electrode. In one embodiment, the SNDR element 104 can include an SNDR material. In one embodiment, the SNDR element 102 can include a second electrode.

[0028] In an embodiment, the SNDR material used for the SNDR element 104 can include, but are not necessarily limited to, niobium dioxide NbCk, tantalum oxides TaOx (x from 1 to 2.3), vanadium(IV) oxide VO2, nickel (II) oxide NiO, and chalcogenides (for example, Si-Te- As-Ge tetrachalcogenides and the like). In an embodiment, chalcogenides can refer to compound consisting of at least one chalcogen anion and at least one more electropositive element.

[0029] In an embodiment, the first electrode and second electrode can include a conductive material. In an embodiment, the conductive materials used for the first electrode and second electrode can include, but are not limited to, metals, for example, copper, tungsten, tantalum, titanium, hafnium, zirconium, aluminum, silver, tin, lead, metal alloys, metal carbides, for example, hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, aluminum carbide, other conductive materials, or any combination thereof, and the like. In an embodiment, the first electrode and second electrode can include a metallic, semi-metallic, or intermetallic material. In various embodiments, the first electrode and second electrode can comprise a metallic material. Non-limiting examples include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the first electrode and second electrode can comprise a semi-metallic material. Non-limiting examples include arsenic, antimony, bismuth, a-tin (gray tin) and graphite, and mercury telluride (HgTe). Semi-metallic materials may also be any mixtures of such materials. In various embodiments, the first electrode and second electrode can comprise an intermetallic material. Non-limiting examples include gold and aluminum intermetallic s, copper and tin intermetallics, tin and nickel intermetallics, tin and silver intermetallic s, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the first electrode and second electrode may be deposited by any suitable mechanism including, but not limited to, PVD, CVD, MOCVD, metal foil lamination, sputtering, metal paste deposition, combinations thereof, or the like.

[0030] In one embodiment, the device 100 can include a transistor element 106. In one embodiment, a voltage applied at a gate of the transistor element 106 can represent a wordline 108 for the memory device 100. In another embodiment, a voltage applied at a source or drain of the transistor element 106 can represent a bitline 110 of the device 100. In an embodiment, the transistor element 106 can be a transistor fabricated using back-end-of-line (BEOL) or front-end-of-line (FEOL) techniques. In an embodiment, such a BEOL transistor can include a channel that includes zinc oxide ZnO, indium oxides InOx, indium tin oxides ITO, aluminum zinc oxides AZO, indium zinc oxides IZO, indium gallium zinc oxides IGZO, gallium zinc oxides GZO, tin oxides SnO, cobalt oxides CoO, copper oxides CuO and/or Cu ₂ 0, titanium oxide TiOx, and the like. In an embodiment, the use of BEOL or FEOL transistors in connection with the circuits described herein can lead to memory devices that are more dense than memory devices without such transistors.

[0031] In an embodiment, the circuit described in connection with memory device 100 can be configured such that the transistor saturation current can hold either the NNDR element 102 or the SNDR element 104 in an on-state while the transistor 106 leaks relatively little current. In an embodiment, this can be because the NNDR element 102 and/or the SNDR element 106 can have a relatively low threshold voltage. [0032] In an embodiment, the transistor element 106 can include a substrate. In one embodiment, the substrate can refer to a solid (usually planar) substance onto which a layer of another substance is applied, and to which that second substance adheres. In another embodiment, the substrate can include a silicon substrate. In one embodiment, the substrate can include a doped silicon substrate. In one embodiment, the substrate can be a thin slice of material such as silicon, silicon oxide, silicon dioxide, aluminum oxide, sapphire, an alloy of silicon and germanium, and/or indium phosphide (InP), and the like. In one embodiment, the substrate can include a semiconductor material (e.g., monocrystalline silicon, germanium, silicon germanium, SiGe, and/or a III-V materials based material (e.g., gallium arsenide, GaAs), or any combination thereof).

[0033] In an embodiment, the substrate can include a flexible substrate. In various embodiments, substrate can include a polymer based substrate, glass, or any other bendable substrate including 2D materials e.g., graphene and M0S2, organic materials e.g., pentacene, transparent oxides e.g., indium gallium zinc oxide (IGZO), polycrystalline III-V materials, polycrystalline Ge, polycrystalline Si, amorphous III-V materials, amorphous Ge, amorphous Si, or any combination thereof. In an embodiment, the amorphous III-V materials can have a deposition temperature lower than that of the poly crystalline III-V materials. In an embodiment, substrate can be, for example, an organic, a ceramic, a glass, or a semiconductor substrate. In one embodiment, substrate comprises a semiconductor material, e.g., silicon (Si). In one embodiment, substrate is a monocrystalline Si substrate.

[0034] In one embodiment, the substrate, for example, a silicon wafer can include a memory array periphery devices, for example, input/output devices. In an embodiment, placing the memory array periphery devices under the substrate can increase the memory array efficiency while reducing the memory array area consumption. In an embodiment, the substrate can include electronic devices, for example, transistors, memories, capacitors, resistors, optoelectronic devices, switches, any other active and passive electronic devices that are separated by electrically insulating layers, for example, interlayer dielectric layers, trench insulation layers, or any other insulating layers known to one of ordinary skill in the art of the electronic device manufacturing. In at least some embodiments, the substrate can include metal interconnects and vias configured to connect the metallization layers. In an embodiment, substrate can be a semiconductor-on-isolator (SOI) substrate including a bulk lower substrate, a middle insulation layer, and a top monocrystalline layer. The top monocrystalline layer may comprise, for example, silicon. [0035] In another embodiment, the transistor element can include a channel. In one embodiment, both the substrate and the channel can be silicon based. In an embodiment, the channel can represent an area of the transistor between the source and the drain, where charges (for example, electrons or holes) can flow under the application of an electric field, for example, through a gate and/or gate dielectric, to be discussed further below.

[0036] In one embodiment, the transistor element 106 can include a gate dielectric. In one embodiment, the gate dielectric can include a dielectric material. In another embodiment, the gate dielectric can include silicon oxide. In another embodiment, the gate dielectric can include a high-K dielectric material. In another embodiment, the high-K material, for example, hafnium oxide, tantalum oxide, titanium oxide, aluminum oxide, silicon dioxide, silicon nitride and the like. In one embodiment, an electroglass (EG) can be used as the gate dielectric. In one embodiment, the gate dielectric can include hexagonal boron nitride (HBN). In one embodiment, the gate material can be deposited using PVD, CVD, and/or ALD, and the like. In one embodiment, the gate dielectric can have a thickness of approximately 1 nm to approximately 10 nm, with an example thickness of approximately 2 nm to approximately 4 nm.

[0037] In one embodiment, the transistor element 106 can include a gate. In another embodiment, the gate can include a metal. In another embodiment, the gate can include a transition metal. In one embodiment, the gate can be used to tune the threshold voltage of the device. In one embodiment, gate can include titanium nitride, cobalt, tungsten and/or platinum. In one embodiment, the gate can be deposited using PVD, CVD, MOCVD, MBE and/or ALD, and the like. In one embodiment, the gate can have a thickness of approximately 30 nm to approximately 100 nm, with an example thickness of approximately 40 nm to approximately 60 nm.

[0038] In one embodiment, the transistor element 106 can include contacts. In an embodiment, the contacts can include a conductive material. In an embodiment, the conductive materials used for the contacts can include, but are not limited to, metals, for example, copper, tungsten, tantalum, titanium, hafnium, zirconium, aluminum, silver, tin, lead, metal alloys, metal carbides, for example, hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, aluminum carbide, other conductive materials, or any combination thereof, and the like. In an embodiment, the contacts can comprise a metallic, semi-metallic, or intermetallic material. In various embodiments, the contacts can comprise a metallic material. Non-limiting examples include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the contacts can comprise a semi-metallic material. Non-limiting examples include arsenic, antimony, bismuth, a-tin (gray tin) and graphite, and mercury telluride (HgTe). Semi-metallic materials may also be any mixtures of such materials. In various embodiments, the can comprise an intermetallic material. Non-limiting examples include gold and aluminum intermetallics, copper and tin intermetallics, tin and nickel intermetallics, tin and silver intermetallic s, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the contacts may be deposited by any suitable mechanism including, but not limited to, PVD, CVD, MOCVD, metal foil lamination, sputtering, metal paste deposition, combinations thereof, or the like.

[0039] In another embodiment, the transistor element 106 can include spacers. In an embodiment, the spacers can serve to provide electrical insulation between the gate and the source and/or the drain. In one embodiment, the spacers can include an insulator, for example, silicon oxide or silicon nitride. The spacer can be serve to prevent the source and/or drain from making electrical contact to the gate. In an embodiment, the spacers can be deposited using PVD, CVD, MOCVD, MBE, and/or ALD, and the like.

[0040] In one embodiment, the device can have a voltage applied at one end of the NNDR 102. In an embodiment, the voltage VCC 122 (UPDATE FIGURE) can be applied at one terminal of the NNDR. In another embodiment, the SNDR 104 can be grounded at ground 114. In one embodiment, the bitline 110 can have an applied voltage 116. In another embodiment, the bitline 110 can be grounded at ground 118. In one embodiment, the wordline 108 can be connected to a voltage source 120.

[0041] In one embodiment, the device 100 can be configured such that the NNDR 102 and the SNDR 104 element store different memory states in the device 100. In an embodiment, using the transistor 106, the device can turn the SNDR 104 on when writing a“1” on the bitline 110 which makes the NNDR 102 in a high resistant state to be called Sl herein. In another embodiment, when reading a memory state from the device 100, the SNDR 104 can be turned off using the transistor 106 while the NNDR is turned on. This can represent a state“0” (SO).

[0042] In one embodiment, the NNDR material can include a resonant tunneling diode material. In another embodiment, the SNDR 104 can include a threshold switch.

[0043] In an embodiment, the device 100 can stay in the on state, that is, Sl but can leak a limited amount of current because the holding voltage for the device 100 can be relatively low. This can be similar to a capacitor device holding a charge and thus the state for the memory device. In an embodiment, depending on the voltage bias applied through the bitline 110, the NNDR 102 and the SNDR 104 can be either in a low resistance state or a high resistance state. In another embodiment, when the NNDR device 102 is in a low resistant state, the SNDR device is in a high resistant state. In an alternative embodiment when the NNDR 102 is in a high resistant state, the SNDR can be in a low resistant state. In one embodiment, the NNDR being in a low resistant state while the SNDR is in a high resistant state, can be referred to as an“SO” state. In another embodiment, when the NNDR is in a high resistant state while the SNDR is in a low resistant state, the state can be referred to as an“Sl” state.

[0044] In an example operational environment, if a voltage of approximately 1 volt is applied at VCC 122 and an approximately 0.9 voltage is applied at the bitline 110, then a middle node of the device 100, the middle node 112, can experience a voltage of approximately 0.9 volts. In an embodiment, the middle node 112 can represent a voltage node between the NNDR 102 and the SNDR 104. In this situation, the voltage drop or the voltage change across the NNDR 102 can be approximately 0.1 volts which can be relatively small and therefore lead to the NNDR 102 being turned on, that is, being in a low resistant state or a high current state. At the same time, in such a situation, the voltage drop or the voltage change across the SNDR 104 can be approximately 0.9 volts or relatively large leading to an off state for the SNDR 104, that is, a high resistance state or a low current state for the SNDR 104. This can result in the device 100 being in an SO state. In such a state, the SNDR 104 being turned off and the NNDR being turned on, the device 100 can read a charge stored on the device 100.

[0045] In another embodiment, if the voltage applied at VCC 122 is approximately 3 volts and a voltage applied at the bitline 110 is approximately 0.9 volts, then the voltage drop or change across the NNDR 102, that is, the voltage at middle node 112 can be approximately 2.1 volts which can be relatively large and lead to a high resistant state in the NNDR 102 and therefore a low current state in the NNDR 102 and cause the NNDR 102 to be off. At the same time, in such a situation, the drop in voltage across the SNDR 104, that is, the voltage at middle node 112 can be approximately 0.9 volts which is relatively small and can cause the SNDR 104 to have a low resistant state, that is, a high current state and therefore be turned on. In such a situation where the NNDR is in a high resistant state and the SNDR 104 is in a low resistant state, the device 100 can be in a Sl state. Accordingly, the device can write a 1 on the bitline and store a 1 in the device in state 1. [0046] FIG. 2 shows an example diagram 200 of a current voltage characteristic for device, for example, a device 100 shown and discussed in connection with FIG. 1, in accordance with one or more example embodiments of the disclosure.

[0047] In one embodiment, the diagram 200 represents a plot of the current 202 versus voltage 104 in a device such as the device 100 shown and discussed in connection with FIG. 1. In an embodiment, the diagram 200 represents the current- voltage (IV) characteristics of an SNDR device, for example, the SNDR 104 shown and discussed in connection with FIG. 1 with a load line of an NNDR device, for example, the NNDR device 102 shown and discussed in connection with FIG. 1 superimposed thereon. In one embodiment, the portion of the IV characteristic represented by sections 215, 214 and 216 represent the current voltage characteristics of the NNDR device, such as the NNDR device 102, shown in connection with FIG. 1. In another embodiment, the section of the IV curve 206 represented by 212 and 218 represent the IV characteristics of the SNDR device, for example, the SNDR 104 shown and described in connection with FIG. 1.

[0048] In one embodiment, the state 0, that is, the state where the NNDR device is turned on in a low resistant state or a high current state and the SNDR is in an off state that is in a high resistant state or a low current state can be represented by point 210 on the IV characteristics 206. In another embodiment, state 1 Sl where the NNDR device is off or in a high resistant state or in a low current state while the SNDR is on, in a low resistant state or a high current state, can be represented by point 208 on the IV characteristics 206.

[0049] In one embodiment, the voltage represented by axis 204, voltage 204 can represent the voltage applied at VCC 122 in the diagram 100 of FIG. 1. In another embodiment, current 202 can be measured at middle node 112 in device 100 of diagram 100 of FIG. 1. In one embodiment, the IV characteristics of an NNDR device such as the NNDR device 102 of FIG. 1 can have IV characteristics that are a mirror image of sections 215, 214 and 216 of IV curve 206 represented in diagram 200. In another embodiment, the IV curves for an NNDR only device in isolation can have a resistance that is positive at the beginning, that is, for a first voltage range and then experience negative differential resistance, that is, a negative resistant state for a second set of voltages applied after the first range of voltages are applied.

[0050] In an embodiment, the diagram 200 can represent the IV characteristics of a circuit that includes both an SNDR and an NDDR device. In an embodiment, an SNDR device or an NNDR device can include a device having a general structure of a first electrode (for example, a metal or a doped semiconductor), an SNDR or NNDR material, and a second electrode (for example, a metal or a doped semiconductor).

[0051] In an embodiment, the circuit can further include a transistor connected to a wordline at the gate of the transistor and a transistor connected to a bitline at either the source or the drain of the transistor. In an embodiment, the transistor can further be electronically connected to both the NNDR and the SNDR device at another of the source or the drain of the transistor. In an embodiment, the circuit can be configured such that the NNDR device can be connected to a voltage source. In another embodiment the SNDR device can be connected to one terminal or electrode of the NNDR device and have another terminal or electrode of the SNDR device that is grounded.

[0052] In an embodiment, the transistor can be a transistor fabricated using back-end-of- line (BEOL) or front-end-of-line (FEOL) techniques. In an embodiment, such a BEOL transistor can include a channel that includes zinc oxide ZnO, indium oxides InOx, indium tin oxides ITO, aluminum zinc oxides AZO, indium zinc oxides IZO, indium gallium zinc oxides IGZO, gallium zinc oxides GZO, tin oxides SnO, cobalt oxides CoO, copper oxides CuO and/or Cu ₂ 0, titanium oxide TiOx, and the like.

[0053] FIG. 3 shows a diagram 300 of an example memory device in accordance with one or more example embodiments of the disclosure. In one embodiment, the device can include an insulator 302. In one embodiment, the insulator 302 can include an interlayer dielectric (ILD) material. In another embodiment, the insulator 302 can include an oxide. In an embodiment, the insulator 302 can include a silicon dioxide (Si0 ₂ ), or a low-K material. In one embodiment, the insulator can be deposited using PVD, CVD, MOCVD, and/or ALD, and the like.

[0054] In another embodiment, the diagram can include a device portion 304 which represents both a transistor component and an NNDR and an SNDR component to be discussed below. In one embodiment, the portion of the diagram 304 can represent a memory device corresponding to the device 100 of FIG. 1 and associated discussion.

[0055] In an embodiment, the device 300 can include a substrate 310. In one embodiment, the substrate 310 can refer to a solid (usually planar) substance onto which a layer of another substance is applied, and to which that second substance adheres. In another embodiment, the substrate 310 can include a silicon substrate. In one embodiment, the substrate 310 can be a thin slice of material such as silicon, silicon oxide, silicon dioxide, aluminum oxide, sapphire, an alloy of silicon and germanium, and/or indium phosphide (InP), and the like. In one embodiment, the substrate 310 can include a semiconductor material (e.g., monocrystalline silicon, germanium, silicon germanium, SiGe, and/or a III-V materials based material (e.g., gallium arsenide, GaAs), or any combination thereof).

[0056] In an embodiment, the substrate 310 can include a flexible substrate. In various embodiments, substrate 310 can include a polymer based substrate, glass, or any other bendable substrate including 2D materials e.g., graphene and M0S2, organic materials e.g., pentacene, transparent oxides e.g., indium gallium zinc oxide (IGZO), polycrystalline III-V materials, poly crystalline Ge, poly crystalline Si, amorphous III-V materials, amorphous Ge, amorphous Si, or any combination thereof. In an embodiment, the amorphous III-V materials can have a deposition temperature lower than that of the polycrystalline III-V materials. In an embodiment, substrate 310 can be, for example, an organic, a ceramic, a glass, or a semiconductor substrate. In one embodiment, substrate 310 comprises a semiconductor material, e.g., silicon (Si). In one embodiment, substrate 310 is a monocrystalline Si substrate.

[0057] In one embodiment, the substrate 310, for example, a silicon wafer can include a memory array periphery devices, for example, input/output devices. In an embodiment, placing the memory array periphery devices under the substrate 310 can increase the memory array efficiency while reducing the memory array area consumption. In an embodiment, the substrate 310 can include electronic devices, for example, transistors, memories, capacitors, resistors, optoelectronic devices, switches, any other active and passive electronic devices that are separated by electrically insulating layers, for example, interlayer dielectric layers, trench insulation layers, or any other insulating layers known to one of ordinary skill in the art of the electronic device manufacturing. In at least some embodiments, the substrate 310 can include metal interconnects and vias configured to connect the metallization layers. In an embodiment, substrate 310 can be a semiconductor-on-isolator (SOI) substrate including a bulk lower substrate, a middle insulation layer, and a top monocrystalline layer. The top monocrystalline layer may comprise, for example, silicon.

[0058] In another embodiment, the device 300 can include a channel 312. In one embodiment, both the substrate 310 and the channel 312 can be silicon based or in another embodiment, the substrate 310 can be a semiconductor such as silicon or germanium and/or the channel 312 can be a thin film transistor material. In an embodiment, the channel 312 can represent an area of the transistor between the source and the drain, where charges (for example, electrons or holes) can flow under the application of an electric field, for example, through a gate and/or gate dielectric, to be discussed further below. [0059] In one embodiment, the device 300 can include a gate dielectric 314. In one embodiment, the gate dielectric 314 can include a dielectric material. In another embodiment, the gate dielectric 314 can include silicon oxide. In another embodiment, the gate dielectric 314 can include a high-K dielectric material. In another embodiment, the high-K material, for example, hafnium oxide, tantalum oxide, titanium oxide, aluminum oxide, silicon dioxide, silicon nitride and the like. In one embodiment, an electroglass (EG) can be used as the gate dielectric 314. In one embodiment, the gate dielectric 314 can include hexagonal boron nitride (HBN). In one embodiment, the gate material can be deposited using PVD, CVD, and/or ALD, and the like. In one embodiment, the gate dielectric 314 can have a thickness of approximately 1 nm to approximately 10 nm, with an example thickness of approximately 2 nm to approximately 4 nm.

[0060] In one embodiment, the device 300 can include a gate 316. In another embodiment, the gate 316 can include a metal. In another embodiment, the gate 316 can include a transition metal. In one embodiment, the gate 316 can be used to tune the threshold voltage of the transistor. In one embodiment, gate 316 can include titanium nitride, cobalt, tungsten and/or platinum. In one embodiment, the gate 316 can be deposited using PVD, CVD, MOCVD, MBE and/or ALD, and the like. In one embodiment, the gate 316 can have a thickness of approximately 30 nm to approximately 100 nm, with an example thickness of approximately 40 nm to approximately 60 nm.

[0061] In one embodiment, the device 300 can include an insulator 318. In one embodiment, the insulator 318 can include an interlayer dielectric (ILD) material. In another embodiment, the insulator 318 can include an oxide. In an embodiment, the insulator 318 can include a silicon dioxide (S1O2), or a low-K material. In one embodiment, the insulator 318 can be deposited using PVD, CVD, MOCVD, and/or ALD, and the like.

[0062] In another embodiment, the device 300 can include an insulator 320. In one embodiment, the insulator 320 can include an interlayer dielectric (ILD) material. In another embodiment, the insulator 320 can include an oxide. In an embodiment, the insulator 320 can include a silicon dioxide (Si0 ₂ ), or a low-K material. In one embodiment, the insulator 320 can be deposited using PVD, CVD, MOCVD, and/or ALD, and the like.

[0063] In one embodiment, the device 300 can include contacts 322. In an embodiment, the contacts 322 can include a conductive material. In an embodiment, the conductive materials used for the contacts 322 can include, but are not limited to, metals, for example, copper, tungsten, tantalum, titanium, hafnium, zirconium, aluminum, silver, tin, lead, metal alloys, metal carbides, for example, hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, aluminum carbide, other conductive materials, or any combination thereof, and the like. In various embodiments, the various contacts 322 can comprise a metallic, semi-metallic, or intermetallic material. In various embodiments, the contacts 322 can comprise a metallic material. Non-limiting examples include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the contacts 322 can comprise a semi-metallic material. Non-limiting examples include arsenic, antimony, bismuth, a-tin (gray tin) and graphite, and mercury telluride (HgTe). Semi-metallic materials may also be any mixtures of such materials. In various embodiments, the contacts 322 can comprise an intermetallic material. Non-limiting examples include gold and aluminum intermetallics, copper and tin intermetallics, tin and nickel intermetallic s, tin and silver intermetallics, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the contacts 322 may be deposited by any suitable mechanism including, but not limited to, metal foil lamination, physical vapor deposition, chemical vapor deposition, sputtering, metal paste deposition, combinations thereof, or the like.

[0064] In another embodiment, the device 300 can include spacers 324. In an embodiment, the spacers 324 can serve to provide electrical insulation between the gate and the source and/or the drain. In one embodiment, the spacers 324 can include silicon oxide or silicon nitride. The spacers 324 can serve to prevent the source and/or drain from making electrical contact to the gate. In an embodiment, the spacers 324 can be deposited using PVD, CVD, MOCVD, MBE, and/or ALD, and the like.

[0065] In one embodiment, the device 300 can include a contact 330. In another embodiment, the contact 330 can connect the transistor device to an NNDR and an SNDR element. In an embodiment, the contacts 330 can include a conductive material. In an embodiment, the conductive materials used for the contacts 330 can include, but are not limited to, metals, for example, copper, tungsten, tantalum, titanium, hafnium, zirconium, aluminum, silver, tin, lead, metal alloys, metal carbides, for example, hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, aluminum carbide, other conductive materials, or any combination thereof, and the like. In various embodiments, the various contact 330 can comprise a metallic, semi-metallic, or intermetallic material. In various embodiments, the contact 330 can comprise a metallic material. Non- limiting examples include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the contact 330 can comprise a semi-metallic material. Non-limiting examples include arsenic, antimony, bismuth, a-tin (gray tin) and graphite, and mercury telluride (HgTe). Semi-metallic materials may also be any mixtures of such materials. In various embodiments, the contact 330 can comprise an intermetallic material. Non-limiting examples include gold and aluminum intermetallics, copper and tin intermetallic s, tin and nickel intermetallics, tin and silver intermetallics, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the contact 330 may be deposited by any suitable mechanism including, but not limited to, metal foil lamination, physical vapor deposition, chemical vapor deposition, sputtering, metal paste deposition, combinations thereof, or the like.

[0066] In one embodiment, the device 300 can include an electrode 332. In an embodiment, the electrode 332 can include a conductive material. In an embodiment, the conductive materials used for the electrode 332 can include, but are not limited to, metals, for example, copper, tungsten, tantalum, titanium, hafnium, zirconium, aluminum, silver, tin, lead, metal alloys, metal carbides, for example, hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, aluminum carbide, other conductive materials, or any combination thereof, and the like. In various embodiments, the electrode 332 can comprise a metallic, semi- metallic, or intermetallic material. In various embodiments, the electrode 332 can comprise a metallic material. Non-limiting examples include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the electrode 332 can comprise a semi-metallic material. Non-limiting examples include arsenic, antimony, bismuth, a-tin (gray tin) and graphite, and mercury telluride (HgTe). Semi-metallic materials may also be any mixtures of such materials. In various embodiments, the electrode 332 can comprise an intermetallic material. Non-limiting examples include gold and aluminum intermetallics, copper and tin intermetallics, tin and nickel intermetallics, tin and silver intermetallics, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the electrode 332 may be deposited by any suitable mechanism including, but not limited to, metal foil lamination, physical vapor deposition, chemical vapor deposition, sputtering, metal paste deposition, combinations thereof, or the like.

[0067] In another embodiment, the device 300 can include an SNDR material 334. In an embodiment, the SNDR material 334 can include, but is not necessarily limited to, niobium dioxide NbCk, tantalum oxides TaOx (x from 1 to 2.3), vanadium(IV) oxide VO2, nickel (II) oxide NiO, and chalcogenides (for example, Si-Te-As-Ge tetrachalcogenides and the like). In an embodiment, chalcogenides can refer to compound consisting of at least one chalcogen anion and at least one more electropositive element. In an embodiment, the SNDR material 334 can have a thickness of approximately 0.2 nm to approximately 80 nm, with an example thickness of approximately 1 nm to approximately 20 nm. In an embodiment, the SNDR material 334 can be deposited using physical vapor deposition, chemical vapor deposition, sputtering, atomic layer deposition, combinations thereof, or the like.

[0068] In one embodiment, the device 300 can include an NNDR material 336. In an embodiment, the NNDR material 336 can include, but is not necessarily limited to, niobium dioxide NbCh, tantalum oxides TaOx (x from 1 to 2.3), vanadium(IV) oxide VO2, nickel (II) oxide NiO, and chalcogenides (for example, Si-Te-As-Ge tetrachalcogenides and the like). In an embodiment, chalcogenides can refer to compound consisting of at least one chalcogen anion and at least one more electropositive element. In an embodiment, the NNDR material 336 can have a thickness of approximately 0.2 nm to approximately 80 nm, with an example thickness of approximately 1 nm to approximately 20 nm. In an embodiment, the NNDR material 336 can be deposited using physical vapor deposition, chemical vapor deposition, sputtering, atomic layer deposition, combinations thereof, or the like.

[0069] In one embodiment, the device 300 can include an electrode 338. In another embodiment, the electrode 338 can serve as a ground connection. In an embodiment, the electrode 338 can include a conductive material. In an embodiment, the conductive materials used for the electrode 338 can include, hut are not limited to, metals, for example, copper, tungsten, tantalum, titanium, hafnium, zirconium, aluminum, silver, tin, lead, metal alloys, metal carbides, for example, hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, aluminum carbide, other conductive materials, or any combination thereof, and the like. In various embodiments, the electrode 338 can comprise a metallic, semi-metallic, or intermetallic material. In various embodiments, the electrode 338 can comprise a metallic material. Non-limiting examples include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the electrode 338 can comprise a semi-metallic material. Non-limiting examples include arsenic, antimony, bismuth, a-tin (gray tin) and graphite, and mercury telluride (HgTe). Semi-metallic materials may also be any mixtures of such materials. In various embodiments, the electrode 338 can comprise an intermetallic material. Non-limiting examples include gold and aluminum intermetallics, copper and tin intermetallics, tin and nickel intermetallics, tin and silver intermetallics, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the contacts electrode 338 may be deposited by any suitable mechanism including, but not limited to, metal foil lamination, physical vapor deposition, chemical vapor deposition, sputtering, metal paste deposition, combinations thereof, or the like.

[0070] In one embodiment, the device 300 can include an electrode 340. In another embodiment, the device 300 can include an electrode 340 that can be connected to a voltage source. In an embodiment, the electrode 340 can include a conductive material. In an embodiment, the conductive materials used for the electrode 340 can include, but are not limited to, metals, for example, copper, tungsten, tantalum, titanium, hafnium, zirconium, aluminum, silver, tin, lead, metal alloys, metal carbides, for example, hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, aluminum carbide, other conductive materials, or any combination thereof, and the like. In various embodiments, the electrode 340 can comprise a metallic, semi-metallic, or intermetallic material. In various embodiments, the electrode 340 can comprise a metallic material. Non-limiting examples include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the electrode 340 can comprise a semi- metallic material. Non-limiting examples include arsenic, antimony, bismuth, a-tin (gray tin) and graphite, and mercury telluride (HgTe). Semi-metallic materials may also be any mixtures of such materials. In various embodiments, the electrode 340 can comprise an intermetallic material. Non-limiting examples include gold and aluminum intermetallics, copper and tin intermetallics, tin and nickel intermetallics, tin and silver intermetallics, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the electrode 340 may be deposited by any suitable mechanism including, but not limited to, metal foil lamination, physical vapor deposition, chemical vapor deposition, sputtering, metal paste deposition, combinations thereof, or the like.

[0071] In one embodiment, the gate 316 can serve as a wordline for the device 300. In another embodiment, an input to the device can exist at the contact 322 where the charge can flow through the transistor and the data be stored at the output node represented by 330. In an embodiment, once the transistor is in an on state then the input and the output node, that is, input 322 and output 330 can have the same voltage that corresponds to the middle node 112 of FIG. 1. In one embodiment, memory can be written when the transistor is in an on state and memory can be read when the transistor is in an off state. [0072] FIG. 4 shows an example flow diagram for the fabrication of a portion of the device disclosed herein in accordance with one or more example embodiments of the disclosure.

[0073] At block 402, a bottom electrode can be deposited. In an embodiment, the bottom electrode can correspondent to the bottom electrode 332 shown and described in connection with FIG. 3. In an embodiment, the bottom electrode can include a conductive material. In an embodiment, the conductive materials used for the bottom electrode can include, but are not limited to, metals, for example, copper, tungsten, tantalum, titanium, hafnium, zirconium, aluminum, silver, tin, lead, metal alloys, metal carbides, for example, hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, aluminum carbide, other conductive materials, or any combination thereof, and the like. In various embodiments, the bottom electrode can comprise a metallic, semi-metallic, or intermetallic material. In various embodiments, the bottom electrode can comprise a metallic material. Non-limiting examples include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the bottom electrode can comprise a semi-metallic material. Non-limiting examples include arsenic, antimony, bismuth, a-tin (gray tin) and graphite, and mercury telluride (HgTe). Semi-metallic materials may also be any mixtures of such materials. In various embodiments, the bottom electrode can comprise an intermetallic material. Non-limiting examples include gold and aluminum intermetallics, copper and tin intermetallics, tin and nickel intermetallic s, tin and silver intermetallics, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the bottom electrode may be deposited by any suitable mechanism including, but not limited to, metal foil lamination, physical vapor deposition, chemical vapor deposition, sputtering, metal paste deposition, combinations thereof, or the like.

[0074] At block 404, an NNDR material can be deposited on the bottom electrode. In an embodiment, the NNDR material can be represented by the NNDR material 336 shown and discussed in connection with FIG. 3. In an embodiment, the NNDR material can include, but is not necessarily limited to, niobium dioxide Nb0 ₂ , tantalum oxides TaOx (x from 1 to 2.3), vanadium(IV) oxide V0 ₂ , nickel (II) oxide NiO, and chalcogenides (for example, Si-Te-As- Ge tetrachalcogenides and the like). In an embodiment, chalcogenides can refer to compound consisting of at least one chalcogen anion and at least one more electropositive element. In an embodiment, the NNDR material can have a thickness of approximately 0.2 nm to approximately 80 nm, with an example thickness of approximately 1 nm to approximately 20 nm. In an embodiment, the NNDR material can be deposited using physical vapor deposition, chemical vapor deposition, sputtering, atomic layer deposition, combinations thereof, or the like.

[0075] At block 406, an SNDR material can be deposited on a bottom electrode. In another embodiment, the SNDR material can be represented by SNDR material 334 shown and described in connection with FIG. 3. In an embodiment, the SNDR material can include, but is not necessarily limited to, niobium dioxide NbCk, tantalum oxides TaOx (x from 1 to 2.3), vanadium(IV) oxide VO2, nickel (II) oxide NiO, and chalcogenides (for example, Si-Te-As- Ge tetrachalcogenides and the like). In an embodiment, chalcogenides can refer to compound consisting of at least one chalcogen anion and at least one more electropositive element. In an embodiment, the SNDR material can have a thickness of approximately 0.2 nm to approximately 80 nm, with an example thickness of approximately 1 nm to approximately 20 nm. In an embodiment, the SNDR material can be deposited using physical vapor deposition, chemical vapor deposition, sputtering, atomic layer deposition, combinations thereof, or the like.

[0076] At block 408, a top electrode can be deposited on the NNDR material. In one embodiment, the top electrode on the NNDR material can be represented by top electrode 340 shown and described in connection with FIG. 3. In an embodiment, the top electrode can include a conductive material. In an embodiment, the conductive materials used for the top electrode can include, but are not limited to, metals, for example, copper, tungsten, tantalum, titanium, hafnium, zirconium, aluminum, silver, tin, lead, metal alloys, metal carbides, for example, hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, aluminum carbide, other conductive materials, or any combination thereof, and the like. In various embodiments, the top electrode can comprise a metallic, semi-metallic, or intermetallic material. In various embodiments, the top electrode can comprise a metallic, semi-metallic, or intermetallic material. In various embodiments, the top electrode can comprise a metallic material. Non-limiting examples include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the top electrode can comprise a semi-metallic material. Non- limiting examples include arsenic, antimony, bismuth, a-tin (gray tin) and graphite, and mercury telluride (HgTe). Semi-metallic materials may also be any mixtures of such materials. In various embodiments, the top electrode can comprise an intermetallic material. Non-limiting examples include gold and aluminum intermetallics, copper and tin intermetallics, tin and nickel intermetallics, tin and silver intermetallics, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the top electrode may be deposited by any suitable mechanism including, but not limited to, metal foil lamination, physical vapor deposition, chemical vapor deposition, sputtering, metal paste deposition, combinations thereof, or the like.

[0077] At block 410, a top electrode can be deposited on the SNDR material. In another embodiment, the top electrode on the SNDR material can be represented by the top electrode 338 shown and described in connection with FIG. 3. In an embodiment, the top electrode can include a conductive material. In an embodiment, the conductive materials used for the top electrode can include, but are not limited to, metals, for example, copper, tungsten, tantalum, titanium, hafnium, zirconium, aluminum, silver, tin, lead, metal alloys, metal carbides, for example, hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, aluminum carbide, other conductive materials, or any combination thereof, and the like. In various embodiments, the top electrode can comprise a metallic, semi-metallic, or intermetallic material. In various embodiments, the top electrode can comprise a metallic material. Non limiting examples include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the top electrode can comprise a semi-metallic material. Non-limiting examples include arsenic, antimony, bismuth, a-tin (gray tin) and graphite, and mercury telluride (HgTe). Semi-metallic materials may also be any mixtures of such materials. In various embodiments, the top electrode can comprise an intermetallic material. Non-limiting examples include gold and aluminum intermetallics, copper and tin intermetallics, tin and nickel intermetallics, tin and silver intermetallics, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the top electrode may be deposited by any suitable mechanism including, but not limited to, metal foil lamination, physical vapor deposition, chemical vapor deposition, sputtering, metal paste deposition, combinations thereof, or the like.

[0078] At block 412, the bottom electrode can be electronically coupled to the output of a driving transistor. In another embodiment, the output of the driving transistor can be represented by the output 330 shown and described in connection with FIG. 3.

[0079] In an embodiment, the circuit fabricated by the system and method shown and described in connection with FIGs. 3 and 4 can be configured to store different memory states (“0” or“1”) based on different on-off states of the SNDR and NNDR devices. In an embodiment, the circuit can be configured to turn on the SNDR device by placing the SNDR device in a low resistance state (LRS) when writing a“1” on a bitline, while placing the NNDR device in a high resistance state (HRS). Such a configuration can be referred to as an Sl state herein. In another embodiment, for example, when reading from the memory device, the circuit can be configured to turn off the SNDR device by placing the SNDR device in a LRS, while placing the NNDR device in a LRS, thereby turning the NNDR device on. Such a configuration can be referred to as an SO state herein.

[0080] In an embodiment, the transistor used in connection with the circuit described herein can be a transistor fabricated using back-end-of-line (BEOL) or front-end-of-line (FEOL) techniques. In an embodiment, such a BEOL transistor can include a channel that includes zinc oxide ZnO, indium oxides InOx, indium tin oxides ITO, aluminum zinc oxides AZO, indium zinc oxides IZO, indium gallium zinc oxides IGZO, gallium zinc oxides GZO, tin oxides SnO, cobalt oxides CoO, copper oxides CuO and/or Cu ₂ 0, titanium oxide TiOx, and the like. In an embodiment, the use of BEOL or FEOL transistors in connection with the circuits described herein can lead to memory devices that are more dense than memory devices without such transistors.

[0081] In an embodiment, the circuit can be configured such that the transistor saturation current can hold either the NNDR or the SNDR device in an on-state while the transistor leaks little current. In an embodiment, this can be because the NNDR and/or the SNDR devices can have a relatively low threshold voltage.

[0082] FIG. 5 depicts an example of a system 500 according to one or more embodiments of the disclosure. In an embodiment, system 500 can include the various transistors and NDR devices and circuits described herein. In one embodiment, system 500 includes, but is not limited to, a desktop computer, a laptop computer, a netbook, a tablet, a notebook computer, a personal digital assistant (PDA), a server, a workstation, a cellular telephone, a mobile computing device, a smart phone, an Internet appliance or any other type of computing device. In some embodiments, system 500 can include a system on a chip (SOC) system.

[0083] In one embodiment, system 500 includes multiple processors including processor 510 and processor N 505, where processor N 505 has logic similar or identical to the logic of processor 510. In one embodiment, processor 510 has one or more processing cores (represented here by processing core 1 512 and processing core N 512N, where 512N represents the Nth processor core inside processor 510, where N is a positive integer). More processing cores can be present (but not depicted in the diagram of FIG. 5). In some embodiments, processing core 512 includes, but is not limited to, pre-fetch logic to fetch instructions, decode logic to decode the instructions, execution logic to execute instructions, a combination thereof, or the like. In some embodiments, processor 510 has a cache memory

516 to cache instructions and/or data for system 500. Cache memory 516 may be organized into a hierarchical structure including one or more levels of cache memory.

[0084] In some embodiments, processor 510 includes a memory controller (MC) 514, which is configured to perform functions that enable the processor 510 to access and communicate with memory 530 that includes a volatile memory 532 and/or a non-volatile memory 534. In some embodiments, processor 510 can be coupled with memory 530 and chipset 520. Processor 510 may also be coupled to a wireless antenna 578 to communicate with any device configured to transmit and/or receive wireless signals. In one embodiment, the wireless antenna antenna 578 operates in accordance with, but is not limited to, the IEEE 802.11 standard and its related family, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.

[0085] In some embodiments, volatile memory 532 includes, but is not limited to, Synchronous Dynamic Random Access Memory (SDRAM), Dynamic Random Access Memory (DRAM), RAMBUS Dynamic Random Access Memory (RDRAM), and/or any other type of random access memory device. Non-volatile memory 534 includes, but is not limited to, flash memory, phase change memory (PCM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), or any other type of non volatile memory device.

[0086] Memory device 530 stores information and instructions to be executed by processor 510. In one embodiment, memory 530 may also store temporary variables or other intermediate information while processor 510 is executing instructions. In the illustrated embodiment, chipset 520 connects with processor 510 via Point-to-Point (PtP or P-P) interface

517 and P-P interface 522. Chipset 520 enables processor 510 to connect to other elements in system 500. In some embodiments of the disclosure, P-P interface 517 and P-P interface 522 can operate in accordance with a PtP communication protocol, such as the Intel® QuickPath Interconnect (QPI) or the like. In other embodiments, a different interconnect may be used.

[0087] In some embodiments, chipset 520 can be configured to communicate with processor 510, the processor N 505, display device 540, and other devices 572, 576, 574, 560, 562, 564, 566, 577, etc. Chipset 520 may also be coupled to the wireless antenna 578 to communicate with any device configured to transmit and/or receive wireless signals. [0088] Chipset 520 connects to display device 540 via interface 526. Display 540 may be, for example, a liquid crystal display (LCD), a plasma display, cathode ray tube (CRT) display, or any other form of visual display device. In some embodiments of the disclosure, processor 510 and chipset 520 are integrated into a single SOC. In addition, chipset 520 connects to bus 550 and/or bus 555 that interconnect various elements 574, 560, 562, 564, and 566. Bus 550 and bus 555 may be interconnected via a bus bridge 572. In one embodiment, chipset 520 couples with a non-volatile memory 560, a mass storage device(s) 562, a keyboard/mouse 564, and a network interface 566 via interface 524 and/or 504, smart TV 576, consumer electronics 577, etc.

[0089] In one embodiment, mass storage device(s) 552 can include, but not be limited to, a solid state drive, a hard disk drive, a universal serial bus flash memory drive, or any other form of computer data storage medium. In one embodiment, network interface 566 is implemented by any type of well-known network interface standard including, but not limited to, an Ethernet interface, a universal serial bus (USB) interface, a Peripheral Component Interconnect (PCI) Express interface, a wireless interface and/or any other suitable type of interface. In one embodiment, the wireless interface operates in accordance with, but is not limited to, the IEEE 802.11 standard and its related family, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.

[0090] While the modules shown in FIG. 5 are depicted as separate blocks within the system 500, the functions performed by some of these blocks may be integrated within a single semiconductor circuit or may be implemented using two or more separate integrated circuits. For example, although cache memory 516 is depicted as a separate block within processor 510, cache memory 516 or selected elements thereof can be incorporated into processor core 512.

[0091] It is noted that the system 500 described herein may include any suitable type of microelectronics packaging and configurations thereof, including, for example, system in a package (SiP), system on a package (SOP), package on package (PoP), interposer package, 3D stacked package, etc. Further, any suitable type of microelectronic components may be provided in the semiconductor packages, as described herein. For example, microcontrollers, microprocessors, baseband processors, digital signal processors, memory dies, field gate arrays, logic gate dies, passive component dies, MEMSs, surface mount devices, application specific integrated circuits, baseband processors, amplifiers, filters, combinations thereof, or the like may be packaged in the semiconductor packages, as disclosed herein. The semiconductor devices (for example, the semiconductor devices described in connection with any of FIGS. 1-4), as disclosed herein, may be provided in any variety of electronic device including consumer, industrial, military, communications, infrastructural, and/or other electronic devices.

[0092] In various embodiments, the devices, as described herein, may be used in connection with one or more processors. The one or more processors may include, without limitation, a central processing unit (CPU), a digital signal processor(s) (DSP), a reduced instruction set computer (RISC), a complex instruction set computer (CISC), a microprocessor, a microcontroller, a field programmable gate array (FPGA), or any combination thereof. The processors may also include one or more application specific integrated circuits (ASICs) or application specific standard products (ASSPs) for handling specific data processing functions or tasks. In certain embodiments, the processors may be based on an Intel® Architecture system and the one or more processors and any chipset included in an electronic device may be from a family of Intel® processors and chipsets, such as the Intel® Atom® processor(s) family or Intel-64 processors (for example, Sandy Bridge®, Ivy Bridge®, Haswell®, Broadwell®, Skylake®, etc.).

[0093] Additionally or alternatively, the devices, as described herein, may be used in connection with one or more additional memory chips. The memory may include one or more volatile and/or non-volatile memory devices including, but not limited to, magnetic storage devices, read-only memory (ROM), random access memory (RAM), dynamic RAM (DRAM), static RAM (SRAM), synchronous dynamic RAM (SDRAM), double data rate (DDR) SDRAM (DDR-SDRAM), RAM-BUS DRAM (RDRAM), flash memory devices, electrically erasable programmable read-only memory (EEPROM), non-volatile RAM (NVRAM), universal serial bus (USB) removable memory, or combinations thereof.

[0094] In example embodiments, the electronic device in which the disclosed devices are used and/or provided may be a computing device. Such a computing device may house one or more boards on which the devices may be disposed. The board may include a number of components including, but not limited to, a processor and/or at least one communication chip. The processor may be physically and electrically connected to the board through, for example, electrical connections of the devices. The computing device may further include a plurality of communication chips. For instance, a first communication chip may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth, and a second communication chip may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, and others. In various example embodiments, the computing device may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, combinations thereof, or the like. In further example embodiments, the computing device may be any other electronic device that processes data.

[0095] Example 1 , may include a memory element, comprising: a first electrode; a first material on a first portion of the first electrode, the first material having a negative differential resistance (NDR); a second material on a second portion of the first electrode, the second material having a NDR; a second electrode on the first material; and a third electrode on the second material.

[0096] Example 2 may include the memory element of example 1 and/or some other example herein, wherein the first material is an N-type NDR (NNDR) material.

[0097] Example 3 may include the memory element of example 2 and/or some other example herein, wherein the NNDR material comprises a resonant tunneling diode material.

[0098] Example 4 may include the memory element of example 1 and/or some other example herein, wherein the second material is an S-type NDR (SNDR) material.

[0099] Example 5 may include the memory element of example 3 and/or some other example herein, wherein the SNDR material comprises a threshold switch material.

[00100] Example 6 may include the memory element of example 1 and/or some other example herein, wherein the first material comprises one or more of niobium and oxygen, tantalum and oxygen, vanadium and oxygen, nickel and oxygen, or a chalcogenide.

[00101] Example 7 may include the memory element of example 1 and/or some other example herein, wherein the second material comprises one or more of niobium and oxygen, tantalum and oxygen, vanadium and oxygen, nickel and oxygen, or a chalcogenide.

[00102] Example 8, may include a memory device, comprising: a transistor comprising: a source, a drain, a channel, a gate, and a gate dielectric; a first contact on the source; a second contact on the drain; the gate in contact with the gate dielectric; and the gate dielectric in contact with the channel; a memory element comprising: a first electrode; a first material on a first portion of the first electrode, the first material having a negative differential resistance (NDR); a second material on a second portion of the first electrode, the second material having a NDR; a second electrode on the first material; and a third electrode on the second material; a third contact electrically connecting the second contact with the first electrode. [00103] Example 9 may include the memory device of example 8 and/or some other example herein, wherein the memory device includes a substrate, the substrate comprising silicon, silicon germanium, or germanium.

[00104] Example 10 may include the memory device of example 8 and/or some other example herein, wherein the channel comprises silicon, silicon germanium, and germanium.

[00105] Example 11 may include the memory device of example 8 and/or some other example herein, wherein the transistor is a front-end-of-line (FEOL) transistor.

[00106] Example 12 may include the memory device of example 8 and/or some other example herein, wherein the transistor is a back-end-of-line (BEOL) transistor.

[00107] Example 13 may include the memory device of example 8 and/or some other example herein, wherein the channel comprises one or more of (1) zinc and oxygen, (2) indium and oxygen, (3) indium, tin, and oxygen, (4) aluminum, zinc, and oxygen, (5) indium, zinc, and oxygen, (6) indium, gallium, zinc, and oxygen, (7) gallium, zinc, and oxygen, (8) tin and oxygen, (9) cobalt and oxygen, (10) copper and oxygen, (11) copper and oxygen, or (12) titanium and oxygen.

[00108] Example 14 may include the memory device of example 8 and/or some other example herein, wherein the first material is an N-type NDR (NNDR) material.

[00109] Example 15 may include the memory device of example 14 and/or some other example herein, wherein the NNDR material comprises a resonant tunneling diode material.

[00110] Example 16 may include the memory device of example 8 and/or some other example herein, wherein the second material is a S-type NDR (SNDR) material.

[00111] Example 17 may include the memory device of example 16 and/or some other example herein, wherein the SNDR material comprises a threshold switch material.

[00112] Example 18 may include the memory device of example 8 and/or some other example herein, wherein the first material comprises one or more of niobium and oxygen, tantalum and oxygen, vanadium and oxygen, nickel and oxygen, or a chalcogenide.

[00113] Example 19 may include the memory device of example 8 and/or some other example herein, wherein the second material comprises one or more of niobium and oxygen, tantalum and oxygen, vanadium and oxygen, nickel and oxygen, or a chalcogenide.

[00114] Example 20 may include a device including a memory element, the memory element comprising: a first electrode; a first material on a first portion of the first electrode, the first material having a negative differential resistance (NDR); a second material on a second portion of the first electrode, the second material having a NDR; a second electrode on the first material; and a third electrode on the second material.

[00115] Example 21 may include the device of example 20 and/or some other example herein, wherein the first material is an N-type NDR (NNDR) material.

[00116] Example 22 may include the device of example 20 and/or some other example herein, wherein the second material is a S-type NDR (SNDR) material.

[00117] Example 23 may include the device of example 21 and/or some other example herein, wherein the NNDR material comprises a resonant tunneling diode material.

[00118] Example 24 may include the device of example 23 and/or some other example herein, wherein the SNDR material comprises a threshold switch material.

[00119] Example 25 may include the device of example 20 and/or some other example herein, wherein the first material comprises one or more of niobium and oxygen, tantalum and oxygen, vanadium and oxygen, nickel and oxygen, or a chalcogenide.

[00120] Example 26 may include the device of example 20 and/or some other example herein, wherein the second material comprises one or more of niobium and oxygen, tantalum and oxygen, vanadium and oxygen, nickel and oxygen, or a chalcogenide.

[00121] Example 27 may include an electronic device comprising: a memory element, comprising: a first electrode; a first material on a first portion of the first electrode, the first material having a negative differential resistance (NDR); a second material on a second portion of the first electrode, the second material having a NDR; a second electrode on the first material; and a third electrode on the second material.

[00122] Example 28 may include the electronic device of example 27 and/or some other example herein, wherein the first material is an N-type NDR (NNDR) material.

[00123] Example 29 may include the electronic device of example 28 and/or some other example herein, wherein the NNDR material comprises a resonant tunneling diode material.

[00124] Example 30 may include the electronic device of example 27 and/or some other example herein, wherein the second material is an S-type NDR (SNDR) material.

[00125] Example 31 may include the electronic device of example 29 and/or some other example herein, wherein the SNDR material comprises a threshold switch material.

[00126] Example 32 may include the electronic device of example 27 and/or some other example herein, wherein the first material comprises one or more of niobium and oxygen, tantalum and oxygen, vanadium and oxygen, nickel and oxygen, or a chalcogenide. [00127] Example 33 may include the electronic device of example 27 and/or some other example herein, wherein the second material comprises one or more of niobium and oxygen, tantalum and oxygen, vanadium and oxygen, nickel and oxygen, or a chalcogenide.

[00128] Example 34 may include an electronic device comprising: a memory device, comprising: a transistor comprising: a source, a drain, a channel, a gate, and a gate dielectric; a first contact on the source; a second contact on the drain; the gate in contact with the gate dielectric; and the gate dielectric in contact with the channel; a memory element comprising: a first electrode; a first material on a first portion of the first electrode, the first material having a negative differential resistance (NDR); a second material on a second portion of the first electrode, the second material having a NDR; a second electrode on the first material; and a third electrode on the second material; a third contact electrically connecting the second contact with the first electrode.

[00129] Example 35 may include the electronic device of example 34 and/or some other example herein, wherein the memory device includes a substrate, the substrate comprising silicon, silicon germanium, or germanium.

[00130] Example 36 may include the electronic device of example 34 and/or some other example herein, wherein the channel comprises silicon, silicon germanium, and germanium.

[00131] Example 37 may include the electronic device of example 34 and/or some other example herein, wherein the transistor is a front-end-of-line (FEOL) transistor.

[00132] Example 38 may include the electronic device of example 34 and/or some other example herein, wherein the transistor is a back-end-of-line (BEOL) transistor.

[00133] Example 39 may include the electronic device of example 34 and/or some other example herein, wherein the channel comprises one or more of (1) zinc and oxygen, (2) indium and oxygen, (3) indium, tin, and oxygen, (4) aluminum, zinc, and oxygen, (5) indium, zinc, and oxygen, (6) indium, gallium, zinc, and oxygen, (7) gallium, zinc, and oxygen, (8) tin and oxygen, (9) cobalt and oxygen, (10) copper and oxygen, (11) copper and oxygen, or (12) titanium and oxygen.

[00134] Example 40 may include the electronic device of example 34 and/or some other example herein, wherein the first material is an N-type NDR (NNDR) material.

[00135] Example 41 may include the electronic device of example 40 and/or some other example herein, wherein the NNDR material comprises a resonant tunneling diode material.

[00136] Example 42 may include the electronic device of example 34 and/or some other example herein, wherein the second material is a S-type NDR (SNDR) material. [00137] Example 43 may include the electronic device of example 42 and/or some other example herein, wherein the SNDR material comprises a threshold switch material.

[00138] Example 44 may include the electronic device of example 34 and/or some other example herein, wherein the first material comprises one or more of niobium and oxygen, tantalum and oxygen, vanadium and oxygen, nickel and oxygen, or a chalcogenide.

[00139] Example 45 may include the electronic device of example 34 and/or some other example herein, wherein the second material comprises one or more of niobium and oxygen, tantalum and oxygen, vanadium and oxygen, nickel and oxygen, or a chalcogenide.

[00140] Various features, aspects, and embodiments have been described herein. The features, aspects, and embodiments are susceptible to combination with one another as well as to variation and modification, as will be understood by those having skill in the art. The present disclosure should, therefore, be considered to encompass such combinations, variations, and modifications.

[00141] The terms and expressions which have been employed herein are used as terms of description and not of limitation, and there is no intention, in the use of such terms and expressions, of excluding any equivalents of the features shown and described (or portions thereof), and it is recognized that various modifications are possible within the scope of the claims. Other modifications, variations, and alternatives are also possible. Accordingly, the claims are intended to cover all such equivalents.

[00142] While the disclosure includes various embodiments, including at least a best mode, it is to be understood that many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the foregoing description. Accordingly, the disclosure is intended to embrace all such alternatives, modifications, and variations, which fall within the scope of the included claims. All matters disclosed herein or shown in the accompanying drawings are to be interpreted in an illustrative and non-limiting sense.

[00143] This written description uses examples to disclose certain embodiments of the disclosure, including the best mode, and also to enable any person skilled in the art to practice certain embodiments of the disclosure, including making and using any apparatus, devices or systems and the performance of any incorporated methods and processes. The patentable scope of certain embodiments of the disclosure is defined in the claims, and may include other examples that occur to those skilled in the art. Such other examples are intended to be within the scope of the claims if they have structural elements that do not differ from the literal language of the claims, or if they include equivalent structural elements with insubstantial differences from the literal language of the claims.