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Title:
MEMORY SYSTEM, MEMORY PERIPHERAL CIRCUIT, AND MEMORY CONTROL METHOD
Document Type and Number:
WIPO Patent Application WO/2015/174020
Kind Code:
A1
Abstract:
Provided is a memory system having memory cells and memory peripheral circuits, with the memory cells being divided into a first region in which high-speed writing is performed and a second region having a long data retention period. The memory peripheral circuits include an address circuit, a data writing circuit, a sense amp, and a programmable timing generation circuit, with the length of the writing activation period being set by the programmable timing generation circuit. Also provided is a memory control method whereby memory cells are divided into a first region in which high-speed writing is performed and a second region having a long data retention period, with the division period being set by means of configuration data.

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Inventors:
ASO SHINGO (JP)
SATORI KENICHI (JP)
Application Number:
PCT/JP2015/002164
Publication Date:
November 19, 2015
Filing Date:
April 21, 2015
Export Citation:
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Assignee:
SONY CORP (JP)
International Classes:
G11C11/15
Foreign References:
JP2008204581A2008-09-04
JP2007172819A2007-07-05
JP2012079367A2012-04-19
JP2012038371A2012-02-23
Attorney, Agent or Firm:
SUGIURA, Masatomo et al. (JP)
Masatomo Sugiura (JP)
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